Commit 207b7b2c9d9752e0f6478c30c29b7087f6e6cbb6

Authored by Wolfgang Denk
1 parent ac4cd59d59
Exists in master and in 55 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Get rid of duplicated file (see doc/README.SBC8560 instead)

Signed-off-by: Wolfgang Denk <wd@denx.de>

Showing 1 changed file with 0 additions and 53 deletions Side-by-side Diff

doc/README.sbc8560
1   -The port was tested on Wind River System Sbc8560 board <www.windriver.com>.
2   -U-Boot was installed on the flash memory of the CPU card (no the SODIMM).
3   -
4   -NOTE: Please configure uboot compile to the proper PCI frequency and
5   -setup the appropriate DIP switch settings.
6   -
7   -SBC8560 board:
8   -
9   -Make sure boards switches are set to their appropriate conditions.
10   -Refer to the Engineering Reference Guide ERG-00300-002. Of particular
11   -importance are: 1)Tthe settings for JP4 (JP4 1-3 and 2-4), which
12   -select the on-board FLASH device (Intel 28F128Jx); 2) The settings
13   -for the Clock SW9 (33 MHz or 66 MHz).
14   -
15   - Note: SW9 Settings: 66 MHz
16   - 4:1 ratio CCB clocks:SYSCLK
17   - 3:1 ration e500 Core:CCB
18   - pos1 - on, pos2 - on, pos3 - off, pos4 - on, pos5 - off, pos6 - on
19   - Note: SW9 Settings: 33 MHz
20   - 8:1 ratio CCB clocks:SYSCLK
21   - 3:1 ration e500 Core:CCB
22   - pos1 - on, pos2 - on, pos3 - on, pos4 - off, pos5 - off, pos6 - on
23   -
24   -
25   -Flashing the FLASH device with the "Wind River ICE":
26   -
27   -1) Properly connect and configure the Wind River ICE to the
28   - target JTAG port. This includes running the SBC8560 register script.
29   - Make sure target memory can be read and written.
30   -
31   -2) Build the u-boot image:
32   - make distclean
33   - make SBC8560_66_config or SBC8560_33_config
34   - make CROSS_COMPILE=.../ELDK3.0/ppc_8xx-/ all
35   -
36   - Note: reference is made to the ELDK3.0 compiler but any 85xx cross-compiler
37   - should suffice.
38   -
39   -3) Convert the uboot (.elf) file to a uboot.bin file (using visionClick converter).
40   - The bin file should be converted from fffc0000 to ffffffff
41   -
42   -4) Setup the Flash Utility (tools menu) for:
43   -
44   - Determine the clock speed of the PCI bus and set SW9 accordingly
45   - Note: the speed of the PCI bus defaults to the slowest PCI card
46   - PlayBack the "default" register file for the SBC8560
47   - Select the uboot.bin file with zero bias
48   - Select the initialize Target prior to programming
49   - Select the V28F640Jx (8192 x 8) 1 device FLASH Algorithm
50   - Select the erase base address from FFFC0000 to FFFFFFFF
51   - Select the start address from 0 with size of 4000
52   -
53   -5) Erase and Program