rockchip: rk3308: Add support for ROC-RK3308-CC board

ROC-RK3308-CC is a rk3308 based board designed by Firelfy, with eMMC and 256MB DDR3 and RTL8188 Wifi on board. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

rockchip: rk3308: Add support for ROC-RK3308-CC board
ROC-RK3308-CC is a rk3308 based board designed by Firelfy, with eMMC and 256MB DDR3 and RTL8188 Wifi on board. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Andy Yan · Kever Yang
1 parent 9ce3de1b18
Showing 7 changed files with 210 additions and 0 deletions Side-by-side Diff
arch/arm/mach-rockchip/rk3308/Kconfig
board/firefly/firefly-rk3308/Kconfig
board/firefly/firefly-rk3308/MAINTAINERS
board/firefly/firefly-rk3308/Makefile
board/firefly/firefly-rk3308/roc_cc_rk3308.c
configs/roc-cc-rk3308_defconfig
include/configs/firefly_rk3308.h
@@ -4,6 +4,10 @@
 	bool "EVB_RK3308"
 	select BOARD_LATE_INIT
  
+config TARGET_ROC_RK3308_CC
+       bool "Firefly roc-rk3308-cc"
+	select BOARD_LATE_INIT
+
 config SYS_SOC
 	default "rk3308"
  
@@ -18,6 +22,7 @@
  
  
 source "board/rockchip/evb_rk3308/Kconfig"
+source "board/firefly/firefly-rk3308/Kconfig"
  
 endif
+if TARGET_ROC_RK3308_CC
+
+config SYS_BOARD
+	default "firefly-rk3308"
+
+config SYS_VENDOR
+	default "firefly"
+
+config SYS_CONFIG_NAME
+	default "firefly_rk3308"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
+ROC-RK3308-CC
+M:      Andy Yan <andy.yan@rock-chips.com>
+S:      Maintained
+F:      board/firefly/firefly-rk3308/roc_cc_rk3308.c
+F:      configs/roc-cc-rk3308_defconfig
+#
+# (C) Copyright 2018 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= roc_cc_rk3308.o
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <adc.h>
+#include <asm/io.h>
+#include <asm/arch/grf_rk3308.h>
+#include <asm/arch-rockchip/hardware.h>
+
+#if defined(CONFIG_DEBUG_UART)
+#define GRF_BASE	0xff000000
+
+enum {
+	GPIO1C7_SHIFT		= 8,
+	GPIO1C7_MASK		= GENMASK(11, 8),
+	GPIO1C7_GPIO		= 0,
+	GPIO1C7_UART1_RTSN,
+	GPIO1C7_UART2_TX_M0,
+	GPIO1C7_SPI2_MOSI,
+	GPIO1C7_JTAG_TMS,
+
+	GPIO1C6_SHIFT		= 4,
+	GPIO1C6_MASK		= GENMASK(7, 4),
+	GPIO1C6_GPIO		= 0,
+	GPIO1C6_UART1_CTSN,
+	GPIO1C6_UART2_RX_M0,
+	GPIO1C6_SPI2_MISO,
+	GPIO1C6_JTAG_TCLK,
+
+	GPIO4D3_SHIFT           = 6,
+	GPIO4D3_MASK            = GENMASK(7, 6),
+	GPIO4D3_GPIO            = 0,
+	GPIO4D3_SDMMC_D3,
+	GPIO4D3_UART2_TX_M1,
+
+	GPIO4D2_SHIFT           = 4,
+	GPIO4D2_MASK            = GENMASK(5, 4),
+	GPIO4D2_GPIO            = 0,
+	GPIO4D2_SDMMC_D2,
+	GPIO4D2_UART2_RX_M1,
+
+	UART2_IO_SEL_SHIFT	= 2,
+	UART2_IO_SEL_MASK	= GENMASK(3, 2),
+	UART2_IO_SEL_M0		= 0,
+	UART2_IO_SEL_M1,
+	UART2_IO_SEL_USB,
+};
+
+void board_debug_uart_init(void)
+{
+	static struct rk3308_grf * const grf = (void *)GRF_BASE;
+
+	/* Enable early UART2 channel m0 on the rk3308 */
+	rk_clrsetreg(&grf->soc_con5, UART2_IO_SEL_MASK,
+		     UART2_IO_SEL_M0 << UART2_IO_SEL_SHIFT);
+	rk_clrsetreg(&grf->gpio1ch_iomux,
+		     GPIO1C6_MASK | GPIO1C7_MASK,
+		     GPIO1C6_UART2_RX_M0 << GPIO1C6_SHIFT |
+		     GPIO1C7_UART2_TX_M0 << GPIO1C7_SHIFT);
+}
+#endif
+
+#define KEY_DOWN_MIN_VAL        0
+#define KEY_DOWN_MAX_VAL        30
+
+int rockchip_dnl_key_pressed(void)
+{
+	unsigned int val;
+
+	if (adc_channel_single_shot("saradc", 1, &val)) {
+		printf("%s read adc key val failed\n", __func__);
+		return false;
+	}
+
+	if (val >= KEY_DOWN_MIN_VAL && val <= KEY_DOWN_MAX_VAL)
+		return true;
+	else
+		return false;
+}
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00600000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ROCKCHIP_RK3308=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_TARGET_ROC_RK3308_CC=y
+CONFIG_SPL_STACK_R_ADDR=0xc00000
+CONFIG_DEBUG_UART_BASE=0xFF0C0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=0
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_STACK_R=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3308-roc-cc"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_LZ4=y
+CONFIG_LZO=y
+CONFIG_ERRNO_STR=y
+# CONFIG_EFI_LOADER is not set
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __FIREFLY_RK3308_H
+#define __FIREFLY_RK3308_H
+
+#include <configs/rk3308_common.h>
+
+#define CONFIG_SUPPORT_EMMC_RPMB
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+			"stdout=serial,vidconsole\0" \
+			"stderr=serial,vidconsole\0"
+#undef CONFIG_CONSOLE_SCROLL_LINES
+#define CONFIG_CONSOLE_SCROLL_LINES            10
+
+#endif
...	...	@@ -4,6 +4,10 @@
4	4	bool "EVB_RK3308"
5	5	select BOARD_LATE_INIT
6	6
	7	+config TARGET_ROC_RK3308_CC
	8	+ bool "Firefly roc-rk3308-cc"
	9	+ select BOARD_LATE_INIT
	10	+
7	11	config SYS_SOC
8	12	default "rk3308"
9	13
...	...	@@ -18,6 +22,7 @@
18	22
19	23
20	24	source "board/rockchip/evb_rk3308/Kconfig"
	25	+source "board/firefly/firefly-rk3308/Kconfig"
21	26
22	27	endif
	1	+if TARGET_ROC_RK3308_CC
	2	+
	3	+config SYS_BOARD
	4	+ default "firefly-rk3308"
	5	+
	6	+config SYS_VENDOR
	7	+ default "firefly"
	8	+
	9	+config SYS_CONFIG_NAME
	10	+ default "firefly_rk3308"
	11	+
	12	+config BOARD_SPECIFIC_OPTIONS # dummy
	13	+ def_bool y
	14	+
	15	+endif
	1	+ROC-RK3308-CC
	2	+M: Andy Yan <andy.yan@rock-chips.com>
	3	+S: Maintained
	4	+F: board/firefly/firefly-rk3308/roc_cc_rk3308.c
	5	+F: configs/roc-cc-rk3308_defconfig
	1	+#
	2	+# (C) Copyright 2018 Rockchip Electronics Co., Ltd
	3	+#
	4	+# SPDX-License-Identifier: GPL-2.0+
	5	+#
	6	+
	7	+obj-y += roc_cc_rk3308.o
	1	+// SPDX-License-Identifier: GPL-2.0+
	2	+/*
	3	+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
	4	+ */
	5	+
	6	+#include <common.h>
	7	+#include <adc.h>
	8	+#include <asm/io.h>
	9	+#include <asm/arch/grf_rk3308.h>
	10	+#include <asm/arch-rockchip/hardware.h>
	11	+
	12	+#if defined(CONFIG_DEBUG_UART)
	13	+#define GRF_BASE 0xff000000
	14	+
	15	+enum {
	16	+ GPIO1C7_SHIFT = 8,
	17	+ GPIO1C7_MASK = GENMASK(11, 8),
	18	+ GPIO1C7_GPIO = 0,
	19	+ GPIO1C7_UART1_RTSN,
	20	+ GPIO1C7_UART2_TX_M0,
	21	+ GPIO1C7_SPI2_MOSI,
	22	+ GPIO1C7_JTAG_TMS,
	23	+
	24	+ GPIO1C6_SHIFT = 4,
	25	+ GPIO1C6_MASK = GENMASK(7, 4),
	26	+ GPIO1C6_GPIO = 0,
	27	+ GPIO1C6_UART1_CTSN,
	28	+ GPIO1C6_UART2_RX_M0,
	29	+ GPIO1C6_SPI2_MISO,
	30	+ GPIO1C6_JTAG_TCLK,
	31	+
	32	+ GPIO4D3_SHIFT = 6,
	33	+ GPIO4D3_MASK = GENMASK(7, 6),
	34	+ GPIO4D3_GPIO = 0,
	35	+ GPIO4D3_SDMMC_D3,
	36	+ GPIO4D3_UART2_TX_M1,
	37	+
	38	+ GPIO4D2_SHIFT = 4,
	39	+ GPIO4D2_MASK = GENMASK(5, 4),
	40	+ GPIO4D2_GPIO = 0,
	41	+ GPIO4D2_SDMMC_D2,
	42	+ GPIO4D2_UART2_RX_M1,
	43	+
	44	+ UART2_IO_SEL_SHIFT = 2,
	45	+ UART2_IO_SEL_MASK = GENMASK(3, 2),
	46	+ UART2_IO_SEL_M0 = 0,
	47	+ UART2_IO_SEL_M1,
	48	+ UART2_IO_SEL_USB,
	49	+};
	50	+
	51	+void board_debug_uart_init(void)
	52	+{
	53	+ static struct rk3308_grf * const grf = (void *)GRF_BASE;
	54	+
	55	+ /* Enable early UART2 channel m0 on the rk3308 */
	56	+ rk_clrsetreg(&grf->soc_con5, UART2_IO_SEL_MASK,
	57	+ UART2_IO_SEL_M0 << UART2_IO_SEL_SHIFT);
	58	+ rk_clrsetreg(&grf->gpio1ch_iomux,
	59	+ GPIO1C6_MASK \| GPIO1C7_MASK,
	60	+ GPIO1C6_UART2_RX_M0 << GPIO1C6_SHIFT \|
	61	+ GPIO1C7_UART2_TX_M0 << GPIO1C7_SHIFT);
	62	+}
	63	+#endif
	64	+
	65	+#define KEY_DOWN_MIN_VAL 0
	66	+#define KEY_DOWN_MAX_VAL 30
	67	+
	68	+int rockchip_dnl_key_pressed(void)
	69	+{
	70	+ unsigned int val;
	71	+
	72	+ if (adc_channel_single_shot("saradc", 1, &val)) {
	73	+ printf("%s read adc key val failed\n", __func__);
	74	+ return false;
	75	+ }
	76	+
	77	+ if (val >= KEY_DOWN_MIN_VAL && val <= KEY_DOWN_MAX_VAL)
	78	+ return true;
	79	+ else
	80	+ return false;
	81	+}
	1	+CONFIG_ARM=y
	2	+CONFIG_ARCH_ROCKCHIP=y
	3	+CONFIG_SYS_TEXT_BASE=0x00600000
	4	+CONFIG_SPL_LIBCOMMON_SUPPORT=y
	5	+CONFIG_SPL_LIBGENERIC_SUPPORT=y
	6	+CONFIG_SYS_MALLOC_F_LEN=0x2000
	7	+CONFIG_ROCKCHIP_RK3308=y
	8	+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
	9	+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
	10	+CONFIG_TARGET_ROC_RK3308_CC=y
	11	+CONFIG_SPL_STACK_R_ADDR=0xc00000
	12	+CONFIG_DEBUG_UART_BASE=0xFF0C0000
	13	+CONFIG_DEBUG_UART_CLOCK=24000000
	14	+CONFIG_DEBUG_UART=y
	15	+CONFIG_ANDROID_BOOT_IMAGE=y
	16	+CONFIG_FIT=y
	17	+CONFIG_FIT_VERBOSE=y
	18	+CONFIG_BOOTDELAY=0
	19	+CONFIG_SYS_CONSOLE_INFO_QUIET=y
	20	+# CONFIG_DISPLAY_CPUINFO is not set
	21	+CONFIG_SPL_STACK_R=y
	22	+# CONFIG_CMD_BDI is not set
	23	+# CONFIG_CMD_CONSOLE is not set
	24	+# CONFIG_CMD_ELF is not set
	25	+# CONFIG_CMD_IMI is not set
	26	+# CONFIG_CMD_XIMG is not set
	27	+# CONFIG_CMD_FLASH is not set
	28	+CONFIG_CMD_GPT=y
	29	+# CONFIG_CMD_LOADB is not set
	30	+# CONFIG_CMD_LOADS is not set
	31	+CONFIG_CMD_MMC=y
	32	+CONFIG_CMD_USB=y
	33	+CONFIG_CMD_USB_MASS_STORAGE=y
	34	+# CONFIG_CMD_ITEST is not set
	35	+# CONFIG_CMD_SETEXPR is not set
	36	+# CONFIG_CMD_MISC is not set
	37	+# CONFIG_DOS_PARTITION is not set
	38	+# CONFIG_ISO_PARTITION is not set
	39	+CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
	40	+CONFIG_SPL_OF_CONTROL=y
	41	+CONFIG_OF_LIVE=y
	42	+CONFIG_DEFAULT_DEVICE_TREE="rk3308-roc-cc"
	43	+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
	44	+CONFIG_REGMAP=y
	45	+CONFIG_SYSCON=y
	46	+CONFIG_CLK=y
	47	+# CONFIG_USB_FUNCTION_FASTBOOT is not set
	48	+CONFIG_ROCKCHIP_GPIO=y
	49	+CONFIG_SYS_I2C_ROCKCHIP=y
	50	+CONFIG_MMC_DW=y
	51	+CONFIG_MMC_DW_ROCKCHIP=y
	52	+CONFIG_DM_ETH=y
	53	+CONFIG_ETH_DESIGNWARE=y
	54	+CONFIG_GMAC_ROCKCHIP=y
	55	+CONFIG_PHY=y
	56	+CONFIG_PINCTRL=y
	57	+CONFIG_REGULATOR_PWM=y
	58	+CONFIG_DM_REGULATOR_FIXED=y
	59	+CONFIG_PWM_ROCKCHIP=y
	60	+CONFIG_RAM=y
	61	+CONFIG_DM_RESET=y
	62	+CONFIG_BAUDRATE=1500000
	63	+CONFIG_DEBUG_UART_SHIFT=2
	64	+CONFIG_DEBUG_UART_SKIP_INIT=y
	65	+CONFIG_SYSRESET=y
	66	+CONFIG_USB=y
	67	+CONFIG_USB_EHCI_HCD=y
	68	+CONFIG_USB_EHCI_GENERIC=y
	69	+CONFIG_USB_DWC2=y
	70	+CONFIG_USB_GADGET=y
	71	+CONFIG_USB_GADGET_DWC2_OTG=y
	72	+CONFIG_USB_GADGET_DOWNLOAD=y
	73	+CONFIG_SPL_TINY_MEMSET=y
	74	+CONFIG_LZ4=y
	75	+CONFIG_LZO=y
	76	+CONFIG_ERRNO_STR=y
	77	+# CONFIG_EFI_LOADER is not set
	1	+/* SPDX-License-Identifier: GPL-2.0+ */
	2	+/*
	3	+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
	4	+ */
	5	+
	6	+#ifndef __FIREFLY_RK3308_H
	7	+#define __FIREFLY_RK3308_H
	8	+
	9	+#include <configs/rk3308_common.h>
	10	+
	11	+#define CONFIG_SUPPORT_EMMC_RPMB
	12	+#define CONFIG_SYS_MMC_ENV_DEV 0
	13	+
	14	+#define ROCKCHIP_DEVICE_SETTINGS \
	15	+ "stdout=serial,vidconsole\0" \
	16	+ "stderr=serial,vidconsole\0"
	17	+#undef CONFIG_CONSOLE_SCROLL_LINES
	18	+#define CONFIG_CONSOLE_SCROLL_LINES 10
	19	+
	20	+#endif