Eric Lee / smarc-uboot

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Commit 20913018fbce5a2e3c93b6eeb56e67460e29542c

Authored by Tom Rini
2 parents a32d279129 6c739c5d8a
Exists in v2017.01-smarct4x and in 34 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

Merge branch 'master' of http://git.denx.de/u-boot-sunxi

Showing 40 changed files Side-by-side Diff

arch/arm/cpu/armv7/sunxi/board.c
Diff comments   View file @ 2091301
... ... @@ -46,28 +46,33 @@
46 46 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
47 47 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
48 48 #endif
49   - sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF2_UART0_TX);
50   - sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF4_UART0_RX);
  49 +#if defined(CONFIG_MACH_SUN8I)
  50 + sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0_TX);
  51 + sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0_RX);
  52 +#else
  53 + sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0_TX);
  54 + sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0_RX);
  55 +#endif
51 56 sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
52 57 #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
53   - sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
54   - sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
  58 + sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
  59 + sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
55 60 sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
56 61 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
57   - sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
58   - sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
  62 + sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
  63 + sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
59 64 sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
60 65 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
61   - sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH20_UART0_TX);
62   - sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH21_UART0_RX);
  66 + sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
  67 + sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
63 68 sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
64 69 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
65   - sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
66   - sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
  70 + sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
  71 + sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
67 72 sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
68 73 #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
69   - sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL2_R_UART_TX);
70   - sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL3_R_UART_RX);
  74 + sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
  75 + sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
71 76 sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
72 77 #else
73 78 #error Unsupported console port number. Please fix pin mux settings in board.c
arch/arm/cpu/armv7/sunxi/rsb.c
Diff comments   View file @ 2091301
... ... @@ -21,15 +21,15 @@
21 21 static void rsb_cfg_io(void)
22 22 {
23 23 #ifdef CONFIG_MACH_SUN8I
24   - sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL0_R_RSB_SCK);
25   - sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL1_R_RSB_SDA);
  24 + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
  25 + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
26 26 sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
27 27 sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
28 28 sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
29 29 sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
30 30 #elif defined CONFIG_MACH_SUN9I
31   - sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN0_R_RSB_SCK);
32   - sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN1_R_RSB_SDA);
  31 + sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
  32 + sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
33 33 sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
34 34 sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
35 35 sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
arch/arm/cpu/armv7/sunxi/usbc.c
Diff comments   View file @ 2091301
... ... @@ -41,6 +41,7 @@
41 41 int usb_rst_mask;
42 42 int ahb_clk_mask;
43 43 int gpio_vbus;
  44 + int gpio_vbus_det;
44 45 int irq;
45 46 int id;
46 47 } sunxi_usbc_hcd[] = {
... ... @@ -80,12 +81,6 @@
80 81  
81 82 static int enabled_hcd_count;
82 83  
83   -static bool use_axp_drivebus(int index)
84   -{
85   - return index == 0 &&
86   - strcmp(CONFIG_USB0_VBUS_PIN, "axp_drivebus") == 0;
87   -}
88   -
89 84 void *sunxi_usbc_get_io_base(int index)
90 85 {
91 86 switch (index) {
... ... @@ -102,9 +97,6 @@
102 97  
103 98 static int get_vbus_gpio(int index)
104 99 {
105   - if (use_axp_drivebus(index))
106   - return -1;
107   -
108 100 switch (index) {
109 101 case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_PIN);
110 102 case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN);
... ... @@ -113,6 +105,14 @@
113 105 return -1;
114 106 }
115 107  
  108 +static int get_vbus_detect_gpio(int index)
  109 +{
  110 + switch (index) {
  111 + case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_DET);
  112 + }
  113 + return -1;
  114 +}
  115 +
116 116 static void usb_phy_write(struct sunxi_usbc_hcd *sunxi_usbc, int addr,
117 117 int data, int len)
118 118 {
119 119  
120 120  
121 121  
122 122  
123 123  
... ... @@ -192,22 +192,35 @@
192 192 int sunxi_usbc_request_resources(int index)
193 193 {
194 194 struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
  195 + int ret = 0;
195 196  
196 197 sunxi_usbc->gpio_vbus = get_vbus_gpio(index);
197   - if (sunxi_usbc->gpio_vbus != -1)
198   - return gpio_request(sunxi_usbc->gpio_vbus, "usbc_vbus");
  198 + if (sunxi_usbc->gpio_vbus != -1) {
  199 + ret |= gpio_request(sunxi_usbc->gpio_vbus, "usbc_vbus");
  200 + ret |= gpio_direction_output(sunxi_usbc->gpio_vbus, 0);
  201 + }
199 202  
200   - return 0;
  203 + sunxi_usbc->gpio_vbus_det = get_vbus_detect_gpio(index);
  204 + if (sunxi_usbc->gpio_vbus_det != -1) {
  205 + ret |= gpio_request(sunxi_usbc->gpio_vbus_det, "usbc_vbus_det");
  206 + ret |= gpio_direction_input(sunxi_usbc->gpio_vbus_det);
  207 + }
  208 +
  209 + return ret;
201 210 }
202 211  
203 212 int sunxi_usbc_free_resources(int index)
204 213 {
205 214 struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
  215 + int ret = 0;
206 216  
207 217 if (sunxi_usbc->gpio_vbus != -1)
208   - return gpio_free(sunxi_usbc->gpio_vbus);
  218 + ret |= gpio_free(sunxi_usbc->gpio_vbus);
209 219  
210   - return 0;
  220 + if (sunxi_usbc->gpio_vbus_det != -1)
  221 + ret |= gpio_free(sunxi_usbc->gpio_vbus_det);
  222 +
  223 + return ret;
211 224 }
212 225  
213 226 void sunxi_usbc_enable(int index)
214 227  
215 228  
216 229  
... ... @@ -258,23 +271,39 @@
258 271 {
259 272 struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
260 273  
261   -#ifdef AXP_DRIVEBUS
262   - if (use_axp_drivebus(index))
263   - axp_drivebus_enable();
264   -#endif
265 274 if (sunxi_usbc->gpio_vbus != -1)
266   - gpio_direction_output(sunxi_usbc->gpio_vbus, 1);
  275 + gpio_set_value(sunxi_usbc->gpio_vbus, 1);
267 276 }
268 277  
269 278 void sunxi_usbc_vbus_disable(int index)
270 279 {
271 280 struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
272 281  
273   -#ifdef AXP_DRIVEBUS
274   - if (use_axp_drivebus(index))
275   - axp_drivebus_disable();
276   -#endif
277 282 if (sunxi_usbc->gpio_vbus != -1)
278   - gpio_direction_output(sunxi_usbc->gpio_vbus, 0);
  283 + gpio_set_value(sunxi_usbc->gpio_vbus, 0);
  284 +}
  285 +
  286 +int sunxi_usbc_vbus_detect(int index)
  287 +{
  288 + struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
  289 + int err, retries = 3;
  290 +
  291 + if (sunxi_usbc->gpio_vbus_det == -1) {
  292 + eprintf("Error: invalid vbus detection pin\n");
  293 + return -1;
  294 + }
  295 +
  296 + err = gpio_get_value(sunxi_usbc->gpio_vbus_det);
  297 + /*
  298 + * Vbus may have been provided by the board and just been turned of
  299 + * some milliseconds ago on reset, what we're measuring then is a
  300 + * residual charge on Vbus, sleep a bit and try again.
  301 + */
  302 + while (err > 0 && retries--) {
  303 + mdelay(100);
  304 + err = gpio_get_value(sunxi_usbc->gpio_vbus_det);
  305 + }
  306 +
  307 + return err;
279 308 }
arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
Diff comments   View file @ 2091301
... ... @@ -94,6 +94,13 @@
94 94 #define SUNXI_TWI0_BASE 0x01c2ac00
95 95 #define SUNXI_TWI1_BASE 0x01c2b000
96 96 #define SUNXI_TWI2_BASE 0x01c2b400
  97 +#ifdef CONFIG_MACH_SUN6I
  98 +#define SUNXI_TWI3_BASE 0x01c0b800
  99 +#endif
  100 +#ifdef CONFIG_MACH_SUN7I
  101 +#define SUNXI_TWI3_BASE 0x01c2b800
  102 +#define SUNXI_TWI4_BASE 0x01c2c000
  103 +#endif
97 104  
98 105 #define SUNXI_CAN_BASE 0x01c2bc00
99 106  
arch/arm/include/asm/arch-sunxi/gpio.h
Diff comments   View file @ 2091301
... ... @@ -84,7 +84,7 @@
84 84 #define GPIO_CFG_INDEX(pin) (((pin) & 0x1f) >> 3)
85 85 #define GPIO_CFG_OFFSET(pin) ((((pin) & 0x1f) & 0x7) << 2)
86 86  
87   -#define GPIO_DRV_INDEX(pin) (((pin) & 0x1f) >> 4)
  87 +#define GPIO_DRV_INDEX(pin) (((pin) & 0x1f) >> 4)
88 88 #define GPIO_DRV_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1)
89 89  
90 90 #define GPIO_PULL_INDEX(pin) (((pin) & 0x1f) >> 4)
91 91  
92 92  
93 93  
94 94  
95 95  
96 96  
97 97  
98 98  
99 99  
100 100  
101 101  
102 102  
103 103  
... ... @@ -142,71 +142,77 @@
142 142 #define SUNXI_GPIO_INPUT 0
143 143 #define SUNXI_GPIO_OUTPUT 1
144 144  
145   -#define SUNXI_GPA0_EMAC 2
146   -#define SUN6I_GPA0_GMAC 2
147   -#define SUN7I_GPA0_GMAC 5
  145 +#define SUNXI_GPA_EMAC 2
  146 +#define SUN6I_GPA_GMAC 2
  147 +#define SUN7I_GPA_GMAC 5
  148 +#define SUN6I_GPA_SDC2 5
  149 +#define SUN6I_GPA_SDC3 4
148 150  
149   -#define SUNXI_GPB0_TWI0 2
  151 +#define SUN4I_GPB_TWI0 2
  152 +#define SUN4I_GPB_TWI1 2
  153 +#define SUN5I_GPB_TWI1 2
  154 +#define SUN4I_GPB_TWI2 2
  155 +#define SUN5I_GPB_TWI2 2
  156 +#define SUN4I_GPB_UART0 2
  157 +#define SUN5I_GPB_UART0 2
150 158  
151   -#define SUN4I_GPB22_UART0_TX 2
152   -#define SUN4I_GPB23_UART0_RX 2
  159 +#define SUNXI_GPC_SDC2 3
  160 +#define SUN6I_GPC_SDC3 4
153 161  
154   -#define SUN5I_GPB19_UART0_TX 2
155   -#define SUN5I_GPB20_UART0_RX 2
  162 +#define SUN8I_GPD_SDC1 3
  163 +#define SUNXI_GPD_LCD0 2
  164 +#define SUNXI_GPD_LVDS0 3
156 165  
157   -#define SUNXI_GPC6_SDC2 3
  166 +#define SUN5I_GPE_SDC2 3
  167 +#define SUN8I_GPE_TWI2 3
158 168  
159   -#define SUNXI_GPD0_LCD0 2
160   -#define SUNXI_GPD0_LVDS0 3
  169 +#define SUNXI_GPF_SDC0 2
  170 +#define SUNXI_GPF_UART0 4
  171 +#define SUN8I_GPF_UART0 3
161 172  
162   -#define SUNXI_GPF0_SDC0 2
  173 +#define SUN4I_GPG_SDC1 4
  174 +#define SUN5I_GPG_SDC1 2
  175 +#define SUN6I_GPG_SDC1 2
  176 +#define SUN8I_GPG_SDC1 2
  177 +#define SUN6I_GPG_TWI3 2
  178 +#define SUN5I_GPG_UART1 4
163 179  
164   -#define SUNXI_GPF2_SDC0 2
  180 +#define SUN4I_GPH_SDC1 5
  181 +#define SUN6I_GPH_TWI0 2
  182 +#define SUN8I_GPH_TWI0 2
  183 +#define SUN6I_GPH_TWI1 2
  184 +#define SUN8I_GPH_TWI1 2
  185 +#define SUN6I_GPH_TWI2 2
  186 +#define SUN6I_GPH_UART0 2
165 187  
166   -#ifdef CONFIG_MACH_SUN8I
167   -#define SUNXI_GPF2_UART0_TX 3
168   -#define SUNXI_GPF4_UART0_RX 3
169   -#else
170   -#define SUNXI_GPF2_UART0_TX 4
171   -#define SUNXI_GPF4_UART0_RX 4
172   -#endif
  188 +#define SUNXI_GPI_SDC3 2
  189 +#define SUN7I_GPI_TWI3 3
  190 +#define SUN7I_GPI_TWI4 3
173 191  
174   -#define SUN4I_GPG0_SDC1 4
175   -
176   -#define SUN5I_GPG3_SDC1 2
177   -
178   -#define SUN5I_GPG3_UART1_TX 4
179   -#define SUN5I_GPG4_UART1_RX 4
180   -
181   -#define SUN4I_GPH22_SDC1 5
182   -
183   -#define SUN6I_GPH20_UART0_TX 2
184   -#define SUN6I_GPH21_UART0_RX 2
185   -
186   -#define SUN4I_GPI4_SDC3 2
187   -
188 192 #define SUN6I_GPL0_R_P2WI_SCK 3
189 193 #define SUN6I_GPL1_R_P2WI_SDA 3
190 194  
191   -#define SUN8I_GPL0_R_RSB_SCK 2
192   -#define SUN8I_GPL1_R_RSB_SDA 2
193   -#define SUN8I_GPL2_R_UART_TX 2
194   -#define SUN8I_GPL3_R_UART_RX 2
  195 +#define SUN8I_GPL_R_RSB 2
  196 +#define SUN8I_GPL_R_UART 2
195 197  
196   -#define SUN9I_GPN0_R_RSB_SCK 3
197   -#define SUN9I_GPN1_R_RSB_SDA 3
  198 +#define SUN9I_GPN_R_RSB 3
198 199  
199 200 /* GPIO pin pull-up/down config */
200 201 #define SUNXI_GPIO_PULL_DISABLE 0
201 202 #define SUNXI_GPIO_PULL_UP 1
202 203 #define SUNXI_GPIO_PULL_DOWN 2
203 204  
  205 +/* Virtual AXP0 GPIOs */
  206 +#define SUNXI_GPIO_AXP0_VBUS_DETECT 8
  207 +#define SUNXI_GPIO_AXP0_VBUS_ENABLE 9
  208 +
204 209 void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val);
205 210 void sunxi_gpio_set_cfgpin(u32 pin, u32 val);
206 211 int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset);
207 212 int sunxi_gpio_get_cfgpin(u32 pin);
208 213 int sunxi_gpio_set_drv(u32 pin, u32 val);
209 214 int sunxi_gpio_set_pull(u32 pin, u32 val);
  215 +int sunxi_name_to_gpio_bank(const char *name);
210 216 int sunxi_name_to_gpio(const char *name);
211 217 #define name_to_gpio(name) sunxi_name_to_gpio(name)
212 218  
arch/arm/include/asm/arch-sunxi/i2c.h
Diff comments   View file @ 2091301
... ... @@ -8,7 +8,22 @@
8 8  
9 9 #include <asm/arch/cpu.h>
10 10  
11   -#define CONFIG_I2C_MVTWSI_BASE SUNXI_TWI0_BASE
  11 +#ifdef CONFIG_I2C0_ENABLE
  12 +#define CONFIG_I2C_MVTWSI_BASE0 SUNXI_TWI0_BASE
  13 +#endif
  14 +#ifdef CONFIG_I2C1_ENABLE
  15 +#define CONFIG_I2C_MVTWSI_BASE1 SUNXI_TWI1_BASE
  16 +#endif
  17 +#ifdef CONFIG_I2C2_ENABLE
  18 +#define CONFIG_I2C_MVTWSI_BASE2 SUNXI_TWI2_BASE
  19 +#endif
  20 +#ifdef CONFIG_I2C3_ENABLE
  21 +#define CONFIG_I2C_MVTWSI_BASE3 SUNXI_TWI3_BASE
  22 +#endif
  23 +#ifdef CONFIG_I2C4_ENABLE
  24 +#define CONFIG_I2C_MVTWSI_BASE4 SUNXI_TWI4_BASE
  25 +#endif
  26 +
12 27 /* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */
13 28 #define CONFIG_SYS_TCLK 24000000
14 29  
arch/arm/include/asm/arch-sunxi/usbc.h
Diff comments   View file @ 2091301
... ... @@ -20,5 +20,6 @@
20 20 void sunxi_usbc_disable(int index);
21 21 void sunxi_usbc_vbus_enable(int index);
22 22 void sunxi_usbc_vbus_disable(int index);
  23 +int sunxi_usbc_vbus_detect(int index);
23 24 void sunxi_usbc_enable_squelch_detect(int index, int enable);
arch/arm/mach-kirkwood/include/mach/config.h
Diff comments   View file @ 2091301
... ... @@ -44,7 +44,7 @@
44 44 #define CONFIG_SYS_INIT_SP_ADDR 0xC8012000
45 45 #define CONFIG_NR_DRAM_BANKS_MAX 2
46 46  
47   -#define CONFIG_I2C_MVTWSI_BASE KW_TWSI_BASE
  47 +#define CONFIG_I2C_MVTWSI_BASE0 KW_TWSI_BASE
48 48 #define MV_UART_CONSOLE_BASE KW_UART0_BASE
49 49 #define MV_SATA_BASE KW_SATA_BASE
50 50 #define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET
... ... @@ -212,6 +212,25 @@
212 212 ---help---
213 213 See MMC0_CD_PIN help text.
214 214  
  215 +config MMC1_PINS
  216 + string "Pins for mmc1"
  217 + default ""
  218 + ---help---
  219 + Set the pins used for mmc1, when applicable. This takes a string in the
  220 + format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
  221 +
  222 +config MMC2_PINS
  223 + string "Pins for mmc2"
  224 + default ""
  225 + ---help---
  226 + See MMC1_PINS help text.
  227 +
  228 +config MMC3_PINS
  229 + string "Pins for mmc3"
  230 + default ""
  231 + ---help---
  232 + See MMC1_PINS help text.
  233 +
215 234 config MMC_SUNXI_SLOT_EXTRA
216 235 int "mmc extra slot number"
217 236 default -1
... ... @@ -229,7 +248,6 @@
229 248  
230 249 config USB0_VBUS_DET
231 250 string "Vbus detect pin for usb0 (otg)"
232   - depends on USB_MUSB_SUNXI
233 251 default ""
234 252 ---help---
235 253 Set the Vbus detect pin for usb0 (otg). This takes a string in the
... ... @@ -250,6 +268,44 @@
250 268 default "PH24" if MACH_SUN6I
251 269 ---help---
252 270 See USB1_VBUS_PIN help text.
  271 +
  272 +config I2C0_ENABLE
  273 + bool "Enable I2C/TWI controller 0"
  274 + default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
  275 + default n if MACH_SUN6I || MACH_SUN8I
  276 + ---help---
  277 + This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
  278 + its clock and setting up the bus. This is especially useful on devices
  279 + with slaves connected to the bus or with pins exposed through e.g. an
  280 + expansion port/header.
  281 +
  282 +config I2C1_ENABLE
  283 + bool "Enable I2C/TWI controller 1"
  284 + default n
  285 + ---help---
  286 + See I2C0_ENABLE help text.
  287 +
  288 +config I2C2_ENABLE
  289 + bool "Enable I2C/TWI controller 2"
  290 + default n
  291 + ---help---
  292 + See I2C0_ENABLE help text.
  293 +
  294 +if MACH_SUN6I || MACH_SUN7I
  295 +config I2C3_ENABLE
  296 + bool "Enable I2C/TWI controller 3"
  297 + default n
  298 + ---help---
  299 + See I2C0_ENABLE help text.
  300 +endif
  301 +
  302 +if MACH_SUN7I
  303 +config I2C4_ENABLE
  304 + bool "Enable I2C/TWI controller 4"
  305 + default n
  306 + ---help---
  307 + See I2C0_ENABLE help text.
  308 +endif
253 309  
254 310 config VIDEO
255 311 boolean "Enable graphical uboot console on HDMI, LCD or VGA"
board/sunxi/MAINTAINERS
Diff comments   View file @ 2091301
... ... @@ -42,15 +42,18 @@
42 42 A20-OLINUXINO-LIME BOARD
43 43 M: FUKAUMI Naoki <naobsd@gmail.com>
44 44 S: Maintained
45   -F: board/sunxi/dram_a20_olinuxino_l.c
46 45 F: configs/A20-OLinuXino-Lime_defconfig
47 46  
48 47 A20-OLINUXINO-LIME2 BOARD
49 48 M: Iain Paton <ipaton0@gmail.com>
50 49 S: Maintained
51   -F: board/sunxi/dram_a20_olinuxino_l2.c
52 50 F: configs/A20-OLinuXino-Lime2_defconfig
53 51  
  52 +AINOL AW1 BOARD
  53 +M: Paul Kocialkowski <contact@paulk.fr>
  54 +S: Maintained
  55 +F: configs/Ainol_AW1_defconfig
  56 +
54 57 AMPE A76 BOARD
55 58 M: Paul Kocialkowski <contact@paulk.fr>
56 59 S: Maintained
57 60  
... ... @@ -84,11 +87,20 @@
84 87 S: Maintained
85 88 F: configs/Hummingbird_A31_defconfig
86 89  
87   -INET-86VS BOARD
  90 +INET 3F BOARD
  91 +M: Paul Kocialkowski <contact@paulk.fr>
  92 +S: Maintained
  93 +F: configs/iNet_3F_defconfig
  94 +
  95 +INET 3W BOARD
  96 +M: Paul Kocialkowski <contact@paulk.fr>
  97 +S: Maintained
  98 +F: configs/iNet_3W_defconfig
  99 +
  100 +INET 86VS BOARD
88 101 M: Michal Suchanek <hramrach@gmail.com>
89 102 S: Maintained
90   -F: board/sunxi/dram_inet_86vs.c
91   -F: configs/Inet_86VS_defconfig
  103 +F: configs/iNet_86VS_defconfig
92 104  
93 105 IPPO-Q8H-V5 BOARD
94 106 M: Chen-Yu Tsai <wens@csie.org>
... ... @@ -120,6 +132,11 @@
120 132 S: Maintained
121 133 F: configs/Mele_M5_defconfig
122 134  
  135 +MIXTILE-LOFTQ BOARD
  136 +M: Phil Han <pengphei@sina.com>
  137 +S: Maintained
  138 +F: configs/mixtile_loftq_defconfig
  139 +
123 140 MK808C BOARD
124 141 M: Marcus Cooper <codekipper@gmail.com>
125 142 S: Maintained
... ... @@ -144,4 +161,9 @@
144 161 M: Aleksei Mamlin <mamlinav@gmail.com>
145 162 S: Maintained
146 163 F: configs/Wexler_TAB7200_defconfig
  164 +
  165 +YONES TOPTECH BD1078 BOARD
  166 +M: Paul Kocialkowski <contact@paulk.fr>
  167 +S: Maintained
  168 +F: configs/Yones_Toptech_BD1078_defconfig
... ... @@ -71,42 +71,163 @@
71 71 static void mmc_pinmux_setup(int sdc)
72 72 {
73 73 unsigned int pin;
  74 + __maybe_unused int pins;
74 75  
75 76 switch (sdc) {
76 77 case 0:
77   - /* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */
  78 + /* SDC0: PF0-PF5 */
78 79 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
79   - sunxi_gpio_set_cfgpin(pin, SUNXI_GPF0_SDC0);
  80 + sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
80 81 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
81 82 sunxi_gpio_set_drv(pin, 2);
82 83 }
83 84 break;
84 85  
85 86 case 1:
86   - /* CMD-PG3, CLK-PG4, D0~D3-PG5-8 */
  87 + pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
  88 +
  89 +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
  90 + if (pins == SUNXI_GPIO_H) {
  91 + /* SDC1: PH22-PH-27 */
  92 + for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
  93 + sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
  94 + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  95 + sunxi_gpio_set_drv(pin, 2);
  96 + }
  97 + } else {
  98 + /* SDC1: PG0-PG5 */
  99 + for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
  100 + sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
  101 + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  102 + sunxi_gpio_set_drv(pin, 2);
  103 + }
  104 + }
  105 +#elif defined(CONFIG_MACH_SUN5I)
  106 + /* SDC1: PG3-PG8 */
87 107 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
88   - sunxi_gpio_set_cfgpin(pin, SUN5I_GPG3_SDC1);
  108 + sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
89 109 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
90 110 sunxi_gpio_set_drv(pin, 2);
91 111 }
  112 +#elif defined(CONFIG_MACH_SUN6I)
  113 + /* SDC1: PG0-PG5 */
  114 + for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
  115 + sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
  116 + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  117 + sunxi_gpio_set_drv(pin, 2);
  118 + }
  119 +#elif defined(CONFIG_MACH_SUN8I)
  120 + if (pins == SUNXI_GPIO_D) {
  121 + /* SDC1: PD2-PD7 */
  122 + for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
  123 + sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
  124 + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  125 + sunxi_gpio_set_drv(pin, 2);
  126 + }
  127 + } else {
  128 + /* SDC1: PG0-PG5 */
  129 + for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
  130 + sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
  131 + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  132 + sunxi_gpio_set_drv(pin, 2);
  133 + }
  134 + }
  135 +#endif
92 136 break;
93 137  
94 138 case 2:
95   - /* CMD-PC6, CLK-PC7, D0-PC8, D1-PC9, D2-PC10, D3-PC11 */
  139 + pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
  140 +
  141 +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
  142 + /* SDC2: PC6-PC11 */
96 143 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
97   - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC6_SDC2);
  144 + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
98 145 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
99 146 sunxi_gpio_set_drv(pin, 2);
100 147 }
  148 +#elif defined(CONFIG_MACH_SUN5I)
  149 + if (pins == SUNXI_GPIO_E) {
  150 + /* SDC2: PE4-PE9 */
  151 + for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
  152 + sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
  153 + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  154 + sunxi_gpio_set_drv(pin, 2);
  155 + }
  156 + } else {
  157 + /* SDC2: PC6-PC15 */
  158 + for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
  159 + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  160 + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  161 + sunxi_gpio_set_drv(pin, 2);
  162 + }
  163 + }
  164 +#elif defined(CONFIG_MACH_SUN6I)
  165 + if (pins == SUNXI_GPIO_A) {
  166 + /* SDC2: PA9-PA14 */
  167 + for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
  168 + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
  169 + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  170 + sunxi_gpio_set_drv(pin, 2);
  171 + }
  172 + } else {
  173 + /* SDC2: PC6-PC15, PC24 */
  174 + for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
  175 + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  176 + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  177 + sunxi_gpio_set_drv(pin, 2);
  178 + }
  179 +
  180 + sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
  181 + sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
  182 + sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
  183 + }
  184 +#elif defined(CONFIG_MACH_SUN8I)
  185 + /* SDC2: PC5-PC6, PC8-PC16 */
  186 + for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
  187 + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  188 + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  189 + sunxi_gpio_set_drv(pin, 2);
  190 + }
  191 +
  192 + for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
  193 + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  194 + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  195 + sunxi_gpio_set_drv(pin, 2);
  196 + }
  197 +#endif
101 198 break;
102 199  
103 200 case 3:
104   - /* CMD-PI4, CLK-PI5, D0~D3-PI6~9 : 2 */
  201 + pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
  202 +
  203 +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
  204 + /* SDC3: PI4-PI9 */
105 205 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
106   - sunxi_gpio_set_cfgpin(pin, SUN4I_GPI4_SDC3);
  206 + sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
107 207 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
108 208 sunxi_gpio_set_drv(pin, 2);
109 209 }
  210 +#elif defined(CONFIG_MACH_SUN6I)
  211 + if (pins == SUNXI_GPIO_A) {
  212 + /* SDC3: PA9-PA14 */
  213 + for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
  214 + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
  215 + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  216 + sunxi_gpio_set_drv(pin, 2);
  217 + }
  218 + } else {
  219 + /* SDC3: PC6-PC15, PC24 */
  220 + for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
  221 + sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
  222 + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  223 + sunxi_gpio_set_drv(pin, 2);
  224 + }
  225 +
  226 + sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
  227 + sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
  228 + sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
  229 + }
  230 +#endif
110 231 break;
111 232  
112 233 default:
113 234  
... ... @@ -155,9 +276,82 @@
155 276  
156 277 void i2c_init_board(void)
157 278 {
158   - sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPB0_TWI0);
159   - sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPB0_TWI0);
  279 +#ifdef CONFIG_I2C0_ENABLE
  280 +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
  281 + sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
  282 + sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
160 283 clock_twi_onoff(0, 1);
  284 +#elif defined(CONFIG_MACH_SUN6I)
  285 + sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
  286 + sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
  287 + clock_twi_onoff(0, 1);
  288 +#elif defined(CONFIG_MACH_SUN8I)
  289 + sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
  290 + sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
  291 + clock_twi_onoff(0, 1);
  292 +#endif
  293 +#endif
  294 +
  295 +#ifdef CONFIG_I2C1_ENABLE
  296 +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
  297 + sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
  298 + sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
  299 + clock_twi_onoff(1, 1);
  300 +#elif defined(CONFIG_MACH_SUN5I)
  301 + sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
  302 + sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
  303 + clock_twi_onoff(1, 1);
  304 +#elif defined(CONFIG_MACH_SUN6I)
  305 + sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
  306 + sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
  307 + clock_twi_onoff(1, 1);
  308 +#elif defined(CONFIG_MACH_SUN8I)
  309 + sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
  310 + sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
  311 + clock_twi_onoff(1, 1);
  312 +#endif
  313 +#endif
  314 +
  315 +#ifdef CONFIG_I2C2_ENABLE
  316 +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
  317 + sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
  318 + sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
  319 + clock_twi_onoff(2, 1);
  320 +#elif defined(CONFIG_MACH_SUN5I)
  321 + sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
  322 + sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
  323 + clock_twi_onoff(2, 1);
  324 +#elif defined(CONFIG_MACH_SUN6I)
  325 + sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
  326 + sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
  327 + clock_twi_onoff(2, 1);
  328 +#elif defined(CONFIG_MACH_SUN8I)
  329 + sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
  330 + sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
  331 + clock_twi_onoff(2, 1);
  332 +#endif
  333 +#endif
  334 +
  335 +#ifdef CONFIG_I2C3_ENABLE
  336 +#if defined(CONFIG_MACH_SUN6I)
  337 + sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
  338 + sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
  339 + clock_twi_onoff(3, 1);
  340 +#elif defined(CONFIG_MACH_SUN7I)
  341 + sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
  342 + sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
  343 + clock_twi_onoff(3, 1);
  344 +#endif
  345 +#endif
  346 +
  347 +#ifdef CONFIG_I2C4_ENABLE
  348 +#if defined(CONFIG_MACH_SUN7I)
  349 + sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
  350 + sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
  351 + clock_twi_onoff(4, 1);
  352 +#endif
  353 +#endif
  354 +
161 355 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
162 356 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
163 357 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
164 358  
165 359  
166 360  
167 361  
168 362  
... ... @@ -241,23 +435,41 @@
241 435 };
242 436 #endif
243 437  
  438 +#ifdef CONFIG_USB_GADGET
  439 +int g_dnl_board_usb_cable_connected(void)
  440 +{
  441 + return sunxi_usbc_vbus_detect(0);
  442 +}
  443 +#endif
  444 +
244 445 #ifdef CONFIG_MISC_INIT_R
245 446 int misc_init_r(void)
246 447 {
  448 + char serial_string[17] = { 0 };
247 449 unsigned int sid[4];
  450 + uint8_t mac_addr[6];
  451 + int ret;
248 452  
249   - if (!getenv("ethaddr") && sunxi_get_sid(sid) == 0 &&
250   - sid[0] != 0 && sid[3] != 0) {
251   - uint8_t mac_addr[6];
  453 + ret = sunxi_get_sid(sid);
  454 + if (ret == 0 && sid[0] != 0 && sid[3] != 0) {
  455 + if (!getenv("ethaddr")) {
  456 + /* Non OUI / registered MAC address */
  457 + mac_addr[0] = 0x02;
  458 + mac_addr[1] = (sid[0] >> 0) & 0xff;
  459 + mac_addr[2] = (sid[3] >> 24) & 0xff;
  460 + mac_addr[3] = (sid[3] >> 16) & 0xff;
  461 + mac_addr[4] = (sid[3] >> 8) & 0xff;
  462 + mac_addr[5] = (sid[3] >> 0) & 0xff;
252 463  
253   - mac_addr[0] = 0x02; /* Non OUI / registered MAC address */
254   - mac_addr[1] = (sid[0] >> 0) & 0xff;
255   - mac_addr[2] = (sid[3] >> 24) & 0xff;
256   - mac_addr[3] = (sid[3] >> 16) & 0xff;
257   - mac_addr[4] = (sid[3] >> 8) & 0xff;
258   - mac_addr[5] = (sid[3] >> 0) & 0xff;
  464 + eth_setenv_enetaddr("ethaddr", mac_addr);
  465 + }
259 466  
260   - eth_setenv_enetaddr("ethaddr", mac_addr);
  467 + if (!getenv("serial#")) {
  468 + snprintf(serial_string, sizeof(serial_string),
  469 + "%08x%08x", sid[0], sid[3]);
  470 +
  471 + setenv("serial#", serial_string);
  472 + }
261 473 }
262 474  
263 475 #if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET)
... ... @@ -39,45 +39,45 @@
39 39 if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
40 40 continue;
41 41 #endif
42   - sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC);
  42 + sunxi_gpio_set_cfgpin(pin, SUN7I_GPA_GMAC);
43 43 sunxi_gpio_set_drv(pin, 3);
44 44 }
45 45 #elif defined CONFIG_RGMII
46 46 /* Configure sun6i RGMII mode pin mux settings */
47 47 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) {
48   - sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
  48 + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
49 49 sunxi_gpio_set_drv(pin, 3);
50 50 }
51 51 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
52   - sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
  52 + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
53 53 sunxi_gpio_set_drv(pin, 3);
54 54 }
55 55 for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) {
56   - sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
  56 + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
57 57 sunxi_gpio_set_drv(pin, 3);
58 58 }
59 59 for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) {
60   - sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
  60 + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
61 61 sunxi_gpio_set_drv(pin, 3);
62 62 }
63 63 #elif defined CONFIG_GMII
64 64 /* Configure sun6i GMII mode pin mux settings */
65 65 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) {
66   - sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
  66 + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
67 67 sunxi_gpio_set_drv(pin, 2);
68 68 }
69 69 #else
70 70 /* Configure sun6i MII mode pin mux settings */
71 71 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++)
72   - sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
  72 + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
73 73 for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++)
74   - sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
  74 + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
75 75 for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++)
76   - sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
  76 + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
77 77 for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++)
78   - sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
  78 + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
79 79 for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)
80   - sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
  80 + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
81 81 #endif
82 82  
83 83 #ifdef CONFIG_RGMII
configs/A20-OLinuXino-Lime2_defconfig
Diff comments   View file @ 2091301
1 1 CONFIG_SPL=y
2 2 CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI"
3 3 CONFIG_FDTFILE="sun7i-a20-olinuxino-lime2.dtb"
  4 +CONFIG_MMC0_CD_PIN="PH1"
  5 +CONFIG_USB0_VBUS_PIN="PC17"
  6 +CONFIG_USB0_VBUS_DET="PH5"
4 7 CONFIG_ARM=y
5 8 CONFIG_ARCH_SUNXI=y
6 9 CONFIG_MACH_SUN7I=y
configs/Ainol_AW1_defconfig
Diff comments   View file @ 2091301
  1 +# The Ainol AW1 is an A20 based tablet with a 800x480 lcd screen, sdio wifi,
  2 +# volume up/down and home buttons, micro-sd slot, micro usb (otg), headphones
  3 +# connector and a SPCI modem connector.
  4 +#
  5 +# Also see: http://linux-sunxi.org/Ainol_AW1
  6 +CONFIG_SPL=y
  7 +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
  8 +CONFIG_FDTFILE="sun7i-a20-ainol-aw1.dtb"
  9 +CONFIG_MMC0_CD_PIN="PH1"
  10 +CONFIG_USB_MUSB_SUNXI=y
  11 +CONFIG_USB0_VBUS_PIN="PB9"
  12 +CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
  13 +CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:40000,le:87,ri:112,up:38,lo:141,hs:1,vs:1,sync:3,vmode:0"
  14 +CONFIG_VIDEO_LCD_POWER="PH8"
  15 +CONFIG_VIDEO_LCD_BL_EN="PH7"
  16 +CONFIG_VIDEO_LCD_BL_PWM="PB2"
  17 +CONFIG_ARM=y
  18 +CONFIG_ARCH_SUNXI=y
  19 +CONFIG_MACH_SUN7I=y
  20 +CONFIG_DRAM_CLK=432
  21 +CONFIG_DRAM_ZQ=123
  22 +CONFIG_DRAM_EMR1=4
configs/Ampe_A76_defconfig
Diff comments   View file @ 2091301
1 1 CONFIG_SPL=y
2 2 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER"
3 3 CONFIG_FDTFILE="sun5i-a13-ampe-a76.dtb"
  4 +CONFIG_MMC0_CD_PIN="PG0"
4 5 CONFIG_USB_MUSB_SUNXI=y
5 6 CONFIG_USB0_VBUS_PIN="PG12"
6   -CONFIG_USB0_VBUS_DET="PG01"
  7 +CONFIG_USB0_VBUS_DET="PG1"
7 8 CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:82,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
8 9 CONFIG_VIDEO_LCD_POWER="AXP0-0"
9 10 CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
configs/Cubieboard2_defconfig
Diff comments   View file @ 2091301
1 1 CONFIG_SPL=y
2 2 CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
3 3 CONFIG_FDTFILE="sun7i-a20-cubieboard2.dtb"
  4 +CONFIG_MMC0_CD_PIN="PH1"
4 5 CONFIG_ARM=y
5 6 CONFIG_ARCH_SUNXI=y
6 7 CONFIG_MACH_SUN7I=y
configs/Inet_86VS_defconfig
View file @ 2091301
1   -CONFIG_SPL=y
2   -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
3   -CONFIG_FDTFILE="sun5i-a13-inet-86vs.dtb"
4   -CONFIG_USB_MUSB_SUNXI=y
5   -CONFIG_USB0_VBUS_PIN="PG12"
6   -CONFIG_USB0_VBUS_DET="PG1"
7   -CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
8   -CONFIG_VIDEO_LCD_POWER="AXP0-0"
9   -CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
10   -CONFIG_VIDEO_LCD_BL_PWM="PB2"
11   -CONFIG_ARM=y
12   -CONFIG_ARCH_SUNXI=y
13   -CONFIG_MACH_SUN5I=y
14   -CONFIG_DRAM_CLK=408
15   -CONFIG_DRAM_ZQ=123
16   -CONFIG_DRAM_EMR1=4
configs/Ippo_q8h_v1_2_defconfig
Diff comments   View file @ 2091301
... ... @@ -2,8 +2,8 @@
2 2 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
3 3 CONFIG_FDTFILE="sun8i-a23-ippo-q8h-v1.2.dtb"
4 4 CONFIG_USB_MUSB_SUNXI=y
5   -CONFIG_USB0_VBUS_PIN="axp_drivebus"
6   -CONFIG_USB0_VBUS_DET="axp_vbus_detect"
  5 +CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
  6 +CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
7 7 CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:167,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0"
8 8 CONFIG_VIDEO_LCD_DCLK_PHASE=0
9 9 CONFIG_VIDEO_LCD_POWER="PH7"
configs/Ippo_q8h_v5_defconfig
Diff comments   View file @ 2091301
... ... @@ -2,8 +2,8 @@
2 2 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
3 3 CONFIG_FDTFILE="sun8i-a23-ippo-q8h-v5.dtb"
4 4 CONFIG_USB_MUSB_SUNXI=y
5   -CONFIG_USB0_VBUS_PIN="axp_drivebus"
6   -CONFIG_USB0_VBUS_DET="axp_vbus_detect"
  5 +CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
  6 +CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
7 7 CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:168,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0"
8 8 CONFIG_VIDEO_LCD_DCLK_PHASE=0
9 9 CONFIG_VIDEO_LCD_POWER="PH7"
configs/TZX-Q8-713B7_defconfig
Diff comments   View file @ 2091301
1 1 CONFIG_SPL=y
2 2 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER"
3 3 CONFIG_FDTFILE="sun5i-a13-tzx-q8-713b7.dtb"
  4 +CONFIG_MMC0_CD_PIN="PG0"
4 5 CONFIG_USB_MUSB_SUNXI=y
5 6 CONFIG_USB0_VBUS_PIN="PG12"
6 7 CONFIG_USB0_VBUS_DET="PG1"
configs/Yones_Toptech_BD1078_defconfig
Diff comments   View file @ 2091301
  1 +# The Yones Toptech BD1078 is an A20 based 10" tablet with a 1024x600 lcd
  2 +# screen, volume up/down and back buttons, headphones jack, mini hdmi, micro
  3 +# usb (otg), micro usb (host), external micro-sd slot and a separate internal
  4 +# micro-sd slot.
  5 +#
  6 +# Also see: http://linux-sunxi.org/Yones_Toptech_BD1078
  7 +CONFIG_SPL=y
  8 +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
  9 +CONFIG_FDTFILE="sun7i-a20-yones-toptech-bd1078.dtb"
  10 +CONFIG_MMC_SUNXI_SLOT_EXTRA=1
  11 +CONFIG_MMC0_CD_PIN="PH1"
  12 +CONFIG_MMC1_CD_PIN="PH2"
  13 +CONFIG_MMC1_PINS="PH"
  14 +CONFIG_USB_MUSB_SUNXI=y
  15 +CONFIG_USB0_VBUS_PIN="PB9"
  16 +CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
  17 +CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:24,pclk_khz:63000,le:32,ri:287,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0"
  18 +CONFIG_VIDEO_LCD_DCLK_PHASE=0
  19 +CONFIG_VIDEO_LCD_PANEL_LVDS=y
  20 +CONFIG_VIDEO_LCD_POWER="PH8"
  21 +CONFIG_VIDEO_LCD_BL_EN="PH7"
  22 +CONFIG_VIDEO_LCD_BL_PWM="PB2"
  23 +CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW=n
  24 +CONFIG_ARM=y
  25 +CONFIG_ARCH_SUNXI=y
  26 +CONFIG_MACH_SUN7I=y
  27 +CONFIG_DRAM_CLK=408
  28 +CONFIG_DRAM_ZQ=127
  29 +CONFIG_DRAM_EMR1=4
configs/iNet_3F_defconfig
Diff comments   View file @ 2091301
  1 +# The iNet 3F is an A10 tablet with 1GiB RAM and a 1024x768 screen.
  2 +# Also see: http://linux-sunxi.org/INet_3F
  3 +CONFIG_SPL=y
  4 +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
  5 +CONFIG_FDTFILE="sun4i-a10-inet-3f.dtb"
  6 +CONFIG_MMC0_CD_PIN="PH1"
  7 +CONFIG_USB_MUSB_SUNXI=y
  8 +CONFIG_USB0_VBUS_PIN="PB9"
  9 +CONFIG_USB0_VBUS_DET="PH5"
  10 +CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:100000,le:799,ri:260,up:15,lo:16,hs:1,vs:1,sync:3,vmode:0"
  11 +CONFIG_VIDEO_LCD_PANEL_LVDS=y
  12 +CONFIG_VIDEO_LCD_POWER="PH8"
  13 +CONFIG_VIDEO_LCD_BL_EN="PH7"
  14 +CONFIG_VIDEO_LCD_BL_PWM="PB2"
  15 +CONFIG_ARM=y
  16 +CONFIG_ARCH_SUNXI=y
  17 +CONFIG_MACH_SUN4I=y
  18 +CONFIG_DRAM_CLK=432
  19 +CONFIG_DRAM_ZQ=123
  20 +CONFIG_DRAM_EMR1=4
configs/iNet_3W_defconfig
Diff comments   View file @ 2091301
  1 +# The iNet 3W is an A10 tablet with 1GiB RAM and a 1024x768 screen.
  2 +# Also see: http://linux-sunxi.org/INet_3W
  3 +CONFIG_SPL=y
  4 +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
  5 +CONFIG_FDTFILE="sun4i-a10-inet-3w.dtb"
  6 +CONFIG_MMC0_CD_PIN="PH20"
  7 +CONFIG_USB_MUSB_SUNXI=y
  8 +CONFIG_USB0_VBUS_PIN="PB9"
  9 +CONFIG_USB0_VBUS_DET="PH5"
  10 +CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:24,pclk_khz:65000,le:159,ri:160,up:22,lo:15,hs:1,vs:1,sync:3,vmode:0"
  11 +CONFIG_VIDEO_LCD_POWER="PH8"
  12 +CONFIG_VIDEO_LCD_BL_EN="PH7"
  13 +CONFIG_VIDEO_LCD_BL_PWM="PB2"
  14 +CONFIG_ARM=y
  15 +CONFIG_ARCH_SUNXI=y
  16 +CONFIG_MACH_SUN4I=y
  17 +CONFIG_DRAM_CLK=408
  18 +CONFIG_DRAM_ZQ=127
  19 +CONFIG_DRAM_EMR1=4
configs/iNet_86VS_defconfig
Diff comments   View file @ 2091301
  1 +CONFIG_SPL=y
  2 +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
  3 +CONFIG_FDTFILE="sun5i-a13-inet-86vs.dtb"
  4 +CONFIG_USB_MUSB_SUNXI=y
  5 +CONFIG_USB0_VBUS_PIN="PG12"
  6 +CONFIG_USB0_VBUS_DET="PG1"
  7 +CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
  8 +CONFIG_VIDEO_LCD_POWER="AXP0-0"
  9 +CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
  10 +CONFIG_VIDEO_LCD_BL_PWM="PB2"
  11 +CONFIG_ARM=y
  12 +CONFIG_ARCH_SUNXI=y
  13 +CONFIG_MACH_SUN5I=y
  14 +CONFIG_DRAM_CLK=408
  15 +CONFIG_DRAM_ZQ=123
  16 +CONFIG_DRAM_EMR1=4
configs/mixtile_loftq_defconfig
Diff comments   View file @ 2091301
  1 +# The Mixtile LOFT-Q is an A31 based board with 2G RAM, 8G EMMC, sdio wifi,
  2 +# 1Gbit ethernet, HDMI display, toslink audio plug, 4 USB2.0 port, external
  3 +# USB2SATA connector, sd card plug, 3x60 external fpic expansion connector,
  4 +# NXP JN5168 zigbee gw, remote support.
  5 +#
  6 +# Also see http://focalcrest.com/en/pc.html#pro02
  7 +CONFIG_SPL=y
  8 +CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)"
  9 +CONFIG_ARM=y
  10 +CONFIG_ARCH_SUNXI=y
  11 +CONFIG_MACH_SUN6I=y
  12 +CONFIG_DRAM_CLK=312
  13 +CONFIG_DRAM_ZQ=251
  14 +CONFIG_MMC_SUNXI_SLOT=0
  15 +CONFIG_MMC_SUNXI_SLOT_EXTRA=2
  16 +# Wifi power
  17 +CONFIG_AXP221_ALDO1_VOLT=3300
  18 +# Vbus gpio for usb1
  19 +CONFIG_USB1_VBUS_PIN="PH24"
  20 +# No Vbus gpio for usb2
  21 +CONFIG_USB2_VBUS_PIN=""
drivers/gpio/sunxi_gpio.c
Diff comments   View file @ 2091301
... ... @@ -21,6 +21,9 @@
21 21 #ifdef CONFIG_AXP209_POWER
22 22 #include <axp209.h>
23 23 #endif
  24 +#ifdef CONFIG_AXP221_POWER
  25 +#include <axp221.h>
  26 +#endif
24 27  
25 28 DECLARE_GLOBAL_DATA_PTR;
26 29  
... ... @@ -115,6 +118,20 @@
115 118 return sunxi_gpio_output(gpio, value);
116 119 }
117 120  
  121 +int sunxi_name_to_gpio_bank(const char *name)
  122 +{
  123 + int group = 0;
  124 +
  125 + if (*name == 'P' || *name == 'p')
  126 + name++;
  127 + if (*name >= 'A') {
  128 + group = *name - (*name > 'a' ? 'a' : 'A');
  129 + return group;
  130 + }
  131 +
  132 + return -1;
  133 +}
  134 +
118 135 int sunxi_name_to_gpio(const char *name)
119 136 {
120 137 int group = 0;
... ... @@ -125,6 +142,12 @@
125 142 #ifdef AXP_GPIO
126 143 if (strncasecmp(name, "AXP0-", 5) == 0) {
127 144 name += 5;
  145 + if (strcmp(name, "VBUS-DETECT") == 0)
  146 + return SUNXI_GPIO_AXP0_START +
  147 + SUNXI_GPIO_AXP0_VBUS_DETECT;
  148 + if (strcmp(name, "VBUS-ENABLE") == 0)
  149 + return SUNXI_GPIO_AXP0_START +
  150 + SUNXI_GPIO_AXP0_VBUS_ENABLE;
128 151 pin = simple_strtol(name, &eptr, 10);
129 152 if (!*name || *eptr)
130 153 return -1;
drivers/i2c/mvtwsi.c
Diff comments   View file @ 2091301
... ... @@ -14,7 +14,7 @@
14 14 #include <asm/io.h>
15 15  
16 16 /*
17   - * include a file that will provide CONFIG_I2C_MVTWSI_BASE
  17 + * include a file that will provide CONFIG_I2C_MVTWSI_BASE*
18 18 * and possibly other settings
19 19 */
20 20  
21 21  
22 22  
... ... @@ -91,12 +91,40 @@
91 91 #define MVTWSI_STATUS_IDLE 0xF8
92 92  
93 93 /*
94   - * The single instance of the controller we'll be dealing with
  94 + * MVTWSI controller base
95 95 */
96 96  
97   -static struct mvtwsi_registers *twsi =
98   - (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE;
  97 +static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap)
  98 +{
  99 + switch (adap->hwadapnr) {
  100 +#ifdef CONFIG_I2C_MVTWSI_BASE0
  101 + case 0:
  102 + return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE0;
  103 +#endif
  104 +#ifdef CONFIG_I2C_MVTWSI_BASE1
  105 + case 1:
  106 + return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE1;
  107 +#endif
  108 +#ifdef CONFIG_I2C_MVTWSI_BASE2
  109 + case 2:
  110 + return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE2;
  111 +#endif
  112 +#ifdef CONFIG_I2C_MVTWSI_BASE3
  113 + case 3:
  114 + return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE3;
  115 +#endif
  116 +#ifdef CONFIG_I2C_MVTWSI_BASE4
  117 + case 4:
  118 + return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE4;
  119 +#endif
  120 + default:
  121 + printf("Missing mvtwsi controller %d base\n", adap->hwadapnr);
  122 + break;
  123 + }
99 124  
  125 + return NULL;
  126 +}
  127 +
100 128 /*
101 129 * Returned statuses are 0 for success and nonzero otherwise.
102 130 * Currently, cmd_i2c and cmd_eeprom do not interpret an error status.
103 131  
... ... @@ -117,8 +145,9 @@
117 145 * Wait for IFLG to raise, or return 'timeout'; then if status is as expected,
118 146 * return 0 (ok) or return 'wrong status'.
119 147 */
120   -static int twsi_wait(int expected_status)
  148 +static int twsi_wait(struct i2c_adapter *adap, int expected_status)
121 149 {
  150 + struct mvtwsi_registers *twsi = twsi_get_base(adap);
122 151 int control, status;
123 152 int timeout = 1000;
124 153  
125 154  
126 155  
127 156  
128 157  
129 158  
130 159  
131 160  
... ... @@ -153,35 +182,40 @@
153 182 * Assert the START condition, either in a single I2C transaction
154 183 * or inside back-to-back ones (repeated starts).
155 184 */
156   -static int twsi_start(int expected_status)
  185 +static int twsi_start(struct i2c_adapter *adap, int expected_status)
157 186 {
  187 + struct mvtwsi_registers *twsi = twsi_get_base(adap);
  188 +
158 189 /* globally set TWSIEN in case it was not */
159 190 twsi_control_flags |= MVTWSI_CONTROL_TWSIEN;
160 191 /* assert START */
161 192 writel(twsi_control_flags | MVTWSI_CONTROL_START, &twsi->control);
162 193 /* wait for controller to process START */
163   - return twsi_wait(expected_status);
  194 + return twsi_wait(adap, expected_status);
164 195 }
165 196  
166 197 /*
167 198 * Send a byte (i2c address or data).
168 199 */
169   -static int twsi_send(u8 byte, int expected_status)
  200 +static int twsi_send(struct i2c_adapter *adap, u8 byte, int expected_status)
170 201 {
  202 + struct mvtwsi_registers *twsi = twsi_get_base(adap);
  203 +
171 204 /* put byte in data register for sending */
172 205 writel(byte, &twsi->data);
173 206 /* clear any pending interrupt -- that'll cause sending */
174 207 writel(twsi_control_flags, &twsi->control);
175 208 /* wait for controller to receive byte and check ACK */
176   - return twsi_wait(expected_status);
  209 + return twsi_wait(adap, expected_status);
177 210 }
178 211  
179 212 /*
180 213 * Receive a byte.
181 214 * Global mvtwsi_control_flags variable says if we should ack or nak.
182 215 */
183   -static int twsi_recv(u8 *byte)
  216 +static int twsi_recv(struct i2c_adapter *adap, u8 *byte)
184 217 {
  218 + struct mvtwsi_registers *twsi = twsi_get_base(adap);
185 219 int expected_status, status;
186 220  
187 221 /* compute expected status based on ACK bit in global control flags */
... ... @@ -192,7 +226,7 @@
192 226 /* acknowledge *previous state* and launch receive */
193 227 writel(twsi_control_flags, &twsi->control);
194 228 /* wait for controller to receive byte and assert ACK or NAK */
195   - status = twsi_wait(expected_status);
  229 + status = twsi_wait(adap, expected_status);
196 230 /* if we did receive expected byte then store it */
197 231 if (status == 0)
198 232 *byte = readl(&twsi->data);
199 233  
... ... @@ -204,8 +238,9 @@
204 238 * Assert the STOP condition.
205 239 * This is also used to force the bus back in idle (SDA=SCL=1).
206 240 */
207   -static int twsi_stop(int status)
  241 +static int twsi_stop(struct i2c_adapter *adap, int status)
208 242 {
  243 + struct mvtwsi_registers *twsi = twsi_get_base(adap);
209 244 int control, stop_status;
210 245 int timeout = 1000;
211 246  
... ... @@ -244,6 +279,7 @@
244 279 */
245 280 static void twsi_reset(struct i2c_adapter *adap)
246 281 {
  282 + struct mvtwsi_registers *twsi = twsi_get_base(adap);
247 283 /* ensure controller will be enabled by any twsi*() function */
248 284 twsi_control_flags = MVTWSI_CONTROL_TWSIEN;
249 285 /* reset controller */
... ... @@ -259,6 +295,7 @@
259 295 static unsigned int twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
260 296 unsigned int requested_speed)
261 297 {
  298 + struct mvtwsi_registers *twsi = twsi_get_base(adap);
262 299 unsigned int tmp_speed, highest_speed, n, m;
263 300 unsigned int baud = 0x44; /* baudrate at controller reset */
264 301  
... ... @@ -281,6 +318,8 @@
281 318  
282 319 static void twsi_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
283 320 {
  321 + struct mvtwsi_registers *twsi = twsi_get_base(adap);
  322 +
284 323 /* reset controller */
285 324 twsi_reset(adap);
286 325 /* set speed */
... ... @@ -289,7 +328,7 @@
289 328 writel(slaveadd, &twsi->slave_address);
290 329 writel(0, &twsi->xtnd_slave_addr);
291 330 /* assert STOP but don't care for the result */
292   - (void) twsi_stop(0);
  331 + (void) twsi_stop(adap, 0);
293 332 }
294 333  
295 334 /*
... ... @@ -297,7 +336,8 @@
297 336 * Common to i2c_probe, i2c_read and i2c_write.
298 337 * Expected address status will derive from direction bit (bit 0) in addr.
299 338 */
300   -static int i2c_begin(int expected_start_status, u8 addr)
  339 +static int i2c_begin(struct i2c_adapter *adap, int expected_start_status,
  340 + u8 addr)
301 341 {
302 342 int status, expected_addr_status;
303 343  
304 344  
... ... @@ -307,10 +347,10 @@
307 347 else /* writing */
308 348 expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK;
309 349 /* assert START */
310   - status = twsi_start(expected_start_status);
  350 + status = twsi_start(adap, expected_start_status);
311 351 /* send out the address if the start went well */
312 352 if (status == 0)
313   - status = twsi_send(addr, expected_addr_status);
  353 + status = twsi_send(adap, addr, expected_addr_status);
314 354 /* return ok or status of first failure to caller */
315 355 return status;
316 356 }
317 357  
318 358  
... ... @@ -325,12 +365,12 @@
325 365 int status;
326 366  
327 367 /* begin i2c read */
328   - status = i2c_begin(MVTWSI_STATUS_START, (chip << 1) | 1);
  368 + status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1) | 1);
329 369 /* dummy read was accepted: receive byte but NAK it. */
330 370 if (status == 0)
331   - status = twsi_recv(&dummy_byte);
  371 + status = twsi_recv(adap, &dummy_byte);
332 372 /* Stop transaction */
333   - twsi_stop(0);
  373 + twsi_stop(adap, 0);
334 374 /* return 0 or status of first failure */
335 375 return status;
336 376 }
337 377  
338 378  
... ... @@ -351,15 +391,15 @@
351 391 int status;
352 392  
353 393 /* begin i2c write to send the address bytes */
354   - status = i2c_begin(MVTWSI_STATUS_START, (chip << 1));
  394 + status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1));
355 395 /* send addr bytes */
356 396 while ((status == 0) && alen--)
357   - status = twsi_send(addr >> (8*alen),
  397 + status = twsi_send(adap, addr >> (8*alen),
358 398 MVTWSI_STATUS_DATA_W_ACK);
359 399 /* begin i2c read to receive eeprom data bytes */
360 400 if (status == 0)
361   - status = i2c_begin(
362   - MVTWSI_STATUS_REPEATED_START, (chip << 1) | 1);
  401 + status = i2c_begin(adap, MVTWSI_STATUS_REPEATED_START,
  402 + (chip << 1) | 1);
363 403 /* prepare ACK if at least one byte must be received */
364 404 if (length > 0)
365 405 twsi_control_flags |= MVTWSI_CONTROL_ACK;
366 406  
... ... @@ -369,10 +409,10 @@
369 409 if (length == 0)
370 410 twsi_control_flags &= ~MVTWSI_CONTROL_ACK;
371 411 /* read current byte */
372   - status = twsi_recv(data++);
  412 + status = twsi_recv(adap, data++);
373 413 }
374 414 /* Stop transaction */
375   - status = twsi_stop(status);
  415 + status = twsi_stop(adap, status);
376 416 /* return 0 or status of first failure */
377 417 return status;
378 418 }
379 419  
380 420  
381 421  
382 422  
383 423  
... ... @@ -387,22 +427,52 @@
387 427 int status;
388 428  
389 429 /* begin i2c write to send the eeprom adress bytes then data bytes */
390   - status = i2c_begin(MVTWSI_STATUS_START, (chip << 1));
  430 + status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1));
391 431 /* send addr bytes */
392 432 while ((status == 0) && alen--)
393   - status = twsi_send(addr >> (8*alen),
  433 + status = twsi_send(adap, addr >> (8*alen),
394 434 MVTWSI_STATUS_DATA_W_ACK);
395 435 /* send data bytes */
396 436 while ((status == 0) && (length-- > 0))
397   - status = twsi_send(*(data++), MVTWSI_STATUS_DATA_W_ACK);
  437 + status = twsi_send(adap, *(data++), MVTWSI_STATUS_DATA_W_ACK);
398 438 /* Stop transaction */
399   - status = twsi_stop(status);
  439 + status = twsi_stop(adap, status);
400 440 /* return 0 or status of first failure */
401 441 return status;
402 442 }
403 443  
  444 +#ifdef CONFIG_I2C_MVTWSI_BASE0
404 445 U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe,
405 446 twsi_i2c_read, twsi_i2c_write,
406 447 twsi_i2c_set_bus_speed,
407 448 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
  449 +#endif
  450 +#ifdef CONFIG_I2C_MVTWSI_BASE1
  451 +U_BOOT_I2C_ADAP_COMPLETE(twsi1, twsi_i2c_init, twsi_i2c_probe,
  452 + twsi_i2c_read, twsi_i2c_write,
  453 + twsi_i2c_set_bus_speed,
  454 + CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 1)
  455 +
  456 +#endif
  457 +#ifdef CONFIG_I2C_MVTWSI_BASE2
  458 +U_BOOT_I2C_ADAP_COMPLETE(twsi2, twsi_i2c_init, twsi_i2c_probe,
  459 + twsi_i2c_read, twsi_i2c_write,
  460 + twsi_i2c_set_bus_speed,
  461 + CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 2)
  462 +
  463 +#endif
  464 +#ifdef CONFIG_I2C_MVTWSI_BASE3
  465 +U_BOOT_I2C_ADAP_COMPLETE(twsi3, twsi_i2c_init, twsi_i2c_probe,
  466 + twsi_i2c_read, twsi_i2c_write,
  467 + twsi_i2c_set_bus_speed,
  468 + CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 3)
  469 +
  470 +#endif
  471 +#ifdef CONFIG_I2C_MVTWSI_BASE4
  472 +U_BOOT_I2C_ADAP_COMPLETE(twsi4, twsi_i2c_init, twsi_i2c_probe,
  473 + twsi_i2c_read, twsi_i2c_write,
  474 + twsi_i2c_set_bus_speed,
  475 + CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 4)
  476 +
  477 +#endif
drivers/net/sunxi_emac.c
Diff comments   View file @ 2091301
... ... @@ -497,7 +497,7 @@
497 497  
498 498 /* Configure pin mux settings for MII Ethernet */
499 499 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++)
500   - sunxi_gpio_set_cfgpin(pin, SUNXI_GPA0_EMAC);
  500 + sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC);
501 501  
502 502 /* Set up clock gating */
503 503 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_EMAC);
drivers/power/axp152.c
Diff comments   View file @ 2091301
... ... @@ -8,17 +8,6 @@
8 8 #include <i2c.h>
9 9 #include <axp152.h>
10 10  
11   -enum axp152_reg {
12   - AXP152_CHIP_VERSION = 0x3,
13   - AXP152_DCDC2_VOLTAGE = 0x23,
14   - AXP152_DCDC3_VOLTAGE = 0x27,
15   - AXP152_DCDC4_VOLTAGE = 0x2B,
16   - AXP152_LDO2_VOLTAGE = 0x2A,
17   - AXP152_SHUTDOWN = 0x32,
18   -};
19   -
20   -#define AXP152_POWEROFF (1 << 7)
21   -
22 11 static int axp152_write(enum axp152_reg reg, u8 val)
23 12 {
24 13 return i2c_write(0x30, reg, 1, &val, 1);
drivers/power/axp209.c
Diff comments   View file @ 2091301
... ... @@ -7,45 +7,9 @@
7 7  
8 8 #include <common.h>
9 9 #include <i2c.h>
  10 +#include <asm/arch/gpio.h>
10 11 #include <axp209.h>
11 12  
12   -enum axp209_reg {
13   - AXP209_POWER_STATUS = 0x00,
14   - AXP209_CHIP_VERSION = 0x03,
15   - AXP209_DCDC2_VOLTAGE = 0x23,
16   - AXP209_DCDC3_VOLTAGE = 0x27,
17   - AXP209_LDO24_VOLTAGE = 0x28,
18   - AXP209_LDO3_VOLTAGE = 0x29,
19   - AXP209_IRQ_ENABLE1 = 0x40,
20   - AXP209_IRQ_ENABLE2 = 0x41,
21   - AXP209_IRQ_ENABLE3 = 0x42,
22   - AXP209_IRQ_ENABLE4 = 0x43,
23   - AXP209_IRQ_ENABLE5 = 0x44,
24   - AXP209_IRQ_STATUS5 = 0x4c,
25   - AXP209_SHUTDOWN = 0x32,
26   - AXP209_GPIO0_CTRL = 0x90,
27   - AXP209_GPIO1_CTRL = 0x92,
28   - AXP209_GPIO2_CTRL = 0x93,
29   - AXP209_GPIO_STATE = 0x94,
30   - AXP209_GPIO3_CTRL = 0x95,
31   -};
32   -
33   -#define AXP209_POWER_STATUS_ON_BY_DC (1 << 0)
34   -
35   -#define AXP209_IRQ5_PEK_UP (1 << 6)
36   -#define AXP209_IRQ5_PEK_DOWN (1 << 5)
37   -
38   -#define AXP209_POWEROFF (1 << 7)
39   -
40   -#define AXP209_GPIO_OUTPUT_LOW 0x00 /* Drive pin low */
41   -#define AXP209_GPIO_OUTPUT_HIGH 0x01 /* Drive pin high */
42   -#define AXP209_GPIO_INPUT 0x02 /* Float pin */
43   -
44   -/* GPIO3 is different from the others */
45   -#define AXP209_GPIO3_OUTPUT_LOW 0x00 /* Drive pin low, Output mode */
46   -#define AXP209_GPIO3_OUTPUT_HIGH 0x02 /* Float pin, Output mode */
47   -#define AXP209_GPIO3_INPUT 0x06 /* Float pin, Input mode */
48   -
49 13 static int axp209_write(enum axp209_reg reg, u8 val)
50 14 {
51 15 return i2c_write(0x34, reg, 1, &val, 1);
... ... @@ -205,6 +169,9 @@
205 169  
206 170 int axp_gpio_direction_input(unsigned int pin)
207 171 {
  172 + if (pin == SUNXI_GPIO_AXP0_VBUS_DETECT)
  173 + return 0;
  174 +
208 175 u8 reg = axp209_get_gpio_ctrl_reg(pin);
209 176 /* GPIO3 is "special" */
210 177 u8 val = (pin == 3) ? AXP209_GPIO3_INPUT : AXP209_GPIO_INPUT;
... ... @@ -232,7 +199,10 @@
232 199 u8 val, mask;
233 200 int rc;
234 201  
235   - if (pin == 3) {
  202 + if (pin == SUNXI_GPIO_AXP0_VBUS_DETECT) {
  203 + rc = axp209_read(AXP209_POWER_STATUS, &val);
  204 + mask = AXP209_POWER_STATUS_VBUS_USABLE;
  205 + } else if (pin == 3) {
236 206 rc = axp209_read(AXP209_GPIO3_CTRL, &val);
237 207 mask = 1;
238 208 } else {
drivers/power/axp221.c
Diff comments   View file @ 2091301
... ... @@ -14,6 +14,7 @@
14 14 #include <errno.h>
15 15 #include <asm/arch/p2wi.h>
16 16 #include <asm/arch/rsb.h>
  17 +#include <asm/arch/gpio.h>
17 18 #include <axp221.h>
18 19  
19 20 /*
20 21  
21 22  
22 23  
23 24  
24 25  
25 26  
26 27  
27 28  
28 29  
29 30  
30 31  
... ... @@ -385,55 +386,67 @@
385 386 return 0;
386 387 }
387 388  
388   -int axp_get_vbus(void)
  389 +int axp_gpio_direction_input(unsigned int pin)
389 390 {
390   - int ret;
391   - u8 val;
392   -
393   - ret = axp221_init();
394   - if (ret)
395   - return ret;
396   -
397   - ret = pmic_bus_read(AXP221_POWER_STATUS, &val);
398   - if (ret)
399   - return ret;
400   -
401   - return (val & AXP221_POWER_STATUS_VBUS_USABLE) ? 1 : 0;
  391 + switch (pin) {
  392 + case SUNXI_GPIO_AXP0_VBUS_DETECT:
  393 + return 0;
  394 + default:
  395 + return -EINVAL;
  396 + }
402 397 }
403 398  
404   -static int axp_drivebus_setup(void)
  399 +int axp_gpio_direction_output(unsigned int pin, unsigned int val)
405 400 {
406 401 int ret;
407 402  
408   - ret = axp221_init();
409   - if (ret)
410   - return ret;
  403 + switch (pin) {
  404 + case SUNXI_GPIO_AXP0_VBUS_ENABLE:
  405 + ret = axp221_clrbits(AXP221_MISC_CTRL,
  406 + AXP221_MISC_CTRL_N_VBUSEN_FUNC);
  407 + if (ret)
  408 + return ret;
411 409  
412   - /* Set N_VBUSEN pin to output / DRIVEBUS function */
413   - return axp221_clrbits(AXP221_MISC_CTRL, AXP221_MISC_CTRL_N_VBUSEN_FUNC);
  410 + return axp_gpio_set_value(pin, val);
  411 + default:
  412 + return -EINVAL;
  413 + }
414 414 }
415 415  
416   -int axp_drivebus_enable(void)
  416 +int axp_gpio_get_value(unsigned int pin)
417 417 {
418 418 int ret;
  419 + u8 val;
419 420  
420   - ret = axp_drivebus_setup();
421   - if (ret)
422   - return ret;
  421 + switch (pin) {
  422 + case SUNXI_GPIO_AXP0_VBUS_DETECT:
  423 + ret = pmic_bus_read(AXP221_POWER_STATUS, &val);
  424 + if (ret)
  425 + return ret;
423 426  
424   - /* Set DRIVEBUS high */
425   - return axp221_setbits(AXP221_VBUS_IPSOUT, AXP221_VBUS_IPSOUT_DRIVEBUS);
  427 + return !!(val & AXP221_POWER_STATUS_VBUS_AVAIL);
  428 + default:
  429 + return -EINVAL;
  430 + }
426 431 }
427 432  
428   -int axp_drivebus_disable(void)
  433 +int axp_gpio_set_value(unsigned int pin, unsigned int val)
429 434 {
430 435 int ret;
431 436  
432   - ret = axp_drivebus_setup();
433   - if (ret)
434   - return ret;
  437 + switch (pin) {
  438 + case SUNXI_GPIO_AXP0_VBUS_ENABLE:
  439 + if (val)
  440 + ret = axp221_setbits(AXP221_VBUS_IPSOUT,
  441 + AXP221_VBUS_IPSOUT_DRIVEBUS);
  442 + else
  443 + ret = axp221_clrbits(AXP221_VBUS_IPSOUT,
  444 + AXP221_VBUS_IPSOUT_DRIVEBUS);
435 445  
436   - /* Set DRIVEBUS low */
437   - return axp221_clrbits(AXP221_VBUS_IPSOUT, AXP221_VBUS_IPSOUT_DRIVEBUS);
  446 + if (ret)
  447 + return ret;
  448 + }
  449 +
  450 + return 0;
438 451 }
drivers/usb/musb-new/sunxi.c
Diff comments   View file @ 2091301
... ... @@ -235,51 +235,18 @@
235 235  
236 236 pr_debug("%s():\n", __func__);
237 237  
238   - if (is_host_enabled(musb)) {
239   - int vbus_det = sunxi_name_to_gpio(CONFIG_USB0_VBUS_DET);
  238 + err = sunxi_usbc_request_resources(0);
  239 + if (err)
  240 + return err;
240 241  
241   -#ifdef AXP_VBUS_DETECT
242   - if (!strcmp(CONFIG_USB0_VBUS_DET, "axp_vbus_detect")) {
243   - err = axp_get_vbus();
244   - if (err < 0)
245   - return err;
246   - } else {
247   -#endif
248   - if (vbus_det == -1) {
249   - eprintf("Error invalid Vusb-det pin\n");
250   - return -EINVAL;
251   - }
252   -
253   - err = gpio_request(vbus_det, "vbus0_det");
254   - if (err)
255   - return err;
256   -
257   - err = gpio_direction_input(vbus_det);
258   - if (err) {
259   - gpio_free(vbus_det);
260   - return err;
261   - }
262   -
263   - err = gpio_get_value(vbus_det);
264   - if (err < 0) {
265   - gpio_free(vbus_det);
266   - return -EIO;
267   - }
268   -
269   - gpio_free(vbus_det);
270   -#ifdef AXP_VBUS_DETECT
271   - }
272   -#endif
273   -
  242 + if (is_host_enabled(musb)) {
  243 + err = sunxi_usbc_vbus_detect(0);
274 244 if (err) {
275 245 eprintf("Error: A charger is plugged into the OTG\n");
  246 + sunxi_usbc_free_resources(0);
276 247 return -EIO;
277 248 }
278 249 }
279   -
280   - err = sunxi_usbc_request_resources(0);
281   - if (err)
282   - return err;
283 250  
284 251 musb->isr = sunxi_musb_interrupt;
285 252 sunxi_usbc_enable(0);
drivers/video/sunxi_display.c
Diff comments   View file @ 2091301
... ... @@ -665,10 +665,10 @@
665 665  
666 666 for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(27); pin++)
667 667 #ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
668   - sunxi_gpio_set_cfgpin(pin, SUNXI_GPD0_LCD0);
  668 + sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LCD0);
669 669 #endif
670 670 #ifdef CONFIG_VIDEO_LCD_IF_LVDS
671   - sunxi_gpio_set_cfgpin(pin, SUNXI_GPD0_LVDS0);
  671 + sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LVDS0);
672 672 #endif
673 673  
674 674 sunxi_lcdc_pll_set(0, mode->pixclock_khz, &clk_div, &clk_double);
... ... @@ -779,8 +779,8 @@
779 779 &lcdc->tcon1_timing_sync);
780 780  
781 781 if (use_portd_hvsync) {
782   - sunxi_gpio_set_cfgpin(SUNXI_GPD(26), SUNXI_GPD0_LCD0);
783   - sunxi_gpio_set_cfgpin(SUNXI_GPD(27), SUNXI_GPD0_LCD0);
  782 + sunxi_gpio_set_cfgpin(SUNXI_GPD(26), SUNXI_GPD_LCD0);
  783 + sunxi_gpio_set_cfgpin(SUNXI_GPD(27), SUNXI_GPD_LCD0);
784 784  
785 785 val = 0;
786 786 if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
... ... @@ -3,6 +3,18 @@
3 3 *
4 4 * SPDX-License-Identifier: GPL-2.0+
5 5 */
  6 +
  7 +enum axp152_reg {
  8 + AXP152_CHIP_VERSION = 0x3,
  9 + AXP152_DCDC2_VOLTAGE = 0x23,
  10 + AXP152_DCDC3_VOLTAGE = 0x27,
  11 + AXP152_DCDC4_VOLTAGE = 0x2B,
  12 + AXP152_LDO2_VOLTAGE = 0x2A,
  13 + AXP152_SHUTDOWN = 0x32,
  14 +};
  15 +
  16 +#define AXP152_POWEROFF (1 << 7)
  17 +
6 18 int axp152_set_dcdc2(int mvolt);
7 19 int axp152_set_dcdc3(int mvolt);
8 20 int axp152_set_dcdc4(int mvolt);
... ... @@ -4,6 +4,44 @@
4 4 * SPDX-License-Identifier: GPL-2.0+
5 5 */
6 6  
  7 +enum axp209_reg {
  8 + AXP209_POWER_STATUS = 0x00,
  9 + AXP209_CHIP_VERSION = 0x03,
  10 + AXP209_DCDC2_VOLTAGE = 0x23,
  11 + AXP209_DCDC3_VOLTAGE = 0x27,
  12 + AXP209_LDO24_VOLTAGE = 0x28,
  13 + AXP209_LDO3_VOLTAGE = 0x29,
  14 + AXP209_IRQ_ENABLE1 = 0x40,
  15 + AXP209_IRQ_ENABLE2 = 0x41,
  16 + AXP209_IRQ_ENABLE3 = 0x42,
  17 + AXP209_IRQ_ENABLE4 = 0x43,
  18 + AXP209_IRQ_ENABLE5 = 0x44,
  19 + AXP209_IRQ_STATUS5 = 0x4c,
  20 + AXP209_SHUTDOWN = 0x32,
  21 + AXP209_GPIO0_CTRL = 0x90,
  22 + AXP209_GPIO1_CTRL = 0x92,
  23 + AXP209_GPIO2_CTRL = 0x93,
  24 + AXP209_GPIO_STATE = 0x94,
  25 + AXP209_GPIO3_CTRL = 0x95,
  26 +};
  27 +
  28 +#define AXP209_POWER_STATUS_ON_BY_DC (1 << 0)
  29 +#define AXP209_POWER_STATUS_VBUS_USABLE (1 << 4)
  30 +
  31 +#define AXP209_IRQ5_PEK_UP (1 << 6)
  32 +#define AXP209_IRQ5_PEK_DOWN (1 << 5)
  33 +
  34 +#define AXP209_POWEROFF (1 << 7)
  35 +
  36 +#define AXP209_GPIO_OUTPUT_LOW 0x00 /* Drive pin low */
  37 +#define AXP209_GPIO_OUTPUT_HIGH 0x01 /* Drive pin high */
  38 +#define AXP209_GPIO_INPUT 0x02 /* Float pin */
  39 +
  40 +/* GPIO3 is different from the others */
  41 +#define AXP209_GPIO3_OUTPUT_LOW 0x00 /* Drive pin low, Output mode */
  42 +#define AXP209_GPIO3_OUTPUT_HIGH 0x02 /* Float pin, Output mode */
  43 +#define AXP209_GPIO3_INPUT 0x06 /* Float pin, Input mode */
  44 +
7 45 #define AXP_GPIO
8 46  
9 47 extern int axp209_set_dcdc2(int mvolt);
... ... @@ -62,12 +62,8 @@
62 62 /* Page 1 addresses */
63 63 #define AXP221_SID 0x20
64 64  
65   -/* We support vbus detection */
66   -#define AXP_VBUS_DETECT
  65 +#define AXP_GPIO
67 66  
68   -/* We support drivebus control */
69   -#define AXP_DRIVEBUS
70   -
71 67 int axp221_set_dcdc1(unsigned int mvolt);
72 68 int axp221_set_dcdc2(unsigned int mvolt);
73 69 int axp221_set_dcdc3(unsigned int mvolt);
... ... @@ -83,7 +79,9 @@
83 79 int axp221_set_eldo(int eldo_num, unsigned int mvolt);
84 80 int axp221_init(void);
85 81 int axp221_get_sid(unsigned int *sid);
86   -int axp_get_vbus(void);
87   -int axp_drivebus_enable(void);
88   -int axp_drivebus_disable(void);
  82 +
  83 +int axp_gpio_direction_input(unsigned int pin);
  84 +int axp_gpio_direction_output(unsigned int pin, unsigned int val);
  85 +int axp_gpio_get_value(unsigned int pin);
  86 +int axp_gpio_set_value(unsigned int pin, unsigned int val);
include/configs/db-mv784mp-gp.h
Diff comments   View file @ 2091301
... ... @@ -37,7 +37,7 @@
37 37 /* I2C */
38 38 #define CONFIG_SYS_I2C
39 39 #define CONFIG_SYS_I2C_MVTWSI
40   -#define CONFIG_I2C_MVTWSI_BASE MVEBU_TWSI_BASE
  40 +#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
41 41 #define CONFIG_SYS_I2C_SLAVE 0x0
42 42 #define CONFIG_SYS_I2C_SPEED 100000
43 43  
include/configs/edminiv2.h
Diff comments   View file @ 2091301
... ... @@ -208,7 +208,7 @@
208 208 #ifdef CONFIG_CMD_I2C
209 209 #define CONFIG_SYS_I2C
210 210 #define CONFIG_SYS_I2C_MVTWSI
211   -#define CONFIG_I2C_MVTWSI_BASE ORION5X_TWSI_BASE
  211 +#define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE
212 212 #define CONFIG_SYS_I2C_SLAVE 0x0
213 213 #define CONFIG_SYS_I2C_SPEED 100000
214 214 #endif
include/configs/maxbcm.h
Diff comments   View file @ 2091301
... ... @@ -35,7 +35,7 @@
35 35 /* I2C */
36 36 #define CONFIG_SYS_I2C
37 37 #define CONFIG_SYS_I2C_MVTWSI
38   -#define CONFIG_I2C_MVTWSI_BASE MVEBU_TWSI_BASE
  38 +#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
39 39 #define CONFIG_SYS_I2C_SLAVE 0x0
40 40 #define CONFIG_SYS_I2C_SPEED 100000
41 41  
include/configs/sunxi-common.h
Diff comments   View file @ 2091301
... ... @@ -196,7 +196,11 @@
196 196 #endif
197 197  
198 198 #define CONFIG_SYS_I2C
  199 +#if defined CONFIG_I2C0_ENABLE || defined CONFIG_I2C1_ENABLE || \
  200 + defined CONFIG_I2C2_ENABLE || defined CONFIG_I2C3_ENABLE || \
  201 + defined CONFIG_I2C4_ENABLE
199 202 #define CONFIG_SYS_I2C_MVTWSI
  203 +#endif
200 204 #define CONFIG_SYS_I2C_SPEED 400000
201 205 #define CONFIG_SYS_I2C_SLAVE 0x7f
202 206