Eric Lee / smarc-uboot

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Commit 2100a53919eec7f9a76bc67204cd89e20afa2924

Authored by Peng Fan
1 parent 7c174401a2
Exists in smarc-imx-l5.0.0_1.0.0-ga

MLK-9665-1 QuadSPI: Support flash bigger than 16MB 

By introducing CONFIG_SPI_FLASH_BAR and add related command in LUT to
enable fsl_qspi.c can handle flash size bigger that 16M. Because uboot
does not support 32bits address access, this means bank address should
be used to access bigger flash.

It is hard to let qspi driver dynamically set LUT, so BRRD BRWR RDEAR
and WREAR are all supported.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>

Showing 1 changed file with 50 additions and 1 deletions Side-by-side Diff

drivers/spi/fsl_qspi.c
Diff comments   View file @ 2100a53
... ... @@ -180,6 +180,12 @@
180 180 #define SEQID_RDCR 9
181 181 #define SEQID_DDR_QUAD_READ 10
182 182 #define SEQID_BE_4K 11
  183 +#ifdef CONFIG_SPI_FLASH_BAR
  184 +#define SEQID_BRRD 12
  185 +#define SEQID_BRWR 13
  186 +#define SEQID_RDEAR 14
  187 +#define SEQID_WREAR 15
  188 +#endif
183 189  
184 190 /* Flash opcodes. */
185 191 #define OPCODE_WREN 0x06 /* Write enable */
186 192  
... ... @@ -214,7 +220,12 @@
214 220 #define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */
215 221 #define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */
216 222  
  223 +/* Used for Micron, winbond and Macronix flashes */
  224 +#define OPCODE_WREAR 0xc5 /* EAR register write */
  225 +#define OPCODE_RDEAR 0xc8 /* EAR reigster read */
  226 +
217 227 /* Used for Spansion flashes only. */
  228 +#define OPCODE_BRRD 0x16 /* Bank register read */
218 229 #define OPCODE_BRWR 0x17 /* Bank register write */
219 230  
220 231 /* Status Register bits. */
221 232  
... ... @@ -377,7 +388,32 @@
377 388 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
378 389 base + QUADSPI_LUT(lut_base));
379 390  
  391 +#ifdef CONFIG_SPI_FLASH_BAR
  392 + /*
  393 + * BRRD BRWR RDEAR WREAR are all supported, because it is hard to
  394 + * dynamically check whether to set BRRD BRWR or RDEAR WREAR.
  395 + */
  396 + lut_base = SEQID_BRRD * 4;
  397 + cmd = OPCODE_BRRD;
  398 + writel(LUT0(CMD, PAD1, cmd) | LUT1(READ, PAD1, 0x1),
  399 + base + QUADSPI_LUT(lut_base));
380 400  
  401 + lut_base = SEQID_BRWR * 4;
  402 + cmd = OPCODE_BRWR;
  403 + writel(LUT0(CMD, PAD1, cmd) | LUT1(WRITE, PAD1, 0x1),
  404 + base + QUADSPI_LUT(lut_base));
  405 +
  406 + lut_base = SEQID_RDEAR * 4;
  407 + cmd = OPCODE_RDEAR;
  408 + writel(LUT0(CMD, PAD1, cmd) | LUT1(READ, PAD1, 0x1),
  409 + base + QUADSPI_LUT(lut_base));
  410 +
  411 + lut_base = SEQID_WREAR * 4;
  412 + cmd = OPCODE_WREAR;
  413 + writel(LUT0(CMD, PAD1, cmd) | LUT1(WRITE, PAD1, 0x1),
  414 + base + QUADSPI_LUT(lut_base));
  415 +#endif
  416 +
381 417 fsl_qspi_lock_lut(q);
382 418 }
383 419  
... ... @@ -589,6 +625,16 @@
589 625 return SEQID_DDR_QUAD_READ;
590 626 case OPCODE_BE_4K:
591 627 return SEQID_BE_4K;
  628 +#ifdef CONFIG_SPI_FLASH_BAR
  629 + case OPCODE_BRRD:
  630 + return SEQID_BRRD;
  631 + case OPCODE_BRWR:
  632 + return SEQID_BRWR;
  633 + case OPCODE_RDEAR:
  634 + return SEQID_RDEAR;
  635 + case OPCODE_WREAR:
  636 + return SEQID_WREAR;
  637 +#endif
592 638 default:
593 639 break;
594 640 }
... ... @@ -682,7 +728,10 @@
682 728 /* restore the MCR */
683 729 writel(reg, base + QUADSPI_MCR);
684 730  
685   - if ((OPCODE_SE == cmd) || (OPCODE_PP == cmd) || (OPCODE_BE_4K == cmd))
  731 + /* After switch BANK, AHB buffer should also be invalid. */
  732 + if ((OPCODE_SE == cmd) || (OPCODE_PP == cmd) ||
  733 + (OPCODE_BE_4K == cmd) || (OPCODE_WREAR == cmd) ||
  734 + (OPCODE_BRWR == cmd))
686 735 fsl_qspi_invalid(q);
687 736 return err;
688 737 }