Add SGMII support for the 8544 DS

The 8544 DS has an optional SGMII Riser card, which uses different PHY addresses. Check if we are in SGMII mode, and invoke the SGMII Riser setup code if so. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>

Add SGMII support for the 8544 DS
The 8544 DS has an optional SGMII Riser card, which uses different PHY addresses. Check if we are in SGMII mode, and invoke the SGMII Riser setup code if so. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Andy Fleming · Ben Warren
1 parent 652f7c2eef
Showing 1 changed file with 39 additions and 0 deletions Side-by-side Diff
board/freescale/mpc8544ds/mpc8544ds.c
@@ -32,8 +32,10 @@
 #include <miiphy.h>
 #include <libfdt.h>
 #include <fdt_support.h>
+#include <tsec.h>
  
 #include "../common/pixis.h"
+#include "../common/sgmii_riser.h"
  
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
@@ -462,6 +464,43 @@
  
 	return val;
 }
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+	struct tsec_info_struct tsec_info[2];
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+	int num = 0;
+
+#ifdef CONFIG_TSEC1
+	SET_STD_TSEC_INFO(tsec_info[num], 1);
+	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
+		tsec_info[num].flags |= TSEC_SGMII;
+	num++;
+#endif
+#ifdef CONFIG_TSEC3
+	SET_STD_TSEC_INFO(tsec_info[num], 3);
+	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
+		tsec_info[num].flags |= TSEC_SGMII;
+	num++;
+#endif
+
+	if (!num) {
+		printf("No TSECs initialized\n");
+
+		return 0;
+	}
+
+	if (io_sel & 1)
+		fsl_sgmii_riser_init(tsec_info, num);
+
+
+	tsec_eth_init(bis, tsec_info, num);
+
+	return 0;
+}
+#endif
  
 #if defined(CONFIG_OF_BOARD_SETUP)
...	...	@@ -32,8 +32,10 @@
32	32	#include <miiphy.h>
33	33	#include <libfdt.h>
34	34	#include <fdt_support.h>
	35	+#include <tsec.h>
35	36
36	37	#include "../common/pixis.h"
	38	+#include "../common/sgmii_riser.h"
37	39
38	40	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
39	41	extern void ddr_enable_ecc(unsigned int dram_size);
...	...	@@ -462,6 +464,43 @@
462	464
463	465	return val;
464	466	}
	467	+
	468	+#ifdef CONFIG_TSEC_ENET
	469	+int board_eth_init(bd_t *bis)
	470	+{
	471	+ struct tsec_info_struct tsec_info[2];
	472	+ volatile ccsr_gur_t gur = (void )(CFG_MPC85xx_GUTS_ADDR);
	473	+ uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	474	+ int num = 0;
	475	+
	476	+#ifdef CONFIG_TSEC1
	477	+ SET_STD_TSEC_INFO(tsec_info[num], 1);
	478	+ if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
	479	+ tsec_info[num].flags \|= TSEC_SGMII;
	480	+ num++;
	481	+#endif
	482	+#ifdef CONFIG_TSEC3
	483	+ SET_STD_TSEC_INFO(tsec_info[num], 3);
	484	+ if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
	485	+ tsec_info[num].flags \|= TSEC_SGMII;
	486	+ num++;
	487	+#endif
	488	+
	489	+ if (!num) {
	490	+ printf("No TSECs initialized\n");
	491	+
	492	+ return 0;
	493	+ }
	494	+
	495	+ if (io_sel & 1)
	496	+ fsl_sgmii_riser_init(tsec_info, num);
	497	+
	498	+
	499	+ tsec_eth_init(bis, tsec_info, num);
	500	+
	501	+ return 0;
	502	+}
	503	+#endif
465	504
466	505	#if defined(CONFIG_OF_BOARD_SETUP)
467	506