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Commit 225f5eeccd6c0d376a20c15897edd8c69500d8cc

Authored by Minkyu Kang
1 parent fa8883a1e3
Exists in v2017.01-smarct4x and in 30 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

arm: s5pc1xx: move SoC to mach-s5pc1xx 

move arm/arm/cpu/armv7/s5pc1xx to arch/arm/mach-s5pc1xx

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

Showing 40 changed files with 1895 additions and 1897 deletions Side-by-side Diff

... ... @@ -112,12 +112,10 @@
112 112 S: Maintained
113 113 T: git git://git.denx.de/u-boot-samsung.git
114 114 F: arch/arm/cpu/arm920t/s3c24x0/
115   -F: arch/arm/cpu/armv7/exynos/
116   -F: arch/arm/cpu/armv7/s5pc1xx/
  115 +F: arch/arm/mach-exynos/
  116 +F: arch/arm/mach-s5pc1xx/
117 117 F: arch/arm/cpu/armv7/s5p-common/
118   -F: arch/arm/include/asm/arch-exynos/
119 118 F: arch/arm/include/asm/arch-s3c24x0/
120   -F: arch/arm/include/asm/arch-s5pc1xx/
121 119  
122 120 ARM STM SPEAR
123 121 M: Vipin Kumar <vipin.kumar@st.com>
... ... @@ -721,7 +721,7 @@
721 721  
722 722 source "arch/arm/mach-rockchip/Kconfig"
723 723  
724   -source "arch/arm/cpu/armv7/s5pc1xx/Kconfig"
  724 +source "arch/arm/mach-s5pc1xx/Kconfig"
725 725  
726 726 source "arch/arm/mach-socfpga/Kconfig"
727 727  
... ... @@ -53,6 +53,7 @@
53 53 # TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
54 54 # TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
55 55 machine-$(CONFIG_ORION5X) += orion5x
  56 +machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx
56 57 machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
57 58 machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
58 59 machine-$(CONFIG_TEGRA) += tegra
arch/arm/cpu/armv7/Makefile
Diff comments   View file @ 225f5ee
... ... @@ -49,7 +49,6 @@
49 49 obj-$(CONFIG_OMAP44XX) += omap4/
50 50 obj-$(CONFIG_OMAP54XX) += omap5/
51 51 obj-$(CONFIG_RMOBILE) += rmobile/
52   -obj-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx/
53 52 obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
54 53 obj-$(CONFIG_ARCH_SUNXI) += sunxi/
55 54 obj-$(CONFIG_VF610) += vf610/
arch/arm/cpu/armv7/s5pc1xx/Kconfig
View file @ 225f5ee
1   -if ARCH_S5PC1XX
2   -
3   -choice
4   - prompt "S5PC1XX board select"
5   - optional
6   -
7   -config TARGET_S5P_GONI
8   - bool "S5P Goni board"
9   - select OF_CONTROL
10   -
11   -config TARGET_SMDKC100
12   - bool "Support smdkc100 board"
13   - select OF_CONTROL
14   -
15   -endchoice
16   -
17   -config SYS_SOC
18   - default "s5pc1xx"
19   -
20   -source "board/samsung/goni/Kconfig"
21   -source "board/samsung/smdkc100/Kconfig"
22   -
23   -endif
arch/arm/cpu/armv7/s5pc1xx/Makefile
View file @ 225f5ee
1   -#
2   -# (C) Copyright 2000-2003
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# (C) Copyright 2008
6   -# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
7   -#
8   -# SPDX-License-Identifier: GPL-2.0+
9   -#
10   -
11   -obj-y = cache.o
12   -obj-y += reset.o
13   -
14   -obj-y += clock.o
arch/arm/cpu/armv7/s5pc1xx/cache.c
View file @ 225f5ee
1   -/*
2   - * Copyright (C) 2014 Samsung Electronics
3   - * Minkyu Kang <mk7.kang@samsung.com>
4   - * Robert Baldyga <r.baldyga@samsung.com>
5   - *
6   - * based on arch/arm/cpu/armv7/omap3/cache.S
7   - *
8   - * SPDX-License-Identifier: GPL-2.0+
9   - */
10   -
11   -#include <common.h>
12   -
13   -#ifndef CONFIG_SYS_DCACHE_OFF
14   -void enable_caches(void)
15   -{
16   - dcache_enable();
17   -}
18   -
19   -void disable_caches(void)
20   -{
21   - dcache_disable();
22   -}
23   -#endif
24   -
25   -#ifndef CONFIG_SYS_L2CACHE_OFF
26   -void v7_outer_cache_enable(void)
27   -{
28   - __asm(
29   - "push {r0, r1, r2, lr}\n\t"
30   - "mrc 15, 0, r3, cr1, cr0, 1\n\t"
31   - "orr r3, r3, #2\n\t"
32   - "mcr 15, 0, r3, cr1, cr0, 1\n\t"
33   - "pop {r1, r2, r3, pc}"
34   - );
35   -}
36   -
37   -void v7_outer_cache_disable(void)
38   -{
39   - __asm(
40   - "push {r0, r1, r2, lr}\n\t"
41   - "mrc 15, 0, r3, cr1, cr0, 1\n\t"
42   - "bic r3, r3, #2\n\t"
43   - "mcr 15, 0, r3, cr1, cr0, 1\n\t"
44   - "pop {r1, r2, r3, pc}"
45   - );
46   -}
47   -#endif
arch/arm/cpu/armv7/s5pc1xx/clock.c
View file @ 225f5ee
1   -/*
2   - * Copyright (C) 2009 Samsung Electronics
3   - * Minkyu Kang <mk7.kang@samsung.com>
4   - * Heungjun Kim <riverful.kim@samsung.com>
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -#include <common.h>
10   -#include <asm/io.h>
11   -#include <asm/arch/clock.h>
12   -#include <asm/arch/clk.h>
13   -
14   -#define CLK_M 0
15   -#define CLK_D 1
16   -#define CLK_P 2
17   -
18   -#ifndef CONFIG_SYS_CLK_FREQ_C100
19   -#define CONFIG_SYS_CLK_FREQ_C100 12000000
20   -#endif
21   -#ifndef CONFIG_SYS_CLK_FREQ_C110
22   -#define CONFIG_SYS_CLK_FREQ_C110 24000000
23   -#endif
24   -
25   -/* s5pc110: return pll clock frequency */
26   -static unsigned long s5pc100_get_pll_clk(int pllreg)
27   -{
28   - struct s5pc100_clock *clk =
29   - (struct s5pc100_clock *)samsung_get_base_clock();
30   - unsigned long r, m, p, s, mask, fout;
31   - unsigned int freq;
32   -
33   - switch (pllreg) {
34   - case APLL:
35   - r = readl(&clk->apll_con);
36   - break;
37   - case MPLL:
38   - r = readl(&clk->mpll_con);
39   - break;
40   - case EPLL:
41   - r = readl(&clk->epll_con);
42   - break;
43   - case HPLL:
44   - r = readl(&clk->hpll_con);
45   - break;
46   - default:
47   - printf("Unsupported PLL (%d)\n", pllreg);
48   - return 0;
49   - }
50   -
51   - /*
52   - * APLL_CON: MIDV [25:16]
53   - * MPLL_CON: MIDV [23:16]
54   - * EPLL_CON: MIDV [23:16]
55   - * HPLL_CON: MIDV [23:16]
56   - */
57   - if (pllreg == APLL)
58   - mask = 0x3ff;
59   - else
60   - mask = 0x0ff;
61   -
62   - m = (r >> 16) & mask;
63   -
64   - /* PDIV [13:8] */
65   - p = (r >> 8) & 0x3f;
66   - /* SDIV [2:0] */
67   - s = r & 0x7;
68   -
69   - /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
70   - freq = CONFIG_SYS_CLK_FREQ_C100;
71   - fout = m * (freq / (p * (1 << s)));
72   -
73   - return fout;
74   -}
75   -
76   -/* s5pc100: return pll clock frequency */
77   -static unsigned long s5pc110_get_pll_clk(int pllreg)
78   -{
79   - struct s5pc110_clock *clk =
80   - (struct s5pc110_clock *)samsung_get_base_clock();
81   - unsigned long r, m, p, s, mask, fout;
82   - unsigned int freq;
83   -
84   - switch (pllreg) {
85   - case APLL:
86   - r = readl(&clk->apll_con);
87   - break;
88   - case MPLL:
89   - r = readl(&clk->mpll_con);
90   - break;
91   - case EPLL:
92   - r = readl(&clk->epll_con);
93   - break;
94   - case VPLL:
95   - r = readl(&clk->vpll_con);
96   - break;
97   - default:
98   - printf("Unsupported PLL (%d)\n", pllreg);
99   - return 0;
100   - }
101   -
102   - /*
103   - * APLL_CON: MIDV [25:16]
104   - * MPLL_CON: MIDV [25:16]
105   - * EPLL_CON: MIDV [24:16]
106   - * VPLL_CON: MIDV [24:16]
107   - */
108   - if (pllreg == APLL || pllreg == MPLL)
109   - mask = 0x3ff;
110   - else
111   - mask = 0x1ff;
112   -
113   - m = (r >> 16) & mask;
114   -
115   - /* PDIV [13:8] */
116   - p = (r >> 8) & 0x3f;
117   - /* SDIV [2:0] */
118   - s = r & 0x7;
119   -
120   - freq = CONFIG_SYS_CLK_FREQ_C110;
121   - if (pllreg == APLL) {
122   - if (s < 1)
123   - s = 1;
124   - /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
125   - fout = m * (freq / (p * (1 << (s - 1))));
126   - } else
127   - /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
128   - fout = m * (freq / (p * (1 << s)));
129   -
130   - return fout;
131   -}
132   -
133   -/* s5pc110: return ARM clock frequency */
134   -static unsigned long s5pc110_get_arm_clk(void)
135   -{
136   - struct s5pc110_clock *clk =
137   - (struct s5pc110_clock *)samsung_get_base_clock();
138   - unsigned long div;
139   - unsigned long dout_apll, armclk;
140   - unsigned int apll_ratio;
141   -
142   - div = readl(&clk->div0);
143   -
144   - /* APLL_RATIO: [2:0] */
145   - apll_ratio = div & 0x7;
146   -
147   - dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
148   - armclk = dout_apll;
149   -
150   - return armclk;
151   -}
152   -
153   -/* s5pc100: return ARM clock frequency */
154   -static unsigned long s5pc100_get_arm_clk(void)
155   -{
156   - struct s5pc100_clock *clk =
157   - (struct s5pc100_clock *)samsung_get_base_clock();
158   - unsigned long div;
159   - unsigned long dout_apll, armclk;
160   - unsigned int apll_ratio, arm_ratio;
161   -
162   - div = readl(&clk->div0);
163   -
164   - /* ARM_RATIO: [6:4] */
165   - arm_ratio = (div >> 4) & 0x7;
166   - /* APLL_RATIO: [0] */
167   - apll_ratio = div & 0x1;
168   -
169   - dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
170   - armclk = dout_apll / (arm_ratio + 1);
171   -
172   - return armclk;
173   -}
174   -
175   -/* s5pc100: return HCLKD0 frequency */
176   -static unsigned long get_hclk(void)
177   -{
178   - struct s5pc100_clock *clk =
179   - (struct s5pc100_clock *)samsung_get_base_clock();
180   - unsigned long hclkd0;
181   - uint div, d0_bus_ratio;
182   -
183   - div = readl(&clk->div0);
184   - /* D0_BUS_RATIO: [10:8] */
185   - d0_bus_ratio = (div >> 8) & 0x7;
186   -
187   - hclkd0 = get_arm_clk() / (d0_bus_ratio + 1);
188   -
189   - return hclkd0;
190   -}
191   -
192   -/* s5pc100: return PCLKD1 frequency */
193   -static unsigned long get_pclkd1(void)
194   -{
195   - struct s5pc100_clock *clk =
196   - (struct s5pc100_clock *)samsung_get_base_clock();
197   - unsigned long d1_bus, pclkd1;
198   - uint div, d1_bus_ratio, pclkd1_ratio;
199   -
200   - div = readl(&clk->div0);
201   - /* D1_BUS_RATIO: [14:12] */
202   - d1_bus_ratio = (div >> 12) & 0x7;
203   - /* PCLKD1_RATIO: [18:16] */
204   - pclkd1_ratio = (div >> 16) & 0x7;
205   -
206   - /* ASYNC Mode */
207   - d1_bus = get_pll_clk(MPLL) / (d1_bus_ratio + 1);
208   - pclkd1 = d1_bus / (pclkd1_ratio + 1);
209   -
210   - return pclkd1;
211   -}
212   -
213   -/* s5pc110: return HCLKs frequency */
214   -static unsigned long get_hclk_sys(int dom)
215   -{
216   - struct s5pc110_clock *clk =
217   - (struct s5pc110_clock *)samsung_get_base_clock();
218   - unsigned long hclk;
219   - unsigned int div;
220   - unsigned int offset;
221   - unsigned int hclk_sys_ratio;
222   -
223   - if (dom == CLK_M)
224   - return get_hclk();
225   -
226   - div = readl(&clk->div0);
227   -
228   - /*
229   - * HCLK_MSYS_RATIO: [10:8]
230   - * HCLK_DSYS_RATIO: [19:16]
231   - * HCLK_PSYS_RATIO: [27:24]
232   - */
233   - offset = 8 + (dom << 0x3);
234   -
235   - hclk_sys_ratio = (div >> offset) & 0xf;
236   -
237   - hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1);
238   -
239   - return hclk;
240   -}
241   -
242   -/* s5pc110: return PCLKs frequency */
243   -static unsigned long get_pclk_sys(int dom)
244   -{
245   - struct s5pc110_clock *clk =
246   - (struct s5pc110_clock *)samsung_get_base_clock();
247   - unsigned long pclk;
248   - unsigned int div;
249   - unsigned int offset;
250   - unsigned int pclk_sys_ratio;
251   -
252   - div = readl(&clk->div0);
253   -
254   - /*
255   - * PCLK_MSYS_RATIO: [14:12]
256   - * PCLK_DSYS_RATIO: [22:20]
257   - * PCLK_PSYS_RATIO: [30:28]
258   - */
259   - offset = 12 + (dom << 0x3);
260   -
261   - pclk_sys_ratio = (div >> offset) & 0x7;
262   -
263   - pclk = get_hclk_sys(dom) / (pclk_sys_ratio + 1);
264   -
265   - return pclk;
266   -}
267   -
268   -/* s5pc110: return peripheral clock frequency */
269   -static unsigned long s5pc110_get_pclk(void)
270   -{
271   - return get_pclk_sys(CLK_P);
272   -}
273   -
274   -/* s5pc100: return peripheral clock frequency */
275   -static unsigned long s5pc100_get_pclk(void)
276   -{
277   - return get_pclkd1();
278   -}
279   -
280   -/* s5pc1xx: return uart clock frequency */
281   -static unsigned long s5pc1xx_get_uart_clk(int dev_index)
282   -{
283   - if (cpu_is_s5pc110())
284   - return s5pc110_get_pclk();
285   - else
286   - return s5pc100_get_pclk();
287   -}
288   -
289   -/* s5pc1xx: return pwm clock frequency */
290   -static unsigned long s5pc1xx_get_pwm_clk(void)
291   -{
292   - if (cpu_is_s5pc110())
293   - return s5pc110_get_pclk();
294   - else
295   - return s5pc100_get_pclk();
296   -}
297   -
298   -unsigned long get_pll_clk(int pllreg)
299   -{
300   - if (cpu_is_s5pc110())
301   - return s5pc110_get_pll_clk(pllreg);
302   - else
303   - return s5pc100_get_pll_clk(pllreg);
304   -}
305   -
306   -unsigned long get_arm_clk(void)
307   -{
308   - if (cpu_is_s5pc110())
309   - return s5pc110_get_arm_clk();
310   - else
311   - return s5pc100_get_arm_clk();
312   -}
313   -
314   -unsigned long get_pwm_clk(void)
315   -{
316   - return s5pc1xx_get_pwm_clk();
317   -}
318   -
319   -unsigned long get_uart_clk(int dev_index)
320   -{
321   - return s5pc1xx_get_uart_clk(dev_index);
322   -}
323   -
324   -void set_mmc_clk(int dev_index, unsigned int div)
325   -{
326   - /* Do NOTHING */
327   -}
arch/arm/cpu/armv7/s5pc1xx/reset.S
View file @ 225f5ee
1   -/*
2   - * Copyright (c) 2009 Samsung Electronics.
3   - * Minkyu Kang <mk7.kang@samsung.com>
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <asm/arch/cpu.h>
9   -#include <linux/linkage.h>
10   -
11   -#define S5PC100_SWRESET 0xE0200000
12   -#define S5PC110_SWRESET 0xE0102000
13   -
14   -ENTRY(reset_cpu)
15   - ldr r1, =S5PC100_PRO_ID
16   - ldr r2, [r1]
17   - ldr r4, =0x00010000
18   - and r4, r2, r4
19   - cmp r4, #0
20   - bne 110f
21   - /* S5PC100 */
22   - ldr r1, =S5PC100_SWRESET
23   - ldr r2, =0xC100
24   - b 200f
25   -110: /* S5PC110 */
26   - ldr r1, =S5PC110_SWRESET
27   - mov r2, #1
28   -200:
29   - str r2, [r1]
30   -_loop_forever:
31   - b _loop_forever
32   -ENDPROC(reset_cpu)
arch/arm/include/asm/arch-s5pc1xx/clk.h
View file @ 225f5ee
1   -/*
2   - * (C) Copyright 2009 Samsung Electronics
3   - * Minkyu Kang <mk7.kang@samsung.com>
4   - * Heungjun Kim <riverful.kim@samsung.com>
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -#ifndef __ASM_ARM_ARCH_CLK_H_
10   -#define __ASM_ARM_ARCH_CLK_H_
11   -
12   -#define APLL 0
13   -#define MPLL 1
14   -#define EPLL 2
15   -#define HPLL 3
16   -#define VPLL 4
17   -
18   -unsigned long get_pll_clk(int pllreg);
19   -unsigned long get_arm_clk(void);
20   -unsigned long get_pwm_clk(void);
21   -unsigned long get_uart_clk(int dev_index);
22   -void set_mmc_clk(int dev_index, unsigned int div);
23   -
24   -#endif
arch/arm/include/asm/arch-s5pc1xx/clock.h
View file @ 225f5ee
1   -/*
2   - * (C) Copyright 2009 Samsung Electronics
3   - * Minkyu Kang <mk7.kang@samsung.com>
4   - * Heungjun Kim <riverful.kim@samsung.com>
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -#ifndef __ASM_ARM_ARCH_CLOCK_H_
10   -#define __ASM_ARM_ARCH_CLOCK_H_
11   -
12   -#ifndef __ASSEMBLY__
13   -struct s5pc100_clock {
14   - unsigned int apll_lock;
15   - unsigned int mpll_lock;
16   - unsigned int epll_lock;
17   - unsigned int hpll_lock;
18   - unsigned char res1[0xf0];
19   - unsigned int apll_con;
20   - unsigned int mpll_con;
21   - unsigned int epll_con;
22   - unsigned int hpll_con;
23   - unsigned char res2[0xf0];
24   - unsigned int src0;
25   - unsigned int src1;
26   - unsigned int src2;
27   - unsigned int src3;
28   - unsigned char res3[0xf0];
29   - unsigned int div0;
30   - unsigned int div1;
31   - unsigned int div2;
32   - unsigned int div3;
33   - unsigned int div4;
34   - unsigned char res4[0x1ec];
35   - unsigned int gate_d00;
36   - unsigned int gate_d01;
37   - unsigned int gate_d02;
38   - unsigned char res5[0x54];
39   - unsigned int gate_sclk0;
40   - unsigned int gate_sclk1;
41   -};
42   -
43   -struct s5pc110_clock {
44   - unsigned int apll_lock;
45   - unsigned char res1[0x4];
46   - unsigned int mpll_lock;
47   - unsigned char res2[0x4];
48   - unsigned int epll_lock;
49   - unsigned char res3[0xc];
50   - unsigned int vpll_lock;
51   - unsigned char res4[0xdc];
52   - unsigned int apll_con;
53   - unsigned char res5[0x4];
54   - unsigned int mpll_con;
55   - unsigned char res6[0x4];
56   - unsigned int epll_con;
57   - unsigned char res7[0xc];
58   - unsigned int vpll_con;
59   - unsigned char res8[0xdc];
60   - unsigned int src0;
61   - unsigned int src1;
62   - unsigned int src2;
63   - unsigned int src3;
64   - unsigned char res9[0xf0];
65   - unsigned int div0;
66   - unsigned int div1;
67   - unsigned int div2;
68   - unsigned int div3;
69   - unsigned int div4;
70   - unsigned char res10[0x1ec];
71   - unsigned int gate_d00;
72   - unsigned int gate_d01;
73   - unsigned int gate_d02;
74   - unsigned char res11[0x54];
75   - unsigned int gate_sclk0;
76   - unsigned int gate_sclk1;
77   -};
78   -#endif
79   -
80   -#endif
arch/arm/include/asm/arch-s5pc1xx/cpu.h
View file @ 225f5ee
1   -/*
2   - * (C) Copyright 2009 Samsung Electronics
3   - * Minkyu Kang <mk7.kang@samsung.com>
4   - * Heungjun Kim <riverful.kim@samsung.com>
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -#ifndef _S5PC1XX_CPU_H
10   -#define _S5PC1XX_CPU_H
11   -
12   -#define S5P_CPU_NAME "S5P"
13   -#define S5PC1XX_ADDR_BASE 0xE0000000
14   -
15   -/* S5PC100 */
16   -#define S5PC100_PRO_ID 0xE0000000
17   -#define S5PC100_CLOCK_BASE 0xE0100000
18   -#define S5PC100_GPIO_BASE 0xE0300000
19   -#define S5PC100_VIC0_BASE 0xE4000000
20   -#define S5PC100_VIC1_BASE 0xE4100000
21   -#define S5PC100_VIC2_BASE 0xE4200000
22   -#define S5PC100_DMC_BASE 0xE6000000
23   -#define S5PC100_SROMC_BASE 0xE7000000
24   -#define S5PC100_ONENAND_BASE 0xE7100000
25   -#define S5PC100_PWMTIMER_BASE 0xEA000000
26   -#define S5PC100_WATCHDOG_BASE 0xEA200000
27   -#define S5PC100_UART_BASE 0xEC000000
28   -#define S5PC100_MMC_BASE 0xED800000
29   -
30   -/* S5PC110 */
31   -#define S5PC110_PRO_ID 0xE0000000
32   -#define S5PC110_CLOCK_BASE 0xE0100000
33   -#define S5PC110_GPIO_BASE 0xE0200000
34   -#define S5PC110_PWMTIMER_BASE 0xE2500000
35   -#define S5PC110_WATCHDOG_BASE 0xE2700000
36   -#define S5PC110_UART_BASE 0xE2900000
37   -#define S5PC110_SROMC_BASE 0xE8000000
38   -#define S5PC110_MMC_BASE 0xEB000000
39   -#define S5PC110_DMC0_BASE 0xF0000000
40   -#define S5PC110_DMC1_BASE 0xF1400000
41   -#define S5PC110_VIC0_BASE 0xF2000000
42   -#define S5PC110_VIC1_BASE 0xF2100000
43   -#define S5PC110_VIC2_BASE 0xF2200000
44   -#define S5PC110_VIC3_BASE 0xF2300000
45   -#define S5PC110_OTG_BASE 0xEC000000
46   -#define S5PC110_PHY_BASE 0xEC100000
47   -#define S5PC110_USB_PHY_CONTROL 0xE010E80C
48   -
49   -
50   -#ifndef __ASSEMBLY__
51   -#include <asm/io.h>
52   -/* CPU detection macros */
53   -extern unsigned int s5p_cpu_id;
54   -extern unsigned int s5p_cpu_rev;
55   -
56   -static inline int s5p_get_cpu_rev(void)
57   -{
58   - return s5p_cpu_rev;
59   -}
60   -
61   -static inline void s5p_set_cpu_id(void)
62   -{
63   - s5p_cpu_id = readl(S5PC100_PRO_ID);
64   - s5p_cpu_rev = s5p_cpu_id & 0x000000FF;
65   - s5p_cpu_id = 0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12);
66   -}
67   -
68   -static inline char *s5p_get_cpu_name(void)
69   -{
70   - return S5P_CPU_NAME;
71   -}
72   -
73   -#define IS_SAMSUNG_TYPE(type, id) \
74   -static inline int cpu_is_##type(void) \
75   -{ \
76   - return s5p_cpu_id == id ? 1 : 0; \
77   -}
78   -
79   -IS_SAMSUNG_TYPE(s5pc100, 0xc100)
80   -IS_SAMSUNG_TYPE(s5pc110, 0xc110)
81   -
82   -#define SAMSUNG_BASE(device, base) \
83   -static inline unsigned int samsung_get_base_##device(void) \
84   -{ \
85   - if (cpu_is_s5pc100()) \
86   - return S5PC100_##base; \
87   - else if (cpu_is_s5pc110()) \
88   - return S5PC110_##base; \
89   - else \
90   - return 0; \
91   -}
92   -
93   -SAMSUNG_BASE(clock, CLOCK_BASE)
94   -SAMSUNG_BASE(gpio, GPIO_BASE)
95   -SAMSUNG_BASE(pro_id, PRO_ID)
96   -SAMSUNG_BASE(mmc, MMC_BASE)
97   -SAMSUNG_BASE(sromc, SROMC_BASE)
98   -SAMSUNG_BASE(timer, PWMTIMER_BASE)
99   -SAMSUNG_BASE(uart, UART_BASE)
100   -SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
101   -#endif
102   -
103   -#endif /* _S5PC1XX_CPU_H */
arch/arm/include/asm/arch-s5pc1xx/gpio.h
View file @ 225f5ee
1   -/*
2   - * (C) Copyright 2009 Samsung Electronics
3   - * Minkyu Kang <mk7.kang@samsung.com>
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#ifndef __ASM_ARCH_GPIO_H
9   -#define __ASM_ARCH_GPIO_H
10   -
11   -#ifndef __ASSEMBLY__
12   -struct s5p_gpio_bank {
13   - unsigned int con;
14   - unsigned int dat;
15   - unsigned int pull;
16   - unsigned int drv;
17   - unsigned int pdn_con;
18   - unsigned int pdn_pull;
19   - unsigned char res1[8];
20   -};
21   -
22   -/* A list of valid GPIO numbers for the asm-generic/gpio.h interface */
23   -enum s5pc100_gpio_pin {
24   - S5PC100_GPIO_A00,
25   - S5PC100_GPIO_A01,
26   - S5PC100_GPIO_A02,
27   - S5PC100_GPIO_A03,
28   - S5PC100_GPIO_A04,
29   - S5PC100_GPIO_A05,
30   - S5PC100_GPIO_A06,
31   - S5PC100_GPIO_A07,
32   - S5PC100_GPIO_A10,
33   - S5PC100_GPIO_A11,
34   - S5PC100_GPIO_A12,
35   - S5PC100_GPIO_A13,
36   - S5PC100_GPIO_A14,
37   - S5PC100_GPIO_A15,
38   - S5PC100_GPIO_A16,
39   - S5PC100_GPIO_A17,
40   - S5PC100_GPIO_B0,
41   - S5PC100_GPIO_B1,
42   - S5PC100_GPIO_B2,
43   - S5PC100_GPIO_B3,
44   - S5PC100_GPIO_B4,
45   - S5PC100_GPIO_B5,
46   - S5PC100_GPIO_B6,
47   - S5PC100_GPIO_B7,
48   - S5PC100_GPIO_C0,
49   - S5PC100_GPIO_C1,
50   - S5PC100_GPIO_C2,
51   - S5PC100_GPIO_C3,
52   - S5PC100_GPIO_C4,
53   - S5PC100_GPIO_C5,
54   - S5PC100_GPIO_C6,
55   - S5PC100_GPIO_C7,
56   - S5PC100_GPIO_D0,
57   - S5PC100_GPIO_D1,
58   - S5PC100_GPIO_D2,
59   - S5PC100_GPIO_D3,
60   - S5PC100_GPIO_D4,
61   - S5PC100_GPIO_D5,
62   - S5PC100_GPIO_D6,
63   - S5PC100_GPIO_D7,
64   - S5PC100_GPIO_E00,
65   - S5PC100_GPIO_E01,
66   - S5PC100_GPIO_E02,
67   - S5PC100_GPIO_E03,
68   - S5PC100_GPIO_E04,
69   - S5PC100_GPIO_E05,
70   - S5PC100_GPIO_E06,
71   - S5PC100_GPIO_E07,
72   - S5PC100_GPIO_E10,
73   - S5PC100_GPIO_E11,
74   - S5PC100_GPIO_E12,
75   - S5PC100_GPIO_E13,
76   - S5PC100_GPIO_E14,
77   - S5PC100_GPIO_E15,
78   - S5PC100_GPIO_E16,
79   - S5PC100_GPIO_E17,
80   - S5PC100_GPIO_F00,
81   - S5PC100_GPIO_F01,
82   - S5PC100_GPIO_F02,
83   - S5PC100_GPIO_F03,
84   - S5PC100_GPIO_F04,
85   - S5PC100_GPIO_F05,
86   - S5PC100_GPIO_F06,
87   - S5PC100_GPIO_F07,
88   - S5PC100_GPIO_F10,
89   - S5PC100_GPIO_F11,
90   - S5PC100_GPIO_F12,
91   - S5PC100_GPIO_F13,
92   - S5PC100_GPIO_F14,
93   - S5PC100_GPIO_F15,
94   - S5PC100_GPIO_F16,
95   - S5PC100_GPIO_F17,
96   - S5PC100_GPIO_F20,
97   - S5PC100_GPIO_F21,
98   - S5PC100_GPIO_F22,
99   - S5PC100_GPIO_F23,
100   - S5PC100_GPIO_F24,
101   - S5PC100_GPIO_F25,
102   - S5PC100_GPIO_F26,
103   - S5PC100_GPIO_F27,
104   - S5PC100_GPIO_F30,
105   - S5PC100_GPIO_F31,
106   - S5PC100_GPIO_F32,
107   - S5PC100_GPIO_F33,
108   - S5PC100_GPIO_F34,
109   - S5PC100_GPIO_F35,
110   - S5PC100_GPIO_F36,
111   - S5PC100_GPIO_F37,
112   - S5PC100_GPIO_G00,
113   - S5PC100_GPIO_G01,
114   - S5PC100_GPIO_G02,
115   - S5PC100_GPIO_G03,
116   - S5PC100_GPIO_G04,
117   - S5PC100_GPIO_G05,
118   - S5PC100_GPIO_G06,
119   - S5PC100_GPIO_G07,
120   - S5PC100_GPIO_G10,
121   - S5PC100_GPIO_G11,
122   - S5PC100_GPIO_G12,
123   - S5PC100_GPIO_G13,
124   - S5PC100_GPIO_G14,
125   - S5PC100_GPIO_G15,
126   - S5PC100_GPIO_G16,
127   - S5PC100_GPIO_G17,
128   - S5PC100_GPIO_G20,
129   - S5PC100_GPIO_G21,
130   - S5PC100_GPIO_G22,
131   - S5PC100_GPIO_G23,
132   - S5PC100_GPIO_G24,
133   - S5PC100_GPIO_G25,
134   - S5PC100_GPIO_G26,
135   - S5PC100_GPIO_G27,
136   - S5PC100_GPIO_G30,
137   - S5PC100_GPIO_G31,
138   - S5PC100_GPIO_G32,
139   - S5PC100_GPIO_G33,
140   - S5PC100_GPIO_G34,
141   - S5PC100_GPIO_G35,
142   - S5PC100_GPIO_G36,
143   - S5PC100_GPIO_G37,
144   - S5PC100_GPIO_I0,
145   - S5PC100_GPIO_I1,
146   - S5PC100_GPIO_I2,
147   - S5PC100_GPIO_I3,
148   - S5PC100_GPIO_I4,
149   - S5PC100_GPIO_I5,
150   - S5PC100_GPIO_I6,
151   - S5PC100_GPIO_I7,
152   - S5PC100_GPIO_J00,
153   - S5PC100_GPIO_J01,
154   - S5PC100_GPIO_J02,
155   - S5PC100_GPIO_J03,
156   - S5PC100_GPIO_J04,
157   - S5PC100_GPIO_J05,
158   - S5PC100_GPIO_J06,
159   - S5PC100_GPIO_J07,
160   - S5PC100_GPIO_J10,
161   - S5PC100_GPIO_J11,
162   - S5PC100_GPIO_J12,
163   - S5PC100_GPIO_J13,
164   - S5PC100_GPIO_J14,
165   - S5PC100_GPIO_J15,
166   - S5PC100_GPIO_J16,
167   - S5PC100_GPIO_J17,
168   - S5PC100_GPIO_J20,
169   - S5PC100_GPIO_J21,
170   - S5PC100_GPIO_J22,
171   - S5PC100_GPIO_J23,
172   - S5PC100_GPIO_J24,
173   - S5PC100_GPIO_J25,
174   - S5PC100_GPIO_J26,
175   - S5PC100_GPIO_J27,
176   - S5PC100_GPIO_J30,
177   - S5PC100_GPIO_J31,
178   - S5PC100_GPIO_J32,
179   - S5PC100_GPIO_J33,
180   - S5PC100_GPIO_J34,
181   - S5PC100_GPIO_J35,
182   - S5PC100_GPIO_J36,
183   - S5PC100_GPIO_J37,
184   - S5PC100_GPIO_J40,
185   - S5PC100_GPIO_J41,
186   - S5PC100_GPIO_J42,
187   - S5PC100_GPIO_J43,
188   - S5PC100_GPIO_J44,
189   - S5PC100_GPIO_J45,
190   - S5PC100_GPIO_J46,
191   - S5PC100_GPIO_J47,
192   - S5PC100_GPIO_K00,
193   - S5PC100_GPIO_K01,
194   - S5PC100_GPIO_K02,
195   - S5PC100_GPIO_K03,
196   - S5PC100_GPIO_K04,
197   - S5PC100_GPIO_K05,
198   - S5PC100_GPIO_K06,
199   - S5PC100_GPIO_K07,
200   - S5PC100_GPIO_K10,
201   - S5PC100_GPIO_K11,
202   - S5PC100_GPIO_K12,
203   - S5PC100_GPIO_K13,
204   - S5PC100_GPIO_K14,
205   - S5PC100_GPIO_K15,
206   - S5PC100_GPIO_K16,
207   - S5PC100_GPIO_K17,
208   - S5PC100_GPIO_K20,
209   - S5PC100_GPIO_K21,
210   - S5PC100_GPIO_K22,
211   - S5PC100_GPIO_K23,
212   - S5PC100_GPIO_K24,
213   - S5PC100_GPIO_K25,
214   - S5PC100_GPIO_K26,
215   - S5PC100_GPIO_K27,
216   - S5PC100_GPIO_K30,
217   - S5PC100_GPIO_K31,
218   - S5PC100_GPIO_K32,
219   - S5PC100_GPIO_K33,
220   - S5PC100_GPIO_K34,
221   - S5PC100_GPIO_K35,
222   - S5PC100_GPIO_K36,
223   - S5PC100_GPIO_K37,
224   - S5PC100_GPIO_L00,
225   - S5PC100_GPIO_L01,
226   - S5PC100_GPIO_L02,
227   - S5PC100_GPIO_L03,
228   - S5PC100_GPIO_L04,
229   - S5PC100_GPIO_L05,
230   - S5PC100_GPIO_L06,
231   - S5PC100_GPIO_L07,
232   - S5PC100_GPIO_L10,
233   - S5PC100_GPIO_L11,
234   - S5PC100_GPIO_L12,
235   - S5PC100_GPIO_L13,
236   - S5PC100_GPIO_L14,
237   - S5PC100_GPIO_L15,
238   - S5PC100_GPIO_L16,
239   - S5PC100_GPIO_L17,
240   - S5PC100_GPIO_L20,
241   - S5PC100_GPIO_L21,
242   - S5PC100_GPIO_L22,
243   - S5PC100_GPIO_L23,
244   - S5PC100_GPIO_L24,
245   - S5PC100_GPIO_L25,
246   - S5PC100_GPIO_L26,
247   - S5PC100_GPIO_L27,
248   - S5PC100_GPIO_L30,
249   - S5PC100_GPIO_L31,
250   - S5PC100_GPIO_L32,
251   - S5PC100_GPIO_L33,
252   - S5PC100_GPIO_L34,
253   - S5PC100_GPIO_L35,
254   - S5PC100_GPIO_L36,
255   - S5PC100_GPIO_L37,
256   - S5PC100_GPIO_L40,
257   - S5PC100_GPIO_L41,
258   - S5PC100_GPIO_L42,
259   - S5PC100_GPIO_L43,
260   - S5PC100_GPIO_L44,
261   - S5PC100_GPIO_L45,
262   - S5PC100_GPIO_L46,
263   - S5PC100_GPIO_L47,
264   - S5PC100_GPIO_H00,
265   - S5PC100_GPIO_H01,
266   - S5PC100_GPIO_H02,
267   - S5PC100_GPIO_H03,
268   - S5PC100_GPIO_H04,
269   - S5PC100_GPIO_H05,
270   - S5PC100_GPIO_H06,
271   - S5PC100_GPIO_H07,
272   - S5PC100_GPIO_H10,
273   - S5PC100_GPIO_H11,
274   - S5PC100_GPIO_H12,
275   - S5PC100_GPIO_H13,
276   - S5PC100_GPIO_H14,
277   - S5PC100_GPIO_H15,
278   - S5PC100_GPIO_H16,
279   - S5PC100_GPIO_H17,
280   - S5PC100_GPIO_H20,
281   - S5PC100_GPIO_H21,
282   - S5PC100_GPIO_H22,
283   - S5PC100_GPIO_H23,
284   - S5PC100_GPIO_H24,
285   - S5PC100_GPIO_H25,
286   - S5PC100_GPIO_H26,
287   - S5PC100_GPIO_H27,
288   - S5PC100_GPIO_H30,
289   - S5PC100_GPIO_H31,
290   - S5PC100_GPIO_H32,
291   - S5PC100_GPIO_H33,
292   - S5PC100_GPIO_H34,
293   - S5PC100_GPIO_H35,
294   - S5PC100_GPIO_H36,
295   - S5PC100_GPIO_H37,
296   -
297   - S5PC100_GPIO_MAX_PORT
298   -};
299   -
300   -enum s5pc110_gpio_pin {
301   - S5PC110_GPIO_A00,
302   - S5PC110_GPIO_A01,
303   - S5PC110_GPIO_A02,
304   - S5PC110_GPIO_A03,
305   - S5PC110_GPIO_A04,
306   - S5PC110_GPIO_A05,
307   - S5PC110_GPIO_A06,
308   - S5PC110_GPIO_A07,
309   - S5PC110_GPIO_A10,
310   - S5PC110_GPIO_A11,
311   - S5PC110_GPIO_A12,
312   - S5PC110_GPIO_A13,
313   - S5PC110_GPIO_A14,
314   - S5PC110_GPIO_A15,
315   - S5PC110_GPIO_A16,
316   - S5PC110_GPIO_A17,
317   - S5PC110_GPIO_B0,
318   - S5PC110_GPIO_B1,
319   - S5PC110_GPIO_B2,
320   - S5PC110_GPIO_B3,
321   - S5PC110_GPIO_B4,
322   - S5PC110_GPIO_B5,
323   - S5PC110_GPIO_B6,
324   - S5PC110_GPIO_B7,
325   - S5PC110_GPIO_C00,
326   - S5PC110_GPIO_C01,
327   - S5PC110_GPIO_C02,
328   - S5PC110_GPIO_C03,
329   - S5PC110_GPIO_C04,
330   - S5PC110_GPIO_C05,
331   - S5PC110_GPIO_C06,
332   - S5PC110_GPIO_C07,
333   - S5PC110_GPIO_C10,
334   - S5PC110_GPIO_C11,
335   - S5PC110_GPIO_C12,
336   - S5PC110_GPIO_C13,
337   - S5PC110_GPIO_C14,
338   - S5PC110_GPIO_C15,
339   - S5PC110_GPIO_C16,
340   - S5PC110_GPIO_C17,
341   - S5PC110_GPIO_D00,
342   - S5PC110_GPIO_D01,
343   - S5PC110_GPIO_D02,
344   - S5PC110_GPIO_D03,
345   - S5PC110_GPIO_D04,
346   - S5PC110_GPIO_D05,
347   - S5PC110_GPIO_D06,
348   - S5PC110_GPIO_D07,
349   - S5PC110_GPIO_D10,
350   - S5PC110_GPIO_D11,
351   - S5PC110_GPIO_D12,
352   - S5PC110_GPIO_D13,
353   - S5PC110_GPIO_D14,
354   - S5PC110_GPIO_D15,
355   - S5PC110_GPIO_D16,
356   - S5PC110_GPIO_D17,
357   - S5PC110_GPIO_E00,
358   - S5PC110_GPIO_E01,
359   - S5PC110_GPIO_E02,
360   - S5PC110_GPIO_E03,
361   - S5PC110_GPIO_E04,
362   - S5PC110_GPIO_E05,
363   - S5PC110_GPIO_E06,
364   - S5PC110_GPIO_E07,
365   - S5PC110_GPIO_E10,
366   - S5PC110_GPIO_E11,
367   - S5PC110_GPIO_E12,
368   - S5PC110_GPIO_E13,
369   - S5PC110_GPIO_E14,
370   - S5PC110_GPIO_E15,
371   - S5PC110_GPIO_E16,
372   - S5PC110_GPIO_E17,
373   - S5PC110_GPIO_F00,
374   - S5PC110_GPIO_F01,
375   - S5PC110_GPIO_F02,
376   - S5PC110_GPIO_F03,
377   - S5PC110_GPIO_F04,
378   - S5PC110_GPIO_F05,
379   - S5PC110_GPIO_F06,
380   - S5PC110_GPIO_F07,
381   - S5PC110_GPIO_F10,
382   - S5PC110_GPIO_F11,
383   - S5PC110_GPIO_F12,
384   - S5PC110_GPIO_F13,
385   - S5PC110_GPIO_F14,
386   - S5PC110_GPIO_F15,
387   - S5PC110_GPIO_F16,
388   - S5PC110_GPIO_F17,
389   - S5PC110_GPIO_F20,
390   - S5PC110_GPIO_F21,
391   - S5PC110_GPIO_F22,
392   - S5PC110_GPIO_F23,
393   - S5PC110_GPIO_F24,
394   - S5PC110_GPIO_F25,
395   - S5PC110_GPIO_F26,
396   - S5PC110_GPIO_F27,
397   - S5PC110_GPIO_F30,
398   - S5PC110_GPIO_F31,
399   - S5PC110_GPIO_F32,
400   - S5PC110_GPIO_F33,
401   - S5PC110_GPIO_F34,
402   - S5PC110_GPIO_F35,
403   - S5PC110_GPIO_F36,
404   - S5PC110_GPIO_F37,
405   - S5PC110_GPIO_G00,
406   - S5PC110_GPIO_G01,
407   - S5PC110_GPIO_G02,
408   - S5PC110_GPIO_G03,
409   - S5PC110_GPIO_G04,
410   - S5PC110_GPIO_G05,
411   - S5PC110_GPIO_G06,
412   - S5PC110_GPIO_G07,
413   - S5PC110_GPIO_G10,
414   - S5PC110_GPIO_G11,
415   - S5PC110_GPIO_G12,
416   - S5PC110_GPIO_G13,
417   - S5PC110_GPIO_G14,
418   - S5PC110_GPIO_G15,
419   - S5PC110_GPIO_G16,
420   - S5PC110_GPIO_G17,
421   - S5PC110_GPIO_G20,
422   - S5PC110_GPIO_G21,
423   - S5PC110_GPIO_G22,
424   - S5PC110_GPIO_G23,
425   - S5PC110_GPIO_G24,
426   - S5PC110_GPIO_G25,
427   - S5PC110_GPIO_G26,
428   - S5PC110_GPIO_G27,
429   - S5PC110_GPIO_G30,
430   - S5PC110_GPIO_G31,
431   - S5PC110_GPIO_G32,
432   - S5PC110_GPIO_G33,
433   - S5PC110_GPIO_G34,
434   - S5PC110_GPIO_G35,
435   - S5PC110_GPIO_G36,
436   - S5PC110_GPIO_G37,
437   - S5PC110_GPIO_I0,
438   - S5PC110_GPIO_I1,
439   - S5PC110_GPIO_I2,
440   - S5PC110_GPIO_I3,
441   - S5PC110_GPIO_I4,
442   - S5PC110_GPIO_I5,
443   - S5PC110_GPIO_I6,
444   - S5PC110_GPIO_I7,
445   - S5PC110_GPIO_J00,
446   - S5PC110_GPIO_J01,
447   - S5PC110_GPIO_J02,
448   - S5PC110_GPIO_J03,
449   - S5PC110_GPIO_J04,
450   - S5PC110_GPIO_J05,
451   - S5PC110_GPIO_J06,
452   - S5PC110_GPIO_J07,
453   - S5PC110_GPIO_J10,
454   - S5PC110_GPIO_J11,
455   - S5PC110_GPIO_J12,
456   - S5PC110_GPIO_J13,
457   - S5PC110_GPIO_J14,
458   - S5PC110_GPIO_J15,
459   - S5PC110_GPIO_J16,
460   - S5PC110_GPIO_J17,
461   - S5PC110_GPIO_J20,
462   - S5PC110_GPIO_J21,
463   - S5PC110_GPIO_J22,
464   - S5PC110_GPIO_J23,
465   - S5PC110_GPIO_J24,
466   - S5PC110_GPIO_J25,
467   - S5PC110_GPIO_J26,
468   - S5PC110_GPIO_J27,
469   - S5PC110_GPIO_J30,
470   - S5PC110_GPIO_J31,
471   - S5PC110_GPIO_J32,
472   - S5PC110_GPIO_J33,
473   - S5PC110_GPIO_J34,
474   - S5PC110_GPIO_J35,
475   - S5PC110_GPIO_J36,
476   - S5PC110_GPIO_J37,
477   - S5PC110_GPIO_J40,
478   - S5PC110_GPIO_J41,
479   - S5PC110_GPIO_J42,
480   - S5PC110_GPIO_J43,
481   - S5PC110_GPIO_J44,
482   - S5PC110_GPIO_J45,
483   - S5PC110_GPIO_J46,
484   - S5PC110_GPIO_J47,
485   - S5PC110_GPIO_MP010,
486   - S5PC110_GPIO_MP011,
487   - S5PC110_GPIO_MP012,
488   - S5PC110_GPIO_MP013,
489   - S5PC110_GPIO_MP014,
490   - S5PC110_GPIO_MP015,
491   - S5PC110_GPIO_MP016,
492   - S5PC110_GPIO_MP017,
493   - S5PC110_GPIO_MP020,
494   - S5PC110_GPIO_MP021,
495   - S5PC110_GPIO_MP022,
496   - S5PC110_GPIO_MP023,
497   - S5PC110_GPIO_MP024,
498   - S5PC110_GPIO_MP025,
499   - S5PC110_GPIO_MP026,
500   - S5PC110_GPIO_MP027,
501   - S5PC110_GPIO_MP030,
502   - S5PC110_GPIO_MP031,
503   - S5PC110_GPIO_MP032,
504   - S5PC110_GPIO_MP033,
505   - S5PC110_GPIO_MP034,
506   - S5PC110_GPIO_MP035,
507   - S5PC110_GPIO_MP036,
508   - S5PC110_GPIO_MP037,
509   - S5PC110_GPIO_MP040,
510   - S5PC110_GPIO_MP041,
511   - S5PC110_GPIO_MP042,
512   - S5PC110_GPIO_MP043,
513   - S5PC110_GPIO_MP044,
514   - S5PC110_GPIO_MP045,
515   - S5PC110_GPIO_MP046,
516   - S5PC110_GPIO_MP047,
517   - S5PC110_GPIO_MP050,
518   - S5PC110_GPIO_MP051,
519   - S5PC110_GPIO_MP052,
520   - S5PC110_GPIO_MP053,
521   - S5PC110_GPIO_MP054,
522   - S5PC110_GPIO_MP055,
523   - S5PC110_GPIO_MP056,
524   - S5PC110_GPIO_MP057,
525   - S5PC110_GPIO_MP060,
526   - S5PC110_GPIO_MP061,
527   - S5PC110_GPIO_MP062,
528   - S5PC110_GPIO_MP063,
529   - S5PC110_GPIO_MP064,
530   - S5PC110_GPIO_MP065,
531   - S5PC110_GPIO_MP066,
532   - S5PC110_GPIO_MP067,
533   - S5PC110_GPIO_MP070,
534   - S5PC110_GPIO_MP071,
535   - S5PC110_GPIO_MP072,
536   - S5PC110_GPIO_MP073,
537   - S5PC110_GPIO_MP074,
538   - S5PC110_GPIO_MP075,
539   - S5PC110_GPIO_MP076,
540   - S5PC110_GPIO_MP077,
541   - S5PC110_GPIO_MP100,
542   - S5PC110_GPIO_MP101,
543   - S5PC110_GPIO_MP102,
544   - S5PC110_GPIO_MP103,
545   - S5PC110_GPIO_MP104,
546   - S5PC110_GPIO_MP105,
547   - S5PC110_GPIO_MP106,
548   - S5PC110_GPIO_MP107,
549   - S5PC110_GPIO_MP110,
550   - S5PC110_GPIO_MP111,
551   - S5PC110_GPIO_MP112,
552   - S5PC110_GPIO_MP113,
553   - S5PC110_GPIO_MP114,
554   - S5PC110_GPIO_MP115,
555   - S5PC110_GPIO_MP116,
556   - S5PC110_GPIO_MP117,
557   - S5PC110_GPIO_MP120,
558   - S5PC110_GPIO_MP121,
559   - S5PC110_GPIO_MP122,
560   - S5PC110_GPIO_MP123,
561   - S5PC110_GPIO_MP124,
562   - S5PC110_GPIO_MP125,
563   - S5PC110_GPIO_MP126,
564   - S5PC110_GPIO_MP127,
565   - S5PC110_GPIO_MP130,
566   - S5PC110_GPIO_MP131,
567   - S5PC110_GPIO_MP132,
568   - S5PC110_GPIO_MP133,
569   - S5PC110_GPIO_MP134,
570   - S5PC110_GPIO_MP135,
571   - S5PC110_GPIO_MP136,
572   - S5PC110_GPIO_MP137,
573   - S5PC110_GPIO_MP140,
574   - S5PC110_GPIO_MP141,
575   - S5PC110_GPIO_MP142,
576   - S5PC110_GPIO_MP143,
577   - S5PC110_GPIO_MP144,
578   - S5PC110_GPIO_MP145,
579   - S5PC110_GPIO_MP146,
580   - S5PC110_GPIO_MP147,
581   - S5PC110_GPIO_MP150,
582   - S5PC110_GPIO_MP151,
583   - S5PC110_GPIO_MP152,
584   - S5PC110_GPIO_MP153,
585   - S5PC110_GPIO_MP154,
586   - S5PC110_GPIO_MP155,
587   - S5PC110_GPIO_MP156,
588   - S5PC110_GPIO_MP157,
589   - S5PC110_GPIO_MP160,
590   - S5PC110_GPIO_MP161,
591   - S5PC110_GPIO_MP162,
592   - S5PC110_GPIO_MP163,
593   - S5PC110_GPIO_MP164,
594   - S5PC110_GPIO_MP165,
595   - S5PC110_GPIO_MP166,
596   - S5PC110_GPIO_MP167,
597   - S5PC110_GPIO_MP170,
598   - S5PC110_GPIO_MP171,
599   - S5PC110_GPIO_MP172,
600   - S5PC110_GPIO_MP173,
601   - S5PC110_GPIO_MP174,
602   - S5PC110_GPIO_MP175,
603   - S5PC110_GPIO_MP176,
604   - S5PC110_GPIO_MP177,
605   - S5PC110_GPIO_MP180,
606   - S5PC110_GPIO_MP181,
607   - S5PC110_GPIO_MP182,
608   - S5PC110_GPIO_MP183,
609   - S5PC110_GPIO_MP184,
610   - S5PC110_GPIO_MP185,
611   - S5PC110_GPIO_MP186,
612   - S5PC110_GPIO_MP187,
613   - S5PC110_GPIO_MP200,
614   - S5PC110_GPIO_MP201,
615   - S5PC110_GPIO_MP202,
616   - S5PC110_GPIO_MP203,
617   - S5PC110_GPIO_MP204,
618   - S5PC110_GPIO_MP205,
619   - S5PC110_GPIO_MP206,
620   - S5PC110_GPIO_MP207,
621   - S5PC110_GPIO_MP210,
622   - S5PC110_GPIO_MP211,
623   - S5PC110_GPIO_MP212,
624   - S5PC110_GPIO_MP213,
625   - S5PC110_GPIO_MP214,
626   - S5PC110_GPIO_MP215,
627   - S5PC110_GPIO_MP216,
628   - S5PC110_GPIO_MP217,
629   - S5PC110_GPIO_MP220,
630   - S5PC110_GPIO_MP221,
631   - S5PC110_GPIO_MP222,
632   - S5PC110_GPIO_MP223,
633   - S5PC110_GPIO_MP224,
634   - S5PC110_GPIO_MP225,
635   - S5PC110_GPIO_MP226,
636   - S5PC110_GPIO_MP227,
637   - S5PC110_GPIO_MP230,
638   - S5PC110_GPIO_MP231,
639   - S5PC110_GPIO_MP232,
640   - S5PC110_GPIO_MP233,
641   - S5PC110_GPIO_MP234,
642   - S5PC110_GPIO_MP235,
643   - S5PC110_GPIO_MP236,
644   - S5PC110_GPIO_MP237,
645   - S5PC110_GPIO_MP240,
646   - S5PC110_GPIO_MP241,
647   - S5PC110_GPIO_MP242,
648   - S5PC110_GPIO_MP243,
649   - S5PC110_GPIO_MP244,
650   - S5PC110_GPIO_MP245,
651   - S5PC110_GPIO_MP246,
652   - S5PC110_GPIO_MP247,
653   - S5PC110_GPIO_MP250,
654   - S5PC110_GPIO_MP251,
655   - S5PC110_GPIO_MP252,
656   - S5PC110_GPIO_MP253,
657   - S5PC110_GPIO_MP254,
658   - S5PC110_GPIO_MP255,
659   - S5PC110_GPIO_MP256,
660   - S5PC110_GPIO_MP257,
661   - S5PC110_GPIO_MP260,
662   - S5PC110_GPIO_MP261,
663   - S5PC110_GPIO_MP262,
664   - S5PC110_GPIO_MP263,
665   - S5PC110_GPIO_MP264,
666   - S5PC110_GPIO_MP265,
667   - S5PC110_GPIO_MP266,
668   - S5PC110_GPIO_MP267,
669   - S5PC110_GPIO_MP270,
670   - S5PC110_GPIO_MP271,
671   - S5PC110_GPIO_MP272,
672   - S5PC110_GPIO_MP273,
673   - S5PC110_GPIO_MP274,
674   - S5PC110_GPIO_MP275,
675   - S5PC110_GPIO_MP276,
676   - S5PC110_GPIO_MP277,
677   - S5PC110_GPIO_MP280,
678   - S5PC110_GPIO_MP281,
679   - S5PC110_GPIO_MP282,
680   - S5PC110_GPIO_MP283,
681   - S5PC110_GPIO_MP284,
682   - S5PC110_GPIO_MP285,
683   - S5PC110_GPIO_MP286,
684   - S5PC110_GPIO_MP287,
685   - S5PC110_GPIO_H00,
686   - S5PC110_GPIO_H01,
687   - S5PC110_GPIO_H02,
688   - S5PC110_GPIO_H03,
689   - S5PC110_GPIO_H04,
690   - S5PC110_GPIO_H05,
691   - S5PC110_GPIO_H06,
692   - S5PC110_GPIO_H07,
693   - S5PC110_GPIO_H10,
694   - S5PC110_GPIO_H11,
695   - S5PC110_GPIO_H12,
696   - S5PC110_GPIO_H13,
697   - S5PC110_GPIO_H14,
698   - S5PC110_GPIO_H15,
699   - S5PC110_GPIO_H16,
700   - S5PC110_GPIO_H17,
701   - S5PC110_GPIO_H20,
702   - S5PC110_GPIO_H21,
703   - S5PC110_GPIO_H22,
704   - S5PC110_GPIO_H23,
705   - S5PC110_GPIO_H24,
706   - S5PC110_GPIO_H25,
707   - S5PC110_GPIO_H26,
708   - S5PC110_GPIO_H27,
709   - S5PC110_GPIO_H30,
710   - S5PC110_GPIO_H31,
711   - S5PC110_GPIO_H32,
712   - S5PC110_GPIO_H33,
713   - S5PC110_GPIO_H34,
714   - S5PC110_GPIO_H35,
715   - S5PC110_GPIO_H36,
716   - S5PC110_GPIO_H37,
717   -
718   - S5PC110_GPIO_MAX_PORT
719   -};
720   -
721   -struct gpio_info {
722   - unsigned int reg_addr; /* Address of register for this part */
723   - unsigned int max_gpio; /* Maximum GPIO in this part */
724   -};
725   -
726   -#define S5PC100_GPIO_NUM_PARTS 1
727   -static struct gpio_info s5pc100_gpio_data[S5PC100_GPIO_NUM_PARTS] = {
728   - { S5PC100_GPIO_BASE, S5PC100_GPIO_MAX_PORT },
729   -};
730   -
731   -#define S5PC110_GPIO_NUM_PARTS 1
732   -static struct gpio_info s5pc110_gpio_data[S5PC110_GPIO_NUM_PARTS] = {
733   - { S5PC110_GPIO_BASE, S5PC110_GPIO_MAX_PORT },
734   -};
735   -
736   -static inline struct gpio_info *get_gpio_data(void)
737   -{
738   - if (cpu_is_s5pc100())
739   - return s5pc100_gpio_data;
740   - else if (cpu_is_s5pc110())
741   - return s5pc110_gpio_data;
742   -
743   - return NULL;
744   -}
745   -
746   -static inline unsigned int get_bank_num(void)
747   -{
748   - if (cpu_is_s5pc100())
749   - return S5PC100_GPIO_NUM_PARTS;
750   - else if (cpu_is_s5pc110())
751   - return S5PC110_GPIO_NUM_PARTS;
752   -
753   - return 0;
754   -}
755   -
756   -/*
757   - * This structure helps mapping symbolic GPIO names into indices from
758   - * exynos5_gpio_pin/exynos5420_gpio_pin enums.
759   - *
760   - * By convention, symbolic GPIO name is defined as follows:
761   - *
762   - * g[p]<bank><set><bit>, where
763   - * p is optional
764   - * <bank> - a single character bank name, as defined by the SOC
765   - * <set> - a single digit set number
766   - * <bit> - bit number within the set (in 0..7 range).
767   - *
768   - * <set><bit> essentially form an octal number of the GPIO pin within the bank
769   - * space. On the 5420 architecture some banks' sets do not start not from zero
770   - * ('d' starts from 1 and 'j' starts from 4). To compensate for that and
771   - * maintain flat number space withoout holes, those banks use offsets to be
772   - * deducted from the pin number.
773   - */
774   -struct gpio_name_num_table {
775   - char bank; /* bank name symbol */
776   - u8 bank_size; /* total number of pins in the bank */
777   - char bank_offset; /* offset of the first bank's pin */
778   - unsigned int base; /* index of the first bank's pin in the enum */
779   -};
780   -
781   -#define GPIO_PER_BANK 8
782   -#define GPIO_ENTRY(name, base, top, offset) { name, top - base, offset, base }
783   -static const struct gpio_name_num_table s5pc100_gpio_table[] = {
784   - GPIO_ENTRY('a', S5PC100_GPIO_A00, S5PC100_GPIO_B0, 0),
785   - GPIO_ENTRY('b', S5PC100_GPIO_B0, S5PC100_GPIO_C0, 0),
786   - GPIO_ENTRY('c', S5PC100_GPIO_C0, S5PC100_GPIO_D0, 0),
787   - GPIO_ENTRY('d', S5PC100_GPIO_D0, S5PC100_GPIO_E00, 0),
788   - GPIO_ENTRY('e', S5PC100_GPIO_E00, S5PC100_GPIO_F00, 0),
789   - GPIO_ENTRY('f', S5PC100_GPIO_F00, S5PC100_GPIO_G00, 0),
790   - GPIO_ENTRY('g', S5PC100_GPIO_G00, S5PC100_GPIO_I0, 0),
791   - GPIO_ENTRY('i', S5PC100_GPIO_I0, S5PC100_GPIO_J00, 0),
792   - GPIO_ENTRY('j', S5PC100_GPIO_J00, S5PC100_GPIO_K00, 0),
793   - GPIO_ENTRY('k', S5PC100_GPIO_K00, S5PC100_GPIO_L00, 0),
794   - GPIO_ENTRY('l', S5PC100_GPIO_L00, S5PC100_GPIO_H00, 0),
795   - GPIO_ENTRY('h', S5PC100_GPIO_H00, S5PC100_GPIO_MAX_PORT, 0),
796   - { 0 }
797   -};
798   -
799   -static const struct gpio_name_num_table s5pc110_gpio_table[] = {
800   - GPIO_ENTRY('a', S5PC110_GPIO_A00, S5PC110_GPIO_B0, 0),
801   - GPIO_ENTRY('b', S5PC110_GPIO_B0, S5PC110_GPIO_C00, 0),
802   - GPIO_ENTRY('c', S5PC110_GPIO_C00, S5PC110_GPIO_D00, 0),
803   - GPIO_ENTRY('d', S5PC110_GPIO_D00, S5PC110_GPIO_E00, 0),
804   - GPIO_ENTRY('e', S5PC110_GPIO_E00, S5PC110_GPIO_F00, 0),
805   - GPIO_ENTRY('f', S5PC110_GPIO_F00, S5PC110_GPIO_G00, 0),
806   - GPIO_ENTRY('g', S5PC110_GPIO_G00, S5PC110_GPIO_I0, 0),
807   - GPIO_ENTRY('i', S5PC110_GPIO_I0, S5PC110_GPIO_J00, 0),
808   - GPIO_ENTRY('j', S5PC110_GPIO_J00, S5PC110_GPIO_MP010, 0),
809   - GPIO_ENTRY('h', S5PC110_GPIO_H00, S5PC110_GPIO_MAX_PORT, 0),
810   - { 0 }
811   -};
812   -
813   -/* functions */
814   -void gpio_cfg_pin(int gpio, int cfg);
815   -void gpio_set_pull(int gpio, int mode);
816   -void gpio_set_drv(int gpio, int mode);
817   -void gpio_set_rate(int gpio, int mode);
818   -int s5p_gpio_get_pin(unsigned gpio);
819   -
820   -/* GPIO pins per bank */
821   -#define GPIO_PER_BANK 8
822   -#endif
823   -
824   -/* Pin configurations */
825   -#define S5P_GPIO_INPUT 0x0
826   -#define S5P_GPIO_OUTPUT 0x1
827   -#define S5P_GPIO_IRQ 0xf
828   -#define S5P_GPIO_FUNC(x) (x)
829   -
830   -/* Pull mode */
831   -#define S5P_GPIO_PULL_NONE 0x0
832   -#define S5P_GPIO_PULL_DOWN 0x1
833   -#define S5P_GPIO_PULL_UP 0x2
834   -
835   -/* Drive Strength level */
836   -#define S5P_GPIO_DRV_1X 0x0
837   -#define S5P_GPIO_DRV_3X 0x1
838   -#define S5P_GPIO_DRV_2X 0x2
839   -#define S5P_GPIO_DRV_4X 0x3
840   -#define S5P_GPIO_DRV_FAST 0x0
841   -#define S5P_GPIO_DRV_SLOW 0x1
842   -
843   -#endif
arch/arm/include/asm/arch-s5pc1xx/mmc.h
View file @ 225f5ee
1   -/*
2   - * (C) Copyright 2009 SAMSUNG Electronics
3   - * Minkyu Kang <mk7.kang@samsung.com>
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#ifndef __ASM_ARCH_MMC_H_
9   -#define __ASM_ARCH_MMC_H_
10   -
11   -#define S5P_MMC_DEV_OFFSET 0x100000
12   -
13   -#define SDHCI_CONTROL2 0x80
14   -#define SDHCI_CONTROL3 0x84
15   -#define SDHCI_CONTROL4 0x8C
16   -
17   -#define SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31)
18   -#define SDHCI_CTRL2_ENCMDCNFMSK (1 << 30)
19   -#define SDHCI_CTRL2_CDINVRXD3 (1 << 29)
20   -#define SDHCI_CTRL2_SLCARDOUT (1 << 28)
21   -
22   -#define SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24)
23   -#define SDHCI_CTRL2_FLTCLKSEL_SHIFT (24)
24   -#define SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24)
25   -
26   -#define SDHCI_CTRL2_LVLDAT_MASK (0xff << 16)
27   -#define SDHCI_CTRL2_LVLDAT_SHIFT (16)
28   -#define SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16)
29   -
30   -#define SDHCI_CTRL2_ENFBCLKTX (1 << 15)
31   -#define SDHCI_CTRL2_ENFBCLKRX (1 << 14)
32   -#define SDHCI_CTRL2_SDCDSEL (1 << 13)
33   -#define SDHCI_CTRL2_SDSIGPC (1 << 12)
34   -#define SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11)
35   -
36   -#define SDHCI_CTRL2_DFCNT_MASK(_x) ((_x) << 9)
37   -#define SDHCI_CTRL2_DFCNT_SHIFT (9)
38   -
39   -#define SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8)
40   -#define SDHCI_CTRL2_RWAITMODE (1 << 7)
41   -#define SDHCI_CTRL2_DISBUFRD (1 << 6)
42   -#define SDHCI_CTRL2_SELBASECLK_MASK(_x) ((_x) << 4)
43   -#define SDHCI_CTRL2_SELBASECLK_SHIFT (4)
44   -#define SDHCI_CTRL2_PWRSYNC (1 << 3)
45   -#define SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1)
46   -#define SDHCI_CTRL2_HWINITFIN (1 << 0)
47   -
48   -#define SDHCI_CTRL3_FCSEL3 (1 << 31)
49   -#define SDHCI_CTRL3_FCSEL2 (1 << 23)
50   -#define SDHCI_CTRL3_FCSEL1 (1 << 15)
51   -#define SDHCI_CTRL3_FCSEL0 (1 << 7)
52   -
53   -#define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16)
54   -#define SDHCI_CTRL4_DRIVE_SHIFT (16)
55   -
56   -int s5p_sdhci_init(u32 regbase, int index, int bus_width);
57   -
58   -static inline int s5p_mmc_init(int index, int bus_width)
59   -{
60   - unsigned int base = samsung_get_base_mmc() +
61   - (S5P_MMC_DEV_OFFSET * index);
62   -
63   - return s5p_sdhci_init(base, index, bus_width);
64   -}
65   -#endif
arch/arm/include/asm/arch-s5pc1xx/periph.h
View file @ 225f5ee
1   -/*
2   - * Copyright (C) 2012 Samsung Electronics
3   - * Rajeshwari Shinde <rajeshwari.s@samsung.com>
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#ifndef __ASM_ARM_ARCH_PERIPH_H
9   -#define __ASM_ARM_ARCH_PERIPH_H
10   -
11   -/*
12   - * Peripherals required for pinmux configuration. List will
13   - * grow with support for more devices getting added.
14   - * Numbering based on interrupt table.
15   - *
16   - */
17   -enum periph_id {
18   - PERIPH_ID_UART0 = 51,
19   - PERIPH_ID_UART1,
20   - PERIPH_ID_UART2,
21   - PERIPH_ID_UART3,
22   - PERIPH_ID_I2C0 = 56,
23   - PERIPH_ID_I2C1,
24   - PERIPH_ID_I2C2,
25   - PERIPH_ID_I2C3,
26   - PERIPH_ID_I2C4,
27   - PERIPH_ID_I2C5,
28   - PERIPH_ID_I2C6,
29   - PERIPH_ID_I2C7,
30   - PERIPH_ID_SPI0 = 68,
31   - PERIPH_ID_SPI1,
32   - PERIPH_ID_SPI2,
33   - PERIPH_ID_SDMMC0 = 75,
34   - PERIPH_ID_SDMMC1,
35   - PERIPH_ID_SDMMC2,
36   - PERIPH_ID_SDMMC3,
37   - PERIPH_ID_I2C8 = 87,
38   - PERIPH_ID_I2C9,
39   - PERIPH_ID_I2S0 = 98,
40   - PERIPH_ID_I2S1 = 99,
41   -
42   - /* Since following peripherals do
43   - * not have shared peripheral interrupts (SPIs)
44   - * they are numbered arbitiraly after the maximum
45   - * SPIs Exynos has (128)
46   - */
47   - PERIPH_ID_SROMC = 128,
48   - PERIPH_ID_SPI3,
49   - PERIPH_ID_SPI4,
50   - PERIPH_ID_SDMMC4,
51   - PERIPH_ID_PWM0,
52   - PERIPH_ID_PWM1,
53   - PERIPH_ID_PWM2,
54   - PERIPH_ID_PWM3,
55   - PERIPH_ID_PWM4,
56   - PERIPH_ID_I2C10 = 203,
57   -
58   - PERIPH_ID_NONE = -1,
59   -};
60   -
61   -#endif /* __ASM_ARM_ARCH_PERIPH_H */
arch/arm/include/asm/arch-s5pc1xx/pinmux.h
View file @ 225f5ee
1   -/*
2   - * Copyright (C) 2012 Samsung Electronics
3   - * Abhilash Kesavan <a.kesavan@samsung.com>
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#ifndef __ASM_ARM_ARCH_PINMUX_H
9   -#define __ASM_ARM_ARCH_PINMUX_H
10   -
11   -#include "periph.h"
12   -
13   -/*
14   - * Flags for setting specific configarations of peripherals.
15   - * List will grow with support for more devices getting added.
16   - */
17   -enum {
18   - PINMUX_FLAG_NONE = 0x00000000,
19   -
20   - /* Flags for eMMC */
21   - PINMUX_FLAG_8BIT_MODE = 1 << 0, /* SDMMC 8-bit mode */
22   -
23   - /* Flags for SROM controller */
24   - PINMUX_FLAG_BANK = 3 << 0, /* bank number (0-3) */
25   - PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */
26   -};
27   -
28   -/**
29   - * Configures the pinmux for a particular peripheral.
30   - *
31   - * Each gpio can be configured in many different ways (4 bits on exynos)
32   - * such as "input", "output", "special function", "external interrupt"
33   - * etc. This function will configure the peripheral pinmux along with
34   - * pull-up/down and drive strength.
35   - *
36   - * @param peripheral peripheral to be configured
37   - * @param flags configure flags
38   - * @return 0 if ok, -1 on error (e.g. unsupported peripheral)
39   - */
40   -int exynos_pinmux_config(int peripheral, int flags);
41   -
42   -/**
43   - * Decode the peripheral id using the interrpt numbers.
44   - *
45   - * @param blob Device tree blob
46   - * @param node FDT I2C node to find
47   - * @return peripheral id if ok, PERIPH_ID_NONE on error
48   - */
49   -int pinmux_decode_periph_id(const void *blob, int node);
50   -#endif
arch/arm/include/asm/arch-s5pc1xx/power.h
View file @ 225f5ee
1   -/*
2   - * Copyright (c) 2009 Samsung Electronics
3   - * Kyungmin Park <kyungmin.park@samsung.com>
4   - * Minkyu Kang <mk7.kang@samsung.com>
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -#ifndef __ASM_ARM_ARCH_POWER_H_
10   -#define __ASM_ARM_ARCH_POWER_H_
11   -
12   -/*
13   - * Power control
14   - */
15   -#define S5PC100_OTHERS 0xE0108200
16   -#define S5PC100_RST_STAT 0xE0108300
17   -#define S5PC100_SLEEP_WAKEUP (1 << 3)
18   -#define S5PC100_WAKEUP_STAT 0xE0108304
19   -#define S5PC100_INFORM0 0xE0108400
20   -
21   -#define S5PC110_RST_STAT 0xE010A000
22   -#define S5PC110_SLEEP_WAKEUP (1 << 3)
23   -#define S5PC110_WAKEUP_STAT 0xE010C200
24   -#define S5PC110_OTHERS 0xE010E000
25   -#define S5PC110_USB_PHY_CON 0xE010E80C
26   -#define S5PC110_INFORM0 0xE010F000
27   -
28   -#endif
arch/arm/include/asm/arch-s5pc1xx/pwm.h
View file @ 225f5ee
1   -/*
2   - * Copyright (C) 2009 Samsung Electronics
3   - * Kyungmin Park <kyungmin.park@samsung.com>
4   - * Minkyu Kang <mk7.kang@samsung.com>
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -#ifndef __ASM_ARM_ARCH_PWM_H_
10   -#define __ASM_ARM_ARCH_PWM_H_
11   -
12   -#define PRESCALER_0 (8 - 1) /* prescaler of timer 0, 1 */
13   -#define PRESCALER_1 (16 - 1) /* prescaler of timer 2, 3, 4 */
14   -
15   -/* Divider MUX */
16   -#define MUX_DIV_1 0 /* 1/1 period */
17   -#define MUX_DIV_2 1 /* 1/2 period */
18   -#define MUX_DIV_4 2 /* 1/4 period */
19   -#define MUX_DIV_8 3 /* 1/8 period */
20   -#define MUX_DIV_16 4 /* 1/16 period */
21   -
22   -#define MUX_DIV_SHIFT(x) (x * 4)
23   -
24   -#define TCON_OFFSET(x) ((x + 1) * (!!x) << 2)
25   -
26   -#define TCON_START(x) (1 << TCON_OFFSET(x))
27   -#define TCON_UPDATE(x) (1 << (TCON_OFFSET(x) + 1))
28   -#define TCON_INVERTER(x) (1 << (TCON_OFFSET(x) + 2))
29   -#define TCON_AUTO_RELOAD(x) (1 << (TCON_OFFSET(x) + 3))
30   -#define TCON4_AUTO_RELOAD (1 << 22)
31   -
32   -#ifndef __ASSEMBLY__
33   -struct s5p_timer {
34   - unsigned int tcfg0;
35   - unsigned int tcfg1;
36   - unsigned int tcon;
37   - unsigned int tcntb0;
38   - unsigned int tcmpb0;
39   - unsigned int tcnto0;
40   - unsigned int tcntb1;
41   - unsigned int tcmpb1;
42   - unsigned int tcnto1;
43   - unsigned int tcntb2;
44   - unsigned int tcmpb2;
45   - unsigned int tcnto2;
46   - unsigned int tcntb3;
47   - unsigned int res1;
48   - unsigned int tcnto3;
49   - unsigned int tcntb4;
50   - unsigned int tcnto4;
51   - unsigned int tintcstat;
52   -};
53   -#endif /* __ASSEMBLY__ */
54   -
55   -#endif
arch/arm/include/asm/arch-s5pc1xx/sromc.h
View file @ 225f5ee
1   -/*
2   - * (C) Copyright 2010 Samsung Electronics
3   - * Naveen Krishna Ch <ch.naveen@samsung.com>
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - *
7   - * Note: This file contains the register description for Memory subsystem
8   - * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
9   - *
10   - * Only SROMC is defined as of now
11   - */
12   -
13   -#ifndef __ASM_ARCH_SROMC_H_
14   -#define __ASM_ARCH_SROMC_H_
15   -
16   -#define SMC_DATA16_WIDTH(x) (1<<((x*4)+0))
17   -#define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/
18   - /* 1-> Byte base address*/
19   -#define SMC_WAIT_ENABLE(x) (1<<((x*4)+2))
20   -#define SMC_BYTE_ENABLE(x) (1<<((x*4)+3))
21   -
22   -#define SMC_BC_TACS(x) (x << 28) /* 0clk address set-up */
23   -#define SMC_BC_TCOS(x) (x << 24) /* 4clk chip selection set-up */
24   -#define SMC_BC_TACC(x) (x << 16) /* 14clk access cycle */
25   -#define SMC_BC_TCOH(x) (x << 12) /* 1clk chip selection hold */
26   -#define SMC_BC_TAH(x) (x << 8) /* 4clk address holding time */
27   -#define SMC_BC_TACP(x) (x << 4) /* 6clk page mode access cycle */
28   -#define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
29   -
30   -#ifndef __ASSEMBLY__
31   -struct s5p_sromc {
32   - unsigned int bw;
33   - unsigned int bc[6];
34   -};
35   -#endif /* __ASSEMBLY__ */
36   -
37   -/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
38   -void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
39   -
40   -#endif /* __ASM_ARCH_SMC_H_ */
arch/arm/include/asm/arch-s5pc1xx/sys_proto.h
View file @ 225f5ee
1   -/*
2   - * Copyright (C) 2009 Samsung Electrnoics
3   - * Minkyu Kang <mk7.kang@samsung.com>
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#ifndef _SYS_PROTO_H_
9   -#define _SYS_PROTO_H_
10   -
11   -u32 get_device_type(void);
12   -
13   -#endif
arch/arm/include/asm/arch-s5pc1xx/uart.h
View file @ 225f5ee
1   -/*
2   - * (C) Copyright 2009 Samsung Electronics
3   - * Minkyu Kang <mk7.kang@samsung.com>
4   - * Heungjun Kim <riverful.kim@samsung.com>
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -#ifndef __ASM_ARCH_UART_H_
10   -#define __ASM_ARCH_UART_H_
11   -
12   -#ifndef __ASSEMBLY__
13   -/* baudrate rest value */
14   -union br_rest {
15   - unsigned short slot; /* udivslot */
16   - unsigned char value; /* ufracval */
17   -};
18   -
19   -struct s5p_uart {
20   - unsigned int ulcon;
21   - unsigned int ucon;
22   - unsigned int ufcon;
23   - unsigned int umcon;
24   - unsigned int utrstat;
25   - unsigned int uerstat;
26   - unsigned int ufstat;
27   - unsigned int umstat;
28   - unsigned char utxh;
29   - unsigned char res1[3];
30   - unsigned char urxh;
31   - unsigned char res2[3];
32   - unsigned int ubrdiv;
33   - union br_rest rest;
34   - unsigned char res3[0x3d0];
35   -};
36   -
37   -static inline int s5p_uart_divslot(void)
38   -{
39   - return 1;
40   -}
41   -
42   -#endif /* __ASSEMBLY__ */
43   -
44   -#endif
arch/arm/include/asm/arch-s5pc1xx/watchdog.h
View file @ 225f5ee
1   -/*
2   - * Copyright (C) 2011 Samsung Electronics
3   - * Heungjun Kim <riverful.kim@samsung.com>
4   - * Minkyu Kang <mk7.kang@samsung.com>
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -#ifndef __ASM_ARM_ARCH_WATCHDOG_H_
10   -#define __ASM_ARM_ARCH_WATCHDOG_H_
11   -
12   -#define WTCON_RESET_OFFSET 0
13   -#define WTCON_INTEN_OFFSET 2
14   -#define WTCON_CLKSEL_OFFSET 3
15   -#define WTCON_EN_OFFSET 5
16   -#define WTCON_PRE_OFFSET 8
17   -
18   -#define WTCON_CLK_16 0x0
19   -#define WTCON_CLK_32 0x1
20   -#define WTCON_CLK_64 0x2
21   -#define WTCON_CLK_128 0x3
22   -
23   -#define WTCON_CLK(x) ((x & 0x3) << WTCON_CLKSEL_OFFSET)
24   -#define WTCON_PRESCALER(x) ((x) << WTCON_PRE_OFFSET)
25   -#define WTCON_EN (0x1 << WTCON_EN_OFFSET)
26   -#define WTCON_RESET (0x1 << WTCON_RESET_OFFSET)
27   -#define WTCON_INT (0x1 << WTCON_INTEN_OFFSET)
28   -
29   -#ifndef __ASSEMBLY__
30   -struct s5p_watchdog {
31   - unsigned int wtcon;
32   - unsigned int wtdat;
33   - unsigned int wtcnt;
34   - unsigned int wtclrint;
35   -};
36   -
37   -/* functions */
38   -void wdt_stop(void);
39   -void wdt_start(unsigned int timeout);
40   -#endif /* __ASSEMBLY__ */
41   -
42   -#endif
arch/arm/mach-s5pc1xx/Kconfig
Diff comments   View file @ 225f5ee
  1 +if ARCH_S5PC1XX
  2 +
  3 +choice
  4 + prompt "S5PC1XX board select"
  5 + optional
  6 +
  7 +config TARGET_S5P_GONI
  8 + bool "S5P Goni board"
  9 + select OF_CONTROL
  10 +
  11 +config TARGET_SMDKC100
  12 + bool "Support smdkc100 board"
  13 + select OF_CONTROL
  14 +
  15 +endchoice
  16 +
  17 +config SYS_SOC
  18 + default "s5pc1xx"
  19 +
  20 +source "board/samsung/goni/Kconfig"
  21 +source "board/samsung/smdkc100/Kconfig"
  22 +
  23 +endif
arch/arm/mach-s5pc1xx/Makefile
Diff comments   View file @ 225f5ee
  1 +#
  2 +# (C) Copyright 2000-2003
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# (C) Copyright 2008
  6 +# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
  7 +#
  8 +# SPDX-License-Identifier: GPL-2.0+
  9 +#
  10 +
  11 +obj-y = cache.o
  12 +obj-y += reset.o
  13 +
  14 +obj-y += clock.o
arch/arm/mach-s5pc1xx/cache.c
Diff comments   View file @ 225f5ee
  1 +/*
  2 + * Copyright (C) 2014 Samsung Electronics
  3 + * Minkyu Kang <mk7.kang@samsung.com>
  4 + * Robert Baldyga <r.baldyga@samsung.com>
  5 + *
  6 + * based on arch/arm/cpu/armv7/omap3/cache.S
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +#include <common.h>
  12 +
  13 +#ifndef CONFIG_SYS_DCACHE_OFF
  14 +void enable_caches(void)
  15 +{
  16 + dcache_enable();
  17 +}
  18 +
  19 +void disable_caches(void)
  20 +{
  21 + dcache_disable();
  22 +}
  23 +#endif
  24 +
  25 +#ifndef CONFIG_SYS_L2CACHE_OFF
  26 +void v7_outer_cache_enable(void)
  27 +{
  28 + __asm(
  29 + "push {r0, r1, r2, lr}\n\t"
  30 + "mrc 15, 0, r3, cr1, cr0, 1\n\t"
  31 + "orr r3, r3, #2\n\t"
  32 + "mcr 15, 0, r3, cr1, cr0, 1\n\t"
  33 + "pop {r1, r2, r3, pc}"
  34 + );
  35 +}
  36 +
  37 +void v7_outer_cache_disable(void)
  38 +{
  39 + __asm(
  40 + "push {r0, r1, r2, lr}\n\t"
  41 + "mrc 15, 0, r3, cr1, cr0, 1\n\t"
  42 + "bic r3, r3, #2\n\t"
  43 + "mcr 15, 0, r3, cr1, cr0, 1\n\t"
  44 + "pop {r1, r2, r3, pc}"
  45 + );
  46 +}
  47 +#endif
arch/arm/mach-s5pc1xx/clock.c
Diff comments   View file @ 225f5ee
  1 +/*
  2 + * Copyright (C) 2009 Samsung Electronics
  3 + * Minkyu Kang <mk7.kang@samsung.com>
  4 + * Heungjun Kim <riverful.kim@samsung.com>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <asm/io.h>
  11 +#include <asm/arch/clock.h>
  12 +#include <asm/arch/clk.h>
  13 +
  14 +#define CLK_M 0
  15 +#define CLK_D 1
  16 +#define CLK_P 2
  17 +
  18 +#ifndef CONFIG_SYS_CLK_FREQ_C100
  19 +#define CONFIG_SYS_CLK_FREQ_C100 12000000
  20 +#endif
  21 +#ifndef CONFIG_SYS_CLK_FREQ_C110
  22 +#define CONFIG_SYS_CLK_FREQ_C110 24000000
  23 +#endif
  24 +
  25 +/* s5pc110: return pll clock frequency */
  26 +static unsigned long s5pc100_get_pll_clk(int pllreg)
  27 +{
  28 + struct s5pc100_clock *clk =
  29 + (struct s5pc100_clock *)samsung_get_base_clock();
  30 + unsigned long r, m, p, s, mask, fout;
  31 + unsigned int freq;
  32 +
  33 + switch (pllreg) {
  34 + case APLL:
  35 + r = readl(&clk->apll_con);
  36 + break;
  37 + case MPLL:
  38 + r = readl(&clk->mpll_con);
  39 + break;
  40 + case EPLL:
  41 + r = readl(&clk->epll_con);
  42 + break;
  43 + case HPLL:
  44 + r = readl(&clk->hpll_con);
  45 + break;
  46 + default:
  47 + printf("Unsupported PLL (%d)\n", pllreg);
  48 + return 0;
  49 + }
  50 +
  51 + /*
  52 + * APLL_CON: MIDV [25:16]
  53 + * MPLL_CON: MIDV [23:16]
  54 + * EPLL_CON: MIDV [23:16]
  55 + * HPLL_CON: MIDV [23:16]
  56 + */
  57 + if (pllreg == APLL)
  58 + mask = 0x3ff;
  59 + else
  60 + mask = 0x0ff;
  61 +
  62 + m = (r >> 16) & mask;
  63 +
  64 + /* PDIV [13:8] */
  65 + p = (r >> 8) & 0x3f;
  66 + /* SDIV [2:0] */
  67 + s = r & 0x7;
  68 +
  69 + /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
  70 + freq = CONFIG_SYS_CLK_FREQ_C100;
  71 + fout = m * (freq / (p * (1 << s)));
  72 +
  73 + return fout;
  74 +}
  75 +
  76 +/* s5pc100: return pll clock frequency */
  77 +static unsigned long s5pc110_get_pll_clk(int pllreg)
  78 +{
  79 + struct s5pc110_clock *clk =
  80 + (struct s5pc110_clock *)samsung_get_base_clock();
  81 + unsigned long r, m, p, s, mask, fout;
  82 + unsigned int freq;
  83 +
  84 + switch (pllreg) {
  85 + case APLL:
  86 + r = readl(&clk->apll_con);
  87 + break;
  88 + case MPLL:
  89 + r = readl(&clk->mpll_con);
  90 + break;
  91 + case EPLL:
  92 + r = readl(&clk->epll_con);
  93 + break;
  94 + case VPLL:
  95 + r = readl(&clk->vpll_con);
  96 + break;
  97 + default:
  98 + printf("Unsupported PLL (%d)\n", pllreg);
  99 + return 0;
  100 + }
  101 +
  102 + /*
  103 + * APLL_CON: MIDV [25:16]
  104 + * MPLL_CON: MIDV [25:16]
  105 + * EPLL_CON: MIDV [24:16]
  106 + * VPLL_CON: MIDV [24:16]
  107 + */
  108 + if (pllreg == APLL || pllreg == MPLL)
  109 + mask = 0x3ff;
  110 + else
  111 + mask = 0x1ff;
  112 +
  113 + m = (r >> 16) & mask;
  114 +
  115 + /* PDIV [13:8] */
  116 + p = (r >> 8) & 0x3f;
  117 + /* SDIV [2:0] */
  118 + s = r & 0x7;
  119 +
  120 + freq = CONFIG_SYS_CLK_FREQ_C110;
  121 + if (pllreg == APLL) {
  122 + if (s < 1)
  123 + s = 1;
  124 + /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
  125 + fout = m * (freq / (p * (1 << (s - 1))));
  126 + } else
  127 + /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
  128 + fout = m * (freq / (p * (1 << s)));
  129 +
  130 + return fout;
  131 +}
  132 +
  133 +/* s5pc110: return ARM clock frequency */
  134 +static unsigned long s5pc110_get_arm_clk(void)
  135 +{
  136 + struct s5pc110_clock *clk =
  137 + (struct s5pc110_clock *)samsung_get_base_clock();
  138 + unsigned long div;
  139 + unsigned long dout_apll, armclk;
  140 + unsigned int apll_ratio;
  141 +
  142 + div = readl(&clk->div0);
  143 +
  144 + /* APLL_RATIO: [2:0] */
  145 + apll_ratio = div & 0x7;
  146 +
  147 + dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
  148 + armclk = dout_apll;
  149 +
  150 + return armclk;
  151 +}
  152 +
  153 +/* s5pc100: return ARM clock frequency */
  154 +static unsigned long s5pc100_get_arm_clk(void)
  155 +{
  156 + struct s5pc100_clock *clk =
  157 + (struct s5pc100_clock *)samsung_get_base_clock();
  158 + unsigned long div;
  159 + unsigned long dout_apll, armclk;
  160 + unsigned int apll_ratio, arm_ratio;
  161 +
  162 + div = readl(&clk->div0);
  163 +
  164 + /* ARM_RATIO: [6:4] */
  165 + arm_ratio = (div >> 4) & 0x7;
  166 + /* APLL_RATIO: [0] */
  167 + apll_ratio = div & 0x1;
  168 +
  169 + dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
  170 + armclk = dout_apll / (arm_ratio + 1);
  171 +
  172 + return armclk;
  173 +}
  174 +
  175 +/* s5pc100: return HCLKD0 frequency */
  176 +static unsigned long get_hclk(void)
  177 +{
  178 + struct s5pc100_clock *clk =
  179 + (struct s5pc100_clock *)samsung_get_base_clock();
  180 + unsigned long hclkd0;
  181 + uint div, d0_bus_ratio;
  182 +
  183 + div = readl(&clk->div0);
  184 + /* D0_BUS_RATIO: [10:8] */
  185 + d0_bus_ratio = (div >> 8) & 0x7;
  186 +
  187 + hclkd0 = get_arm_clk() / (d0_bus_ratio + 1);
  188 +
  189 + return hclkd0;
  190 +}
  191 +
  192 +/* s5pc100: return PCLKD1 frequency */
  193 +static unsigned long get_pclkd1(void)
  194 +{
  195 + struct s5pc100_clock *clk =
  196 + (struct s5pc100_clock *)samsung_get_base_clock();
  197 + unsigned long d1_bus, pclkd1;
  198 + uint div, d1_bus_ratio, pclkd1_ratio;
  199 +
  200 + div = readl(&clk->div0);
  201 + /* D1_BUS_RATIO: [14:12] */
  202 + d1_bus_ratio = (div >> 12) & 0x7;
  203 + /* PCLKD1_RATIO: [18:16] */
  204 + pclkd1_ratio = (div >> 16) & 0x7;
  205 +
  206 + /* ASYNC Mode */
  207 + d1_bus = get_pll_clk(MPLL) / (d1_bus_ratio + 1);
  208 + pclkd1 = d1_bus / (pclkd1_ratio + 1);
  209 +
  210 + return pclkd1;
  211 +}
  212 +
  213 +/* s5pc110: return HCLKs frequency */
  214 +static unsigned long get_hclk_sys(int dom)
  215 +{
  216 + struct s5pc110_clock *clk =
  217 + (struct s5pc110_clock *)samsung_get_base_clock();
  218 + unsigned long hclk;
  219 + unsigned int div;
  220 + unsigned int offset;
  221 + unsigned int hclk_sys_ratio;
  222 +
  223 + if (dom == CLK_M)
  224 + return get_hclk();
  225 +
  226 + div = readl(&clk->div0);
  227 +
  228 + /*
  229 + * HCLK_MSYS_RATIO: [10:8]
  230 + * HCLK_DSYS_RATIO: [19:16]
  231 + * HCLK_PSYS_RATIO: [27:24]
  232 + */
  233 + offset = 8 + (dom << 0x3);
  234 +
  235 + hclk_sys_ratio = (div >> offset) & 0xf;
  236 +
  237 + hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1);
  238 +
  239 + return hclk;
  240 +}
  241 +
  242 +/* s5pc110: return PCLKs frequency */
  243 +static unsigned long get_pclk_sys(int dom)
  244 +{
  245 + struct s5pc110_clock *clk =
  246 + (struct s5pc110_clock *)samsung_get_base_clock();
  247 + unsigned long pclk;
  248 + unsigned int div;
  249 + unsigned int offset;
  250 + unsigned int pclk_sys_ratio;
  251 +
  252 + div = readl(&clk->div0);
  253 +
  254 + /*
  255 + * PCLK_MSYS_RATIO: [14:12]
  256 + * PCLK_DSYS_RATIO: [22:20]
  257 + * PCLK_PSYS_RATIO: [30:28]
  258 + */
  259 + offset = 12 + (dom << 0x3);
  260 +
  261 + pclk_sys_ratio = (div >> offset) & 0x7;
  262 +
  263 + pclk = get_hclk_sys(dom) / (pclk_sys_ratio + 1);
  264 +
  265 + return pclk;
  266 +}
  267 +
  268 +/* s5pc110: return peripheral clock frequency */
  269 +static unsigned long s5pc110_get_pclk(void)
  270 +{
  271 + return get_pclk_sys(CLK_P);
  272 +}
  273 +
  274 +/* s5pc100: return peripheral clock frequency */
  275 +static unsigned long s5pc100_get_pclk(void)
  276 +{
  277 + return get_pclkd1();
  278 +}
  279 +
  280 +/* s5pc1xx: return uart clock frequency */
  281 +static unsigned long s5pc1xx_get_uart_clk(int dev_index)
  282 +{
  283 + if (cpu_is_s5pc110())
  284 + return s5pc110_get_pclk();
  285 + else
  286 + return s5pc100_get_pclk();
  287 +}
  288 +
  289 +/* s5pc1xx: return pwm clock frequency */
  290 +static unsigned long s5pc1xx_get_pwm_clk(void)
  291 +{
  292 + if (cpu_is_s5pc110())
  293 + return s5pc110_get_pclk();
  294 + else
  295 + return s5pc100_get_pclk();
  296 +}
  297 +
  298 +unsigned long get_pll_clk(int pllreg)
  299 +{
  300 + if (cpu_is_s5pc110())
  301 + return s5pc110_get_pll_clk(pllreg);
  302 + else
  303 + return s5pc100_get_pll_clk(pllreg);
  304 +}
  305 +
  306 +unsigned long get_arm_clk(void)
  307 +{
  308 + if (cpu_is_s5pc110())
  309 + return s5pc110_get_arm_clk();
  310 + else
  311 + return s5pc100_get_arm_clk();
  312 +}
  313 +
  314 +unsigned long get_pwm_clk(void)
  315 +{
  316 + return s5pc1xx_get_pwm_clk();
  317 +}
  318 +
  319 +unsigned long get_uart_clk(int dev_index)
  320 +{
  321 + return s5pc1xx_get_uart_clk(dev_index);
  322 +}
  323 +
  324 +void set_mmc_clk(int dev_index, unsigned int div)
  325 +{
  326 + /* Do NOTHING */
  327 +}
arch/arm/mach-s5pc1xx/include/mach/clk.h
Diff comments   View file @ 225f5ee
  1 +/*
  2 + * (C) Copyright 2009 Samsung Electronics
  3 + * Minkyu Kang <mk7.kang@samsung.com>
  4 + * Heungjun Kim <riverful.kim@samsung.com>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef __ASM_ARM_ARCH_CLK_H_
  10 +#define __ASM_ARM_ARCH_CLK_H_
  11 +
  12 +#define APLL 0
  13 +#define MPLL 1
  14 +#define EPLL 2
  15 +#define HPLL 3
  16 +#define VPLL 4
  17 +
  18 +unsigned long get_pll_clk(int pllreg);
  19 +unsigned long get_arm_clk(void);
  20 +unsigned long get_pwm_clk(void);
  21 +unsigned long get_uart_clk(int dev_index);
  22 +void set_mmc_clk(int dev_index, unsigned int div);
  23 +
  24 +#endif
arch/arm/mach-s5pc1xx/include/mach/clock.h
Diff comments   View file @ 225f5ee
  1 +/*
  2 + * (C) Copyright 2009 Samsung Electronics
  3 + * Minkyu Kang <mk7.kang@samsung.com>
  4 + * Heungjun Kim <riverful.kim@samsung.com>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef __ASM_ARM_ARCH_CLOCK_H_
  10 +#define __ASM_ARM_ARCH_CLOCK_H_
  11 +
  12 +#ifndef __ASSEMBLY__
  13 +struct s5pc100_clock {
  14 + unsigned int apll_lock;
  15 + unsigned int mpll_lock;
  16 + unsigned int epll_lock;
  17 + unsigned int hpll_lock;
  18 + unsigned char res1[0xf0];
  19 + unsigned int apll_con;
  20 + unsigned int mpll_con;
  21 + unsigned int epll_con;
  22 + unsigned int hpll_con;
  23 + unsigned char res2[0xf0];
  24 + unsigned int src0;
  25 + unsigned int src1;
  26 + unsigned int src2;
  27 + unsigned int src3;
  28 + unsigned char res3[0xf0];
  29 + unsigned int div0;
  30 + unsigned int div1;
  31 + unsigned int div2;
  32 + unsigned int div3;
  33 + unsigned int div4;
  34 + unsigned char res4[0x1ec];
  35 + unsigned int gate_d00;
  36 + unsigned int gate_d01;
  37 + unsigned int gate_d02;
  38 + unsigned char res5[0x54];
  39 + unsigned int gate_sclk0;
  40 + unsigned int gate_sclk1;
  41 +};
  42 +
  43 +struct s5pc110_clock {
  44 + unsigned int apll_lock;
  45 + unsigned char res1[0x4];
  46 + unsigned int mpll_lock;
  47 + unsigned char res2[0x4];
  48 + unsigned int epll_lock;
  49 + unsigned char res3[0xc];
  50 + unsigned int vpll_lock;
  51 + unsigned char res4[0xdc];
  52 + unsigned int apll_con;
  53 + unsigned char res5[0x4];
  54 + unsigned int mpll_con;
  55 + unsigned char res6[0x4];
  56 + unsigned int epll_con;
  57 + unsigned char res7[0xc];
  58 + unsigned int vpll_con;
  59 + unsigned char res8[0xdc];
  60 + unsigned int src0;
  61 + unsigned int src1;
  62 + unsigned int src2;
  63 + unsigned int src3;
  64 + unsigned char res9[0xf0];
  65 + unsigned int div0;
  66 + unsigned int div1;
  67 + unsigned int div2;
  68 + unsigned int div3;
  69 + unsigned int div4;
  70 + unsigned char res10[0x1ec];
  71 + unsigned int gate_d00;
  72 + unsigned int gate_d01;
  73 + unsigned int gate_d02;
  74 + unsigned char res11[0x54];
  75 + unsigned int gate_sclk0;
  76 + unsigned int gate_sclk1;
  77 +};
  78 +#endif
  79 +
  80 +#endif
arch/arm/mach-s5pc1xx/include/mach/cpu.h
Diff comments   View file @ 225f5ee
  1 +/*
  2 + * (C) Copyright 2009 Samsung Electronics
  3 + * Minkyu Kang <mk7.kang@samsung.com>
  4 + * Heungjun Kim <riverful.kim@samsung.com>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef _S5PC1XX_CPU_H
  10 +#define _S5PC1XX_CPU_H
  11 +
  12 +#define S5P_CPU_NAME "S5P"
  13 +#define S5PC1XX_ADDR_BASE 0xE0000000
  14 +
  15 +/* S5PC100 */
  16 +#define S5PC100_PRO_ID 0xE0000000
  17 +#define S5PC100_CLOCK_BASE 0xE0100000
  18 +#define S5PC100_GPIO_BASE 0xE0300000
  19 +#define S5PC100_VIC0_BASE 0xE4000000
  20 +#define S5PC100_VIC1_BASE 0xE4100000
  21 +#define S5PC100_VIC2_BASE 0xE4200000
  22 +#define S5PC100_DMC_BASE 0xE6000000
  23 +#define S5PC100_SROMC_BASE 0xE7000000
  24 +#define S5PC100_ONENAND_BASE 0xE7100000
  25 +#define S5PC100_PWMTIMER_BASE 0xEA000000
  26 +#define S5PC100_WATCHDOG_BASE 0xEA200000
  27 +#define S5PC100_UART_BASE 0xEC000000
  28 +#define S5PC100_MMC_BASE 0xED800000
  29 +
  30 +/* S5PC110 */
  31 +#define S5PC110_PRO_ID 0xE0000000
  32 +#define S5PC110_CLOCK_BASE 0xE0100000
  33 +#define S5PC110_GPIO_BASE 0xE0200000
  34 +#define S5PC110_PWMTIMER_BASE 0xE2500000
  35 +#define S5PC110_WATCHDOG_BASE 0xE2700000
  36 +#define S5PC110_UART_BASE 0xE2900000
  37 +#define S5PC110_SROMC_BASE 0xE8000000
  38 +#define S5PC110_MMC_BASE 0xEB000000
  39 +#define S5PC110_DMC0_BASE 0xF0000000
  40 +#define S5PC110_DMC1_BASE 0xF1400000
  41 +#define S5PC110_VIC0_BASE 0xF2000000
  42 +#define S5PC110_VIC1_BASE 0xF2100000
  43 +#define S5PC110_VIC2_BASE 0xF2200000
  44 +#define S5PC110_VIC3_BASE 0xF2300000
  45 +#define S5PC110_OTG_BASE 0xEC000000
  46 +#define S5PC110_PHY_BASE 0xEC100000
  47 +#define S5PC110_USB_PHY_CONTROL 0xE010E80C
  48 +
  49 +
  50 +#ifndef __ASSEMBLY__
  51 +#include <asm/io.h>
  52 +/* CPU detection macros */
  53 +extern unsigned int s5p_cpu_id;
  54 +extern unsigned int s5p_cpu_rev;
  55 +
  56 +static inline int s5p_get_cpu_rev(void)
  57 +{
  58 + return s5p_cpu_rev;
  59 +}
  60 +
  61 +static inline void s5p_set_cpu_id(void)
  62 +{
  63 + s5p_cpu_id = readl(S5PC100_PRO_ID);
  64 + s5p_cpu_rev = s5p_cpu_id & 0x000000FF;
  65 + s5p_cpu_id = 0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12);
  66 +}
  67 +
  68 +static inline char *s5p_get_cpu_name(void)
  69 +{
  70 + return S5P_CPU_NAME;
  71 +}
  72 +
  73 +#define IS_SAMSUNG_TYPE(type, id) \
  74 +static inline int cpu_is_##type(void) \
  75 +{ \
  76 + return s5p_cpu_id == id ? 1 : 0; \
  77 +}
  78 +
  79 +IS_SAMSUNG_TYPE(s5pc100, 0xc100)
  80 +IS_SAMSUNG_TYPE(s5pc110, 0xc110)
  81 +
  82 +#define SAMSUNG_BASE(device, base) \
  83 +static inline unsigned int samsung_get_base_##device(void) \
  84 +{ \
  85 + if (cpu_is_s5pc100()) \
  86 + return S5PC100_##base; \
  87 + else if (cpu_is_s5pc110()) \
  88 + return S5PC110_##base; \
  89 + else \
  90 + return 0; \
  91 +}
  92 +
  93 +SAMSUNG_BASE(clock, CLOCK_BASE)
  94 +SAMSUNG_BASE(gpio, GPIO_BASE)
  95 +SAMSUNG_BASE(pro_id, PRO_ID)
  96 +SAMSUNG_BASE(mmc, MMC_BASE)
  97 +SAMSUNG_BASE(sromc, SROMC_BASE)
  98 +SAMSUNG_BASE(timer, PWMTIMER_BASE)
  99 +SAMSUNG_BASE(uart, UART_BASE)
  100 +SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
  101 +#endif
  102 +
  103 +#endif /* _S5PC1XX_CPU_H */
arch/arm/mach-s5pc1xx/include/mach/gpio.h
Diff comments   View file @ 225f5ee
  1 +/*
  2 + * (C) Copyright 2009 Samsung Electronics
  3 + * Minkyu Kang <mk7.kang@samsung.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef __ASM_ARCH_GPIO_H
  9 +#define __ASM_ARCH_GPIO_H
  10 +
  11 +#ifndef __ASSEMBLY__
  12 +struct s5p_gpio_bank {
  13 + unsigned int con;
  14 + unsigned int dat;
  15 + unsigned int pull;
  16 + unsigned int drv;
  17 + unsigned int pdn_con;
  18 + unsigned int pdn_pull;
  19 + unsigned char res1[8];
  20 +};
  21 +
  22 +/* A list of valid GPIO numbers for the asm-generic/gpio.h interface */
  23 +enum s5pc100_gpio_pin {
  24 + S5PC100_GPIO_A00,
  25 + S5PC100_GPIO_A01,
  26 + S5PC100_GPIO_A02,
  27 + S5PC100_GPIO_A03,
  28 + S5PC100_GPIO_A04,
  29 + S5PC100_GPIO_A05,
  30 + S5PC100_GPIO_A06,
  31 + S5PC100_GPIO_A07,
  32 + S5PC100_GPIO_A10,
  33 + S5PC100_GPIO_A11,
  34 + S5PC100_GPIO_A12,
  35 + S5PC100_GPIO_A13,
  36 + S5PC100_GPIO_A14,
  37 + S5PC100_GPIO_A15,
  38 + S5PC100_GPIO_A16,
  39 + S5PC100_GPIO_A17,
  40 + S5PC100_GPIO_B0,
  41 + S5PC100_GPIO_B1,
  42 + S5PC100_GPIO_B2,
  43 + S5PC100_GPIO_B3,
  44 + S5PC100_GPIO_B4,
  45 + S5PC100_GPIO_B5,
  46 + S5PC100_GPIO_B6,
  47 + S5PC100_GPIO_B7,
  48 + S5PC100_GPIO_C0,
  49 + S5PC100_GPIO_C1,
  50 + S5PC100_GPIO_C2,
  51 + S5PC100_GPIO_C3,
  52 + S5PC100_GPIO_C4,
  53 + S5PC100_GPIO_C5,
  54 + S5PC100_GPIO_C6,
  55 + S5PC100_GPIO_C7,
  56 + S5PC100_GPIO_D0,
  57 + S5PC100_GPIO_D1,
  58 + S5PC100_GPIO_D2,
  59 + S5PC100_GPIO_D3,
  60 + S5PC100_GPIO_D4,
  61 + S5PC100_GPIO_D5,
  62 + S5PC100_GPIO_D6,
  63 + S5PC100_GPIO_D7,
  64 + S5PC100_GPIO_E00,
  65 + S5PC100_GPIO_E01,
  66 + S5PC100_GPIO_E02,
  67 + S5PC100_GPIO_E03,
  68 + S5PC100_GPIO_E04,
  69 + S5PC100_GPIO_E05,
  70 + S5PC100_GPIO_E06,
  71 + S5PC100_GPIO_E07,
  72 + S5PC100_GPIO_E10,
  73 + S5PC100_GPIO_E11,
  74 + S5PC100_GPIO_E12,
  75 + S5PC100_GPIO_E13,
  76 + S5PC100_GPIO_E14,
  77 + S5PC100_GPIO_E15,
  78 + S5PC100_GPIO_E16,
  79 + S5PC100_GPIO_E17,
  80 + S5PC100_GPIO_F00,
  81 + S5PC100_GPIO_F01,
  82 + S5PC100_GPIO_F02,
  83 + S5PC100_GPIO_F03,
  84 + S5PC100_GPIO_F04,
  85 + S5PC100_GPIO_F05,
  86 + S5PC100_GPIO_F06,
  87 + S5PC100_GPIO_F07,
  88 + S5PC100_GPIO_F10,
  89 + S5PC100_GPIO_F11,
  90 + S5PC100_GPIO_F12,
  91 + S5PC100_GPIO_F13,
  92 + S5PC100_GPIO_F14,
  93 + S5PC100_GPIO_F15,
  94 + S5PC100_GPIO_F16,
  95 + S5PC100_GPIO_F17,
  96 + S5PC100_GPIO_F20,
  97 + S5PC100_GPIO_F21,
  98 + S5PC100_GPIO_F22,
  99 + S5PC100_GPIO_F23,
  100 + S5PC100_GPIO_F24,
  101 + S5PC100_GPIO_F25,
  102 + S5PC100_GPIO_F26,
  103 + S5PC100_GPIO_F27,
  104 + S5PC100_GPIO_F30,
  105 + S5PC100_GPIO_F31,
  106 + S5PC100_GPIO_F32,
  107 + S5PC100_GPIO_F33,
  108 + S5PC100_GPIO_F34,
  109 + S5PC100_GPIO_F35,
  110 + S5PC100_GPIO_F36,
  111 + S5PC100_GPIO_F37,
  112 + S5PC100_GPIO_G00,
  113 + S5PC100_GPIO_G01,
  114 + S5PC100_GPIO_G02,
  115 + S5PC100_GPIO_G03,
  116 + S5PC100_GPIO_G04,
  117 + S5PC100_GPIO_G05,
  118 + S5PC100_GPIO_G06,
  119 + S5PC100_GPIO_G07,
  120 + S5PC100_GPIO_G10,
  121 + S5PC100_GPIO_G11,
  122 + S5PC100_GPIO_G12,
  123 + S5PC100_GPIO_G13,
  124 + S5PC100_GPIO_G14,
  125 + S5PC100_GPIO_G15,
  126 + S5PC100_GPIO_G16,
  127 + S5PC100_GPIO_G17,
  128 + S5PC100_GPIO_G20,
  129 + S5PC100_GPIO_G21,
  130 + S5PC100_GPIO_G22,
  131 + S5PC100_GPIO_G23,
  132 + S5PC100_GPIO_G24,
  133 + S5PC100_GPIO_G25,
  134 + S5PC100_GPIO_G26,
  135 + S5PC100_GPIO_G27,
  136 + S5PC100_GPIO_G30,
  137 + S5PC100_GPIO_G31,
  138 + S5PC100_GPIO_G32,
  139 + S5PC100_GPIO_G33,
  140 + S5PC100_GPIO_G34,
  141 + S5PC100_GPIO_G35,
  142 + S5PC100_GPIO_G36,
  143 + S5PC100_GPIO_G37,
  144 + S5PC100_GPIO_I0,
  145 + S5PC100_GPIO_I1,
  146 + S5PC100_GPIO_I2,
  147 + S5PC100_GPIO_I3,
  148 + S5PC100_GPIO_I4,
  149 + S5PC100_GPIO_I5,
  150 + S5PC100_GPIO_I6,
  151 + S5PC100_GPIO_I7,
  152 + S5PC100_GPIO_J00,
  153 + S5PC100_GPIO_J01,
  154 + S5PC100_GPIO_J02,
  155 + S5PC100_GPIO_J03,
  156 + S5PC100_GPIO_J04,
  157 + S5PC100_GPIO_J05,
  158 + S5PC100_GPIO_J06,
  159 + S5PC100_GPIO_J07,
  160 + S5PC100_GPIO_J10,
  161 + S5PC100_GPIO_J11,
  162 + S5PC100_GPIO_J12,
  163 + S5PC100_GPIO_J13,
  164 + S5PC100_GPIO_J14,
  165 + S5PC100_GPIO_J15,
  166 + S5PC100_GPIO_J16,
  167 + S5PC100_GPIO_J17,
  168 + S5PC100_GPIO_J20,
  169 + S5PC100_GPIO_J21,
  170 + S5PC100_GPIO_J22,
  171 + S5PC100_GPIO_J23,
  172 + S5PC100_GPIO_J24,
  173 + S5PC100_GPIO_J25,
  174 + S5PC100_GPIO_J26,
  175 + S5PC100_GPIO_J27,
  176 + S5PC100_GPIO_J30,
  177 + S5PC100_GPIO_J31,
  178 + S5PC100_GPIO_J32,
  179 + S5PC100_GPIO_J33,
  180 + S5PC100_GPIO_J34,
  181 + S5PC100_GPIO_J35,
  182 + S5PC100_GPIO_J36,
  183 + S5PC100_GPIO_J37,
  184 + S5PC100_GPIO_J40,
  185 + S5PC100_GPIO_J41,
  186 + S5PC100_GPIO_J42,
  187 + S5PC100_GPIO_J43,
  188 + S5PC100_GPIO_J44,
  189 + S5PC100_GPIO_J45,
  190 + S5PC100_GPIO_J46,
  191 + S5PC100_GPIO_J47,
  192 + S5PC100_GPIO_K00,
  193 + S5PC100_GPIO_K01,
  194 + S5PC100_GPIO_K02,
  195 + S5PC100_GPIO_K03,
  196 + S5PC100_GPIO_K04,
  197 + S5PC100_GPIO_K05,
  198 + S5PC100_GPIO_K06,
  199 + S5PC100_GPIO_K07,
  200 + S5PC100_GPIO_K10,
  201 + S5PC100_GPIO_K11,
  202 + S5PC100_GPIO_K12,
  203 + S5PC100_GPIO_K13,
  204 + S5PC100_GPIO_K14,
  205 + S5PC100_GPIO_K15,
  206 + S5PC100_GPIO_K16,
  207 + S5PC100_GPIO_K17,
  208 + S5PC100_GPIO_K20,
  209 + S5PC100_GPIO_K21,
  210 + S5PC100_GPIO_K22,
  211 + S5PC100_GPIO_K23,
  212 + S5PC100_GPIO_K24,
  213 + S5PC100_GPIO_K25,
  214 + S5PC100_GPIO_K26,
  215 + S5PC100_GPIO_K27,
  216 + S5PC100_GPIO_K30,
  217 + S5PC100_GPIO_K31,
  218 + S5PC100_GPIO_K32,
  219 + S5PC100_GPIO_K33,
  220 + S5PC100_GPIO_K34,
  221 + S5PC100_GPIO_K35,
  222 + S5PC100_GPIO_K36,
  223 + S5PC100_GPIO_K37,
  224 + S5PC100_GPIO_L00,
  225 + S5PC100_GPIO_L01,
  226 + S5PC100_GPIO_L02,
  227 + S5PC100_GPIO_L03,
  228 + S5PC100_GPIO_L04,
  229 + S5PC100_GPIO_L05,
  230 + S5PC100_GPIO_L06,
  231 + S5PC100_GPIO_L07,
  232 + S5PC100_GPIO_L10,
  233 + S5PC100_GPIO_L11,
  234 + S5PC100_GPIO_L12,
  235 + S5PC100_GPIO_L13,
  236 + S5PC100_GPIO_L14,
  237 + S5PC100_GPIO_L15,
  238 + S5PC100_GPIO_L16,
  239 + S5PC100_GPIO_L17,
  240 + S5PC100_GPIO_L20,
  241 + S5PC100_GPIO_L21,
  242 + S5PC100_GPIO_L22,
  243 + S5PC100_GPIO_L23,
  244 + S5PC100_GPIO_L24,
  245 + S5PC100_GPIO_L25,
  246 + S5PC100_GPIO_L26,
  247 + S5PC100_GPIO_L27,
  248 + S5PC100_GPIO_L30,
  249 + S5PC100_GPIO_L31,
  250 + S5PC100_GPIO_L32,
  251 + S5PC100_GPIO_L33,
  252 + S5PC100_GPIO_L34,
  253 + S5PC100_GPIO_L35,
  254 + S5PC100_GPIO_L36,
  255 + S5PC100_GPIO_L37,
  256 + S5PC100_GPIO_L40,
  257 + S5PC100_GPIO_L41,
  258 + S5PC100_GPIO_L42,
  259 + S5PC100_GPIO_L43,
  260 + S5PC100_GPIO_L44,
  261 + S5PC100_GPIO_L45,
  262 + S5PC100_GPIO_L46,
  263 + S5PC100_GPIO_L47,
  264 + S5PC100_GPIO_H00,
  265 + S5PC100_GPIO_H01,
  266 + S5PC100_GPIO_H02,
  267 + S5PC100_GPIO_H03,
  268 + S5PC100_GPIO_H04,
  269 + S5PC100_GPIO_H05,
  270 + S5PC100_GPIO_H06,
  271 + S5PC100_GPIO_H07,
  272 + S5PC100_GPIO_H10,
  273 + S5PC100_GPIO_H11,
  274 + S5PC100_GPIO_H12,
  275 + S5PC100_GPIO_H13,
  276 + S5PC100_GPIO_H14,
  277 + S5PC100_GPIO_H15,
  278 + S5PC100_GPIO_H16,
  279 + S5PC100_GPIO_H17,
  280 + S5PC100_GPIO_H20,
  281 + S5PC100_GPIO_H21,
  282 + S5PC100_GPIO_H22,
  283 + S5PC100_GPIO_H23,
  284 + S5PC100_GPIO_H24,
  285 + S5PC100_GPIO_H25,
  286 + S5PC100_GPIO_H26,
  287 + S5PC100_GPIO_H27,
  288 + S5PC100_GPIO_H30,
  289 + S5PC100_GPIO_H31,
  290 + S5PC100_GPIO_H32,
  291 + S5PC100_GPIO_H33,
  292 + S5PC100_GPIO_H34,
  293 + S5PC100_GPIO_H35,
  294 + S5PC100_GPIO_H36,
  295 + S5PC100_GPIO_H37,
  296 +
  297 + S5PC100_GPIO_MAX_PORT
  298 +};
  299 +
  300 +enum s5pc110_gpio_pin {
  301 + S5PC110_GPIO_A00,
  302 + S5PC110_GPIO_A01,
  303 + S5PC110_GPIO_A02,
  304 + S5PC110_GPIO_A03,
  305 + S5PC110_GPIO_A04,
  306 + S5PC110_GPIO_A05,
  307 + S5PC110_GPIO_A06,
  308 + S5PC110_GPIO_A07,
  309 + S5PC110_GPIO_A10,
  310 + S5PC110_GPIO_A11,
  311 + S5PC110_GPIO_A12,
  312 + S5PC110_GPIO_A13,
  313 + S5PC110_GPIO_A14,
  314 + S5PC110_GPIO_A15,
  315 + S5PC110_GPIO_A16,
  316 + S5PC110_GPIO_A17,
  317 + S5PC110_GPIO_B0,
  318 + S5PC110_GPIO_B1,
  319 + S5PC110_GPIO_B2,
  320 + S5PC110_GPIO_B3,
  321 + S5PC110_GPIO_B4,
  322 + S5PC110_GPIO_B5,
  323 + S5PC110_GPIO_B6,
  324 + S5PC110_GPIO_B7,
  325 + S5PC110_GPIO_C00,
  326 + S5PC110_GPIO_C01,
  327 + S5PC110_GPIO_C02,
  328 + S5PC110_GPIO_C03,
  329 + S5PC110_GPIO_C04,
  330 + S5PC110_GPIO_C05,
  331 + S5PC110_GPIO_C06,
  332 + S5PC110_GPIO_C07,
  333 + S5PC110_GPIO_C10,
  334 + S5PC110_GPIO_C11,
  335 + S5PC110_GPIO_C12,
  336 + S5PC110_GPIO_C13,
  337 + S5PC110_GPIO_C14,
  338 + S5PC110_GPIO_C15,
  339 + S5PC110_GPIO_C16,
  340 + S5PC110_GPIO_C17,
  341 + S5PC110_GPIO_D00,
  342 + S5PC110_GPIO_D01,
  343 + S5PC110_GPIO_D02,
  344 + S5PC110_GPIO_D03,
  345 + S5PC110_GPIO_D04,
  346 + S5PC110_GPIO_D05,
  347 + S5PC110_GPIO_D06,
  348 + S5PC110_GPIO_D07,
  349 + S5PC110_GPIO_D10,
  350 + S5PC110_GPIO_D11,
  351 + S5PC110_GPIO_D12,
  352 + S5PC110_GPIO_D13,
  353 + S5PC110_GPIO_D14,
  354 + S5PC110_GPIO_D15,
  355 + S5PC110_GPIO_D16,
  356 + S5PC110_GPIO_D17,
  357 + S5PC110_GPIO_E00,
  358 + S5PC110_GPIO_E01,
  359 + S5PC110_GPIO_E02,
  360 + S5PC110_GPIO_E03,
  361 + S5PC110_GPIO_E04,
  362 + S5PC110_GPIO_E05,
  363 + S5PC110_GPIO_E06,
  364 + S5PC110_GPIO_E07,
  365 + S5PC110_GPIO_E10,
  366 + S5PC110_GPIO_E11,
  367 + S5PC110_GPIO_E12,
  368 + S5PC110_GPIO_E13,
  369 + S5PC110_GPIO_E14,
  370 + S5PC110_GPIO_E15,
  371 + S5PC110_GPIO_E16,
  372 + S5PC110_GPIO_E17,
  373 + S5PC110_GPIO_F00,
  374 + S5PC110_GPIO_F01,
  375 + S5PC110_GPIO_F02,
  376 + S5PC110_GPIO_F03,
  377 + S5PC110_GPIO_F04,
  378 + S5PC110_GPIO_F05,
  379 + S5PC110_GPIO_F06,
  380 + S5PC110_GPIO_F07,
  381 + S5PC110_GPIO_F10,
  382 + S5PC110_GPIO_F11,
  383 + S5PC110_GPIO_F12,
  384 + S5PC110_GPIO_F13,
  385 + S5PC110_GPIO_F14,
  386 + S5PC110_GPIO_F15,
  387 + S5PC110_GPIO_F16,
  388 + S5PC110_GPIO_F17,
  389 + S5PC110_GPIO_F20,
  390 + S5PC110_GPIO_F21,
  391 + S5PC110_GPIO_F22,
  392 + S5PC110_GPIO_F23,
  393 + S5PC110_GPIO_F24,
  394 + S5PC110_GPIO_F25,
  395 + S5PC110_GPIO_F26,
  396 + S5PC110_GPIO_F27,
  397 + S5PC110_GPIO_F30,
  398 + S5PC110_GPIO_F31,
  399 + S5PC110_GPIO_F32,
  400 + S5PC110_GPIO_F33,
  401 + S5PC110_GPIO_F34,
  402 + S5PC110_GPIO_F35,
  403 + S5PC110_GPIO_F36,
  404 + S5PC110_GPIO_F37,
  405 + S5PC110_GPIO_G00,
  406 + S5PC110_GPIO_G01,
  407 + S5PC110_GPIO_G02,
  408 + S5PC110_GPIO_G03,
  409 + S5PC110_GPIO_G04,
  410 + S5PC110_GPIO_G05,
  411 + S5PC110_GPIO_G06,
  412 + S5PC110_GPIO_G07,
  413 + S5PC110_GPIO_G10,
  414 + S5PC110_GPIO_G11,
  415 + S5PC110_GPIO_G12,
  416 + S5PC110_GPIO_G13,
  417 + S5PC110_GPIO_G14,
  418 + S5PC110_GPIO_G15,
  419 + S5PC110_GPIO_G16,
  420 + S5PC110_GPIO_G17,
  421 + S5PC110_GPIO_G20,
  422 + S5PC110_GPIO_G21,
  423 + S5PC110_GPIO_G22,
  424 + S5PC110_GPIO_G23,
  425 + S5PC110_GPIO_G24,
  426 + S5PC110_GPIO_G25,
  427 + S5PC110_GPIO_G26,
  428 + S5PC110_GPIO_G27,
  429 + S5PC110_GPIO_G30,
  430 + S5PC110_GPIO_G31,
  431 + S5PC110_GPIO_G32,
  432 + S5PC110_GPIO_G33,
  433 + S5PC110_GPIO_G34,
  434 + S5PC110_GPIO_G35,
  435 + S5PC110_GPIO_G36,
  436 + S5PC110_GPIO_G37,
  437 + S5PC110_GPIO_I0,
  438 + S5PC110_GPIO_I1,
  439 + S5PC110_GPIO_I2,
  440 + S5PC110_GPIO_I3,
  441 + S5PC110_GPIO_I4,
  442 + S5PC110_GPIO_I5,
  443 + S5PC110_GPIO_I6,
  444 + S5PC110_GPIO_I7,
  445 + S5PC110_GPIO_J00,
  446 + S5PC110_GPIO_J01,
  447 + S5PC110_GPIO_J02,
  448 + S5PC110_GPIO_J03,
  449 + S5PC110_GPIO_J04,
  450 + S5PC110_GPIO_J05,
  451 + S5PC110_GPIO_J06,
  452 + S5PC110_GPIO_J07,
  453 + S5PC110_GPIO_J10,
  454 + S5PC110_GPIO_J11,
  455 + S5PC110_GPIO_J12,
  456 + S5PC110_GPIO_J13,
  457 + S5PC110_GPIO_J14,
  458 + S5PC110_GPIO_J15,
  459 + S5PC110_GPIO_J16,
  460 + S5PC110_GPIO_J17,
  461 + S5PC110_GPIO_J20,
  462 + S5PC110_GPIO_J21,
  463 + S5PC110_GPIO_J22,
  464 + S5PC110_GPIO_J23,
  465 + S5PC110_GPIO_J24,
  466 + S5PC110_GPIO_J25,
  467 + S5PC110_GPIO_J26,
  468 + S5PC110_GPIO_J27,
  469 + S5PC110_GPIO_J30,
  470 + S5PC110_GPIO_J31,
  471 + S5PC110_GPIO_J32,
  472 + S5PC110_GPIO_J33,
  473 + S5PC110_GPIO_J34,
  474 + S5PC110_GPIO_J35,
  475 + S5PC110_GPIO_J36,
  476 + S5PC110_GPIO_J37,
  477 + S5PC110_GPIO_J40,
  478 + S5PC110_GPIO_J41,
  479 + S5PC110_GPIO_J42,
  480 + S5PC110_GPIO_J43,
  481 + S5PC110_GPIO_J44,
  482 + S5PC110_GPIO_J45,
  483 + S5PC110_GPIO_J46,
  484 + S5PC110_GPIO_J47,
  485 + S5PC110_GPIO_MP010,
  486 + S5PC110_GPIO_MP011,
  487 + S5PC110_GPIO_MP012,
  488 + S5PC110_GPIO_MP013,
  489 + S5PC110_GPIO_MP014,
  490 + S5PC110_GPIO_MP015,
  491 + S5PC110_GPIO_MP016,
  492 + S5PC110_GPIO_MP017,
  493 + S5PC110_GPIO_MP020,
  494 + S5PC110_GPIO_MP021,
  495 + S5PC110_GPIO_MP022,
  496 + S5PC110_GPIO_MP023,
  497 + S5PC110_GPIO_MP024,
  498 + S5PC110_GPIO_MP025,
  499 + S5PC110_GPIO_MP026,
  500 + S5PC110_GPIO_MP027,
  501 + S5PC110_GPIO_MP030,
  502 + S5PC110_GPIO_MP031,
  503 + S5PC110_GPIO_MP032,
  504 + S5PC110_GPIO_MP033,
  505 + S5PC110_GPIO_MP034,
  506 + S5PC110_GPIO_MP035,
  507 + S5PC110_GPIO_MP036,
  508 + S5PC110_GPIO_MP037,
  509 + S5PC110_GPIO_MP040,
  510 + S5PC110_GPIO_MP041,
  511 + S5PC110_GPIO_MP042,
  512 + S5PC110_GPIO_MP043,
  513 + S5PC110_GPIO_MP044,
  514 + S5PC110_GPIO_MP045,
  515 + S5PC110_GPIO_MP046,
  516 + S5PC110_GPIO_MP047,
  517 + S5PC110_GPIO_MP050,
  518 + S5PC110_GPIO_MP051,
  519 + S5PC110_GPIO_MP052,
  520 + S5PC110_GPIO_MP053,
  521 + S5PC110_GPIO_MP054,
  522 + S5PC110_GPIO_MP055,
  523 + S5PC110_GPIO_MP056,
  524 + S5PC110_GPIO_MP057,
  525 + S5PC110_GPIO_MP060,
  526 + S5PC110_GPIO_MP061,
  527 + S5PC110_GPIO_MP062,
  528 + S5PC110_GPIO_MP063,
  529 + S5PC110_GPIO_MP064,
  530 + S5PC110_GPIO_MP065,
  531 + S5PC110_GPIO_MP066,
  532 + S5PC110_GPIO_MP067,
  533 + S5PC110_GPIO_MP070,
  534 + S5PC110_GPIO_MP071,
  535 + S5PC110_GPIO_MP072,
  536 + S5PC110_GPIO_MP073,
  537 + S5PC110_GPIO_MP074,
  538 + S5PC110_GPIO_MP075,
  539 + S5PC110_GPIO_MP076,
  540 + S5PC110_GPIO_MP077,
  541 + S5PC110_GPIO_MP100,
  542 + S5PC110_GPIO_MP101,
  543 + S5PC110_GPIO_MP102,
  544 + S5PC110_GPIO_MP103,
  545 + S5PC110_GPIO_MP104,
  546 + S5PC110_GPIO_MP105,
  547 + S5PC110_GPIO_MP106,
  548 + S5PC110_GPIO_MP107,
  549 + S5PC110_GPIO_MP110,
  550 + S5PC110_GPIO_MP111,
  551 + S5PC110_GPIO_MP112,
  552 + S5PC110_GPIO_MP113,
  553 + S5PC110_GPIO_MP114,
  554 + S5PC110_GPIO_MP115,
  555 + S5PC110_GPIO_MP116,
  556 + S5PC110_GPIO_MP117,
  557 + S5PC110_GPIO_MP120,
  558 + S5PC110_GPIO_MP121,
  559 + S5PC110_GPIO_MP122,
  560 + S5PC110_GPIO_MP123,
  561 + S5PC110_GPIO_MP124,
  562 + S5PC110_GPIO_MP125,
  563 + S5PC110_GPIO_MP126,
  564 + S5PC110_GPIO_MP127,
  565 + S5PC110_GPIO_MP130,
  566 + S5PC110_GPIO_MP131,
  567 + S5PC110_GPIO_MP132,
  568 + S5PC110_GPIO_MP133,
  569 + S5PC110_GPIO_MP134,
  570 + S5PC110_GPIO_MP135,
  571 + S5PC110_GPIO_MP136,
  572 + S5PC110_GPIO_MP137,
  573 + S5PC110_GPIO_MP140,
  574 + S5PC110_GPIO_MP141,
  575 + S5PC110_GPIO_MP142,
  576 + S5PC110_GPIO_MP143,
  577 + S5PC110_GPIO_MP144,
  578 + S5PC110_GPIO_MP145,
  579 + S5PC110_GPIO_MP146,
  580 + S5PC110_GPIO_MP147,
  581 + S5PC110_GPIO_MP150,
  582 + S5PC110_GPIO_MP151,
  583 + S5PC110_GPIO_MP152,
  584 + S5PC110_GPIO_MP153,
  585 + S5PC110_GPIO_MP154,
  586 + S5PC110_GPIO_MP155,
  587 + S5PC110_GPIO_MP156,
  588 + S5PC110_GPIO_MP157,
  589 + S5PC110_GPIO_MP160,
  590 + S5PC110_GPIO_MP161,
  591 + S5PC110_GPIO_MP162,
  592 + S5PC110_GPIO_MP163,
  593 + S5PC110_GPIO_MP164,
  594 + S5PC110_GPIO_MP165,
  595 + S5PC110_GPIO_MP166,
  596 + S5PC110_GPIO_MP167,
  597 + S5PC110_GPIO_MP170,
  598 + S5PC110_GPIO_MP171,
  599 + S5PC110_GPIO_MP172,
  600 + S5PC110_GPIO_MP173,
  601 + S5PC110_GPIO_MP174,
  602 + S5PC110_GPIO_MP175,
  603 + S5PC110_GPIO_MP176,
  604 + S5PC110_GPIO_MP177,
  605 + S5PC110_GPIO_MP180,
  606 + S5PC110_GPIO_MP181,
  607 + S5PC110_GPIO_MP182,
  608 + S5PC110_GPIO_MP183,
  609 + S5PC110_GPIO_MP184,
  610 + S5PC110_GPIO_MP185,
  611 + S5PC110_GPIO_MP186,
  612 + S5PC110_GPIO_MP187,
  613 + S5PC110_GPIO_MP200,
  614 + S5PC110_GPIO_MP201,
  615 + S5PC110_GPIO_MP202,
  616 + S5PC110_GPIO_MP203,
  617 + S5PC110_GPIO_MP204,
  618 + S5PC110_GPIO_MP205,
  619 + S5PC110_GPIO_MP206,
  620 + S5PC110_GPIO_MP207,
  621 + S5PC110_GPIO_MP210,
  622 + S5PC110_GPIO_MP211,
  623 + S5PC110_GPIO_MP212,
  624 + S5PC110_GPIO_MP213,
  625 + S5PC110_GPIO_MP214,
  626 + S5PC110_GPIO_MP215,
  627 + S5PC110_GPIO_MP216,
  628 + S5PC110_GPIO_MP217,
  629 + S5PC110_GPIO_MP220,
  630 + S5PC110_GPIO_MP221,
  631 + S5PC110_GPIO_MP222,
  632 + S5PC110_GPIO_MP223,
  633 + S5PC110_GPIO_MP224,
  634 + S5PC110_GPIO_MP225,
  635 + S5PC110_GPIO_MP226,
  636 + S5PC110_GPIO_MP227,
  637 + S5PC110_GPIO_MP230,
  638 + S5PC110_GPIO_MP231,
  639 + S5PC110_GPIO_MP232,
  640 + S5PC110_GPIO_MP233,
  641 + S5PC110_GPIO_MP234,
  642 + S5PC110_GPIO_MP235,
  643 + S5PC110_GPIO_MP236,
  644 + S5PC110_GPIO_MP237,
  645 + S5PC110_GPIO_MP240,
  646 + S5PC110_GPIO_MP241,
  647 + S5PC110_GPIO_MP242,
  648 + S5PC110_GPIO_MP243,
  649 + S5PC110_GPIO_MP244,
  650 + S5PC110_GPIO_MP245,
  651 + S5PC110_GPIO_MP246,
  652 + S5PC110_GPIO_MP247,
  653 + S5PC110_GPIO_MP250,
  654 + S5PC110_GPIO_MP251,
  655 + S5PC110_GPIO_MP252,
  656 + S5PC110_GPIO_MP253,
  657 + S5PC110_GPIO_MP254,
  658 + S5PC110_GPIO_MP255,
  659 + S5PC110_GPIO_MP256,
  660 + S5PC110_GPIO_MP257,
  661 + S5PC110_GPIO_MP260,
  662 + S5PC110_GPIO_MP261,
  663 + S5PC110_GPIO_MP262,
  664 + S5PC110_GPIO_MP263,
  665 + S5PC110_GPIO_MP264,
  666 + S5PC110_GPIO_MP265,
  667 + S5PC110_GPIO_MP266,
  668 + S5PC110_GPIO_MP267,
  669 + S5PC110_GPIO_MP270,
  670 + S5PC110_GPIO_MP271,
  671 + S5PC110_GPIO_MP272,
  672 + S5PC110_GPIO_MP273,
  673 + S5PC110_GPIO_MP274,
  674 + S5PC110_GPIO_MP275,
  675 + S5PC110_GPIO_MP276,
  676 + S5PC110_GPIO_MP277,
  677 + S5PC110_GPIO_MP280,
  678 + S5PC110_GPIO_MP281,
  679 + S5PC110_GPIO_MP282,
  680 + S5PC110_GPIO_MP283,
  681 + S5PC110_GPIO_MP284,
  682 + S5PC110_GPIO_MP285,
  683 + S5PC110_GPIO_MP286,
  684 + S5PC110_GPIO_MP287,
  685 + S5PC110_GPIO_H00,
  686 + S5PC110_GPIO_H01,
  687 + S5PC110_GPIO_H02,
  688 + S5PC110_GPIO_H03,
  689 + S5PC110_GPIO_H04,
  690 + S5PC110_GPIO_H05,
  691 + S5PC110_GPIO_H06,
  692 + S5PC110_GPIO_H07,
  693 + S5PC110_GPIO_H10,
  694 + S5PC110_GPIO_H11,
  695 + S5PC110_GPIO_H12,
  696 + S5PC110_GPIO_H13,
  697 + S5PC110_GPIO_H14,
  698 + S5PC110_GPIO_H15,
  699 + S5PC110_GPIO_H16,
  700 + S5PC110_GPIO_H17,
  701 + S5PC110_GPIO_H20,
  702 + S5PC110_GPIO_H21,
  703 + S5PC110_GPIO_H22,
  704 + S5PC110_GPIO_H23,
  705 + S5PC110_GPIO_H24,
  706 + S5PC110_GPIO_H25,
  707 + S5PC110_GPIO_H26,
  708 + S5PC110_GPIO_H27,
  709 + S5PC110_GPIO_H30,
  710 + S5PC110_GPIO_H31,
  711 + S5PC110_GPIO_H32,
  712 + S5PC110_GPIO_H33,
  713 + S5PC110_GPIO_H34,
  714 + S5PC110_GPIO_H35,
  715 + S5PC110_GPIO_H36,
  716 + S5PC110_GPIO_H37,
  717 +
  718 + S5PC110_GPIO_MAX_PORT
  719 +};
  720 +
  721 +struct gpio_info {
  722 + unsigned int reg_addr; /* Address of register for this part */
  723 + unsigned int max_gpio; /* Maximum GPIO in this part */
  724 +};
  725 +
  726 +#define S5PC100_GPIO_NUM_PARTS 1
  727 +static struct gpio_info s5pc100_gpio_data[S5PC100_GPIO_NUM_PARTS] = {
  728 + { S5PC100_GPIO_BASE, S5PC100_GPIO_MAX_PORT },
  729 +};
  730 +
  731 +#define S5PC110_GPIO_NUM_PARTS 1
  732 +static struct gpio_info s5pc110_gpio_data[S5PC110_GPIO_NUM_PARTS] = {
  733 + { S5PC110_GPIO_BASE, S5PC110_GPIO_MAX_PORT },
  734 +};
  735 +
  736 +static inline struct gpio_info *get_gpio_data(void)
  737 +{
  738 + if (cpu_is_s5pc100())
  739 + return s5pc100_gpio_data;
  740 + else if (cpu_is_s5pc110())
  741 + return s5pc110_gpio_data;
  742 +
  743 + return NULL;
  744 +}
  745 +
  746 +static inline unsigned int get_bank_num(void)
  747 +{
  748 + if (cpu_is_s5pc100())
  749 + return S5PC100_GPIO_NUM_PARTS;
  750 + else if (cpu_is_s5pc110())
  751 + return S5PC110_GPIO_NUM_PARTS;
  752 +
  753 + return 0;
  754 +}
  755 +
  756 +/*
  757 + * This structure helps mapping symbolic GPIO names into indices from
  758 + * exynos5_gpio_pin/exynos5420_gpio_pin enums.
  759 + *
  760 + * By convention, symbolic GPIO name is defined as follows:
  761 + *
  762 + * g[p]<bank><set><bit>, where
  763 + * p is optional
  764 + * <bank> - a single character bank name, as defined by the SOC
  765 + * <set> - a single digit set number
  766 + * <bit> - bit number within the set (in 0..7 range).
  767 + *
  768 + * <set><bit> essentially form an octal number of the GPIO pin within the bank
  769 + * space. On the 5420 architecture some banks' sets do not start not from zero
  770 + * ('d' starts from 1 and 'j' starts from 4). To compensate for that and
  771 + * maintain flat number space withoout holes, those banks use offsets to be
  772 + * deducted from the pin number.
  773 + */
  774 +struct gpio_name_num_table {
  775 + char bank; /* bank name symbol */
  776 + u8 bank_size; /* total number of pins in the bank */
  777 + char bank_offset; /* offset of the first bank's pin */
  778 + unsigned int base; /* index of the first bank's pin in the enum */
  779 +};
  780 +
  781 +#define GPIO_PER_BANK 8
  782 +#define GPIO_ENTRY(name, base, top, offset) { name, top - base, offset, base }
  783 +static const struct gpio_name_num_table s5pc100_gpio_table[] = {
  784 + GPIO_ENTRY('a', S5PC100_GPIO_A00, S5PC100_GPIO_B0, 0),
  785 + GPIO_ENTRY('b', S5PC100_GPIO_B0, S5PC100_GPIO_C0, 0),
  786 + GPIO_ENTRY('c', S5PC100_GPIO_C0, S5PC100_GPIO_D0, 0),
  787 + GPIO_ENTRY('d', S5PC100_GPIO_D0, S5PC100_GPIO_E00, 0),
  788 + GPIO_ENTRY('e', S5PC100_GPIO_E00, S5PC100_GPIO_F00, 0),
  789 + GPIO_ENTRY('f', S5PC100_GPIO_F00, S5PC100_GPIO_G00, 0),
  790 + GPIO_ENTRY('g', S5PC100_GPIO_G00, S5PC100_GPIO_I0, 0),
  791 + GPIO_ENTRY('i', S5PC100_GPIO_I0, S5PC100_GPIO_J00, 0),
  792 + GPIO_ENTRY('j', S5PC100_GPIO_J00, S5PC100_GPIO_K00, 0),
  793 + GPIO_ENTRY('k', S5PC100_GPIO_K00, S5PC100_GPIO_L00, 0),
  794 + GPIO_ENTRY('l', S5PC100_GPIO_L00, S5PC100_GPIO_H00, 0),
  795 + GPIO_ENTRY('h', S5PC100_GPIO_H00, S5PC100_GPIO_MAX_PORT, 0),
  796 + { 0 }
  797 +};
  798 +
  799 +static const struct gpio_name_num_table s5pc110_gpio_table[] = {
  800 + GPIO_ENTRY('a', S5PC110_GPIO_A00, S5PC110_GPIO_B0, 0),
  801 + GPIO_ENTRY('b', S5PC110_GPIO_B0, S5PC110_GPIO_C00, 0),
  802 + GPIO_ENTRY('c', S5PC110_GPIO_C00, S5PC110_GPIO_D00, 0),
  803 + GPIO_ENTRY('d', S5PC110_GPIO_D00, S5PC110_GPIO_E00, 0),
  804 + GPIO_ENTRY('e', S5PC110_GPIO_E00, S5PC110_GPIO_F00, 0),
  805 + GPIO_ENTRY('f', S5PC110_GPIO_F00, S5PC110_GPIO_G00, 0),
  806 + GPIO_ENTRY('g', S5PC110_GPIO_G00, S5PC110_GPIO_I0, 0),
  807 + GPIO_ENTRY('i', S5PC110_GPIO_I0, S5PC110_GPIO_J00, 0),
  808 + GPIO_ENTRY('j', S5PC110_GPIO_J00, S5PC110_GPIO_MP010, 0),
  809 + GPIO_ENTRY('h', S5PC110_GPIO_H00, S5PC110_GPIO_MAX_PORT, 0),
  810 + { 0 }
  811 +};
  812 +
  813 +/* functions */
  814 +void gpio_cfg_pin(int gpio, int cfg);
  815 +void gpio_set_pull(int gpio, int mode);
  816 +void gpio_set_drv(int gpio, int mode);
  817 +void gpio_set_rate(int gpio, int mode);
  818 +int s5p_gpio_get_pin(unsigned gpio);
  819 +
  820 +/* GPIO pins per bank */
  821 +#define GPIO_PER_BANK 8
  822 +#endif
  823 +
  824 +/* Pin configurations */
  825 +#define S5P_GPIO_INPUT 0x0
  826 +#define S5P_GPIO_OUTPUT 0x1
  827 +#define S5P_GPIO_IRQ 0xf
  828 +#define S5P_GPIO_FUNC(x) (x)
  829 +
  830 +/* Pull mode */
  831 +#define S5P_GPIO_PULL_NONE 0x0
  832 +#define S5P_GPIO_PULL_DOWN 0x1
  833 +#define S5P_GPIO_PULL_UP 0x2
  834 +
  835 +/* Drive Strength level */
  836 +#define S5P_GPIO_DRV_1X 0x0
  837 +#define S5P_GPIO_DRV_3X 0x1
  838 +#define S5P_GPIO_DRV_2X 0x2
  839 +#define S5P_GPIO_DRV_4X 0x3
  840 +#define S5P_GPIO_DRV_FAST 0x0
  841 +#define S5P_GPIO_DRV_SLOW 0x1
  842 +
  843 +#endif
arch/arm/mach-s5pc1xx/include/mach/mmc.h
Diff comments   View file @ 225f5ee
  1 +/*
  2 + * (C) Copyright 2009 SAMSUNG Electronics
  3 + * Minkyu Kang <mk7.kang@samsung.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef __ASM_ARCH_MMC_H_
  9 +#define __ASM_ARCH_MMC_H_
  10 +
  11 +#define S5P_MMC_DEV_OFFSET 0x100000
  12 +
  13 +#define SDHCI_CONTROL2 0x80
  14 +#define SDHCI_CONTROL3 0x84
  15 +#define SDHCI_CONTROL4 0x8C
  16 +
  17 +#define SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31)
  18 +#define SDHCI_CTRL2_ENCMDCNFMSK (1 << 30)
  19 +#define SDHCI_CTRL2_CDINVRXD3 (1 << 29)
  20 +#define SDHCI_CTRL2_SLCARDOUT (1 << 28)
  21 +
  22 +#define SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24)
  23 +#define SDHCI_CTRL2_FLTCLKSEL_SHIFT (24)
  24 +#define SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24)
  25 +
  26 +#define SDHCI_CTRL2_LVLDAT_MASK (0xff << 16)
  27 +#define SDHCI_CTRL2_LVLDAT_SHIFT (16)
  28 +#define SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16)
  29 +
  30 +#define SDHCI_CTRL2_ENFBCLKTX (1 << 15)
  31 +#define SDHCI_CTRL2_ENFBCLKRX (1 << 14)
  32 +#define SDHCI_CTRL2_SDCDSEL (1 << 13)
  33 +#define SDHCI_CTRL2_SDSIGPC (1 << 12)
  34 +#define SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11)
  35 +
  36 +#define SDHCI_CTRL2_DFCNT_MASK(_x) ((_x) << 9)
  37 +#define SDHCI_CTRL2_DFCNT_SHIFT (9)
  38 +
  39 +#define SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8)
  40 +#define SDHCI_CTRL2_RWAITMODE (1 << 7)
  41 +#define SDHCI_CTRL2_DISBUFRD (1 << 6)
  42 +#define SDHCI_CTRL2_SELBASECLK_MASK(_x) ((_x) << 4)
  43 +#define SDHCI_CTRL2_SELBASECLK_SHIFT (4)
  44 +#define SDHCI_CTRL2_PWRSYNC (1 << 3)
  45 +#define SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1)
  46 +#define SDHCI_CTRL2_HWINITFIN (1 << 0)
  47 +
  48 +#define SDHCI_CTRL3_FCSEL3 (1 << 31)
  49 +#define SDHCI_CTRL3_FCSEL2 (1 << 23)
  50 +#define SDHCI_CTRL3_FCSEL1 (1 << 15)
  51 +#define SDHCI_CTRL3_FCSEL0 (1 << 7)
  52 +
  53 +#define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16)
  54 +#define SDHCI_CTRL4_DRIVE_SHIFT (16)
  55 +
  56 +int s5p_sdhci_init(u32 regbase, int index, int bus_width);
  57 +
  58 +static inline int s5p_mmc_init(int index, int bus_width)
  59 +{
  60 + unsigned int base = samsung_get_base_mmc() +
  61 + (S5P_MMC_DEV_OFFSET * index);
  62 +
  63 + return s5p_sdhci_init(base, index, bus_width);
  64 +}
  65 +#endif
arch/arm/mach-s5pc1xx/include/mach/periph.h
Diff comments   View file @ 225f5ee
  1 +/*
  2 + * Copyright (C) 2012 Samsung Electronics
  3 + * Rajeshwari Shinde <rajeshwari.s@samsung.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef __ASM_ARM_ARCH_PERIPH_H
  9 +#define __ASM_ARM_ARCH_PERIPH_H
  10 +
  11 +/*
  12 + * Peripherals required for pinmux configuration. List will
  13 + * grow with support for more devices getting added.
  14 + * Numbering based on interrupt table.
  15 + *
  16 + */
  17 +enum periph_id {
  18 + PERIPH_ID_UART0 = 51,
  19 + PERIPH_ID_UART1,
  20 + PERIPH_ID_UART2,
  21 + PERIPH_ID_UART3,
  22 + PERIPH_ID_I2C0 = 56,
  23 + PERIPH_ID_I2C1,
  24 + PERIPH_ID_I2C2,
  25 + PERIPH_ID_I2C3,
  26 + PERIPH_ID_I2C4,
  27 + PERIPH_ID_I2C5,
  28 + PERIPH_ID_I2C6,
  29 + PERIPH_ID_I2C7,
  30 + PERIPH_ID_SPI0 = 68,
  31 + PERIPH_ID_SPI1,
  32 + PERIPH_ID_SPI2,
  33 + PERIPH_ID_SDMMC0 = 75,
  34 + PERIPH_ID_SDMMC1,
  35 + PERIPH_ID_SDMMC2,
  36 + PERIPH_ID_SDMMC3,
  37 + PERIPH_ID_I2C8 = 87,
  38 + PERIPH_ID_I2C9,
  39 + PERIPH_ID_I2S0 = 98,
  40 + PERIPH_ID_I2S1 = 99,
  41 +
  42 + /* Since following peripherals do
  43 + * not have shared peripheral interrupts (SPIs)
  44 + * they are numbered arbitiraly after the maximum
  45 + * SPIs Exynos has (128)
  46 + */
  47 + PERIPH_ID_SROMC = 128,
  48 + PERIPH_ID_SPI3,
  49 + PERIPH_ID_SPI4,
  50 + PERIPH_ID_SDMMC4,
  51 + PERIPH_ID_PWM0,
  52 + PERIPH_ID_PWM1,
  53 + PERIPH_ID_PWM2,
  54 + PERIPH_ID_PWM3,
  55 + PERIPH_ID_PWM4,
  56 + PERIPH_ID_I2C10 = 203,
  57 +
  58 + PERIPH_ID_NONE = -1,
  59 +};
  60 +
  61 +#endif /* __ASM_ARM_ARCH_PERIPH_H */
arch/arm/mach-s5pc1xx/include/mach/pinmux.h
Diff comments   View file @ 225f5ee
  1 +/*
  2 + * Copyright (C) 2012 Samsung Electronics
  3 + * Abhilash Kesavan <a.kesavan@samsung.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef __ASM_ARM_ARCH_PINMUX_H
  9 +#define __ASM_ARM_ARCH_PINMUX_H
  10 +
  11 +#include "periph.h"
  12 +
  13 +/*
  14 + * Flags for setting specific configarations of peripherals.
  15 + * List will grow with support for more devices getting added.
  16 + */
  17 +enum {
  18 + PINMUX_FLAG_NONE = 0x00000000,
  19 +
  20 + /* Flags for eMMC */
  21 + PINMUX_FLAG_8BIT_MODE = 1 << 0, /* SDMMC 8-bit mode */
  22 +
  23 + /* Flags for SROM controller */
  24 + PINMUX_FLAG_BANK = 3 << 0, /* bank number (0-3) */
  25 + PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */
  26 +};
  27 +
  28 +/**
  29 + * Configures the pinmux for a particular peripheral.
  30 + *
  31 + * Each gpio can be configured in many different ways (4 bits on exynos)
  32 + * such as "input", "output", "special function", "external interrupt"
  33 + * etc. This function will configure the peripheral pinmux along with
  34 + * pull-up/down and drive strength.
  35 + *
  36 + * @param peripheral peripheral to be configured
  37 + * @param flags configure flags
  38 + * @return 0 if ok, -1 on error (e.g. unsupported peripheral)
  39 + */
  40 +int exynos_pinmux_config(int peripheral, int flags);
  41 +
  42 +/**
  43 + * Decode the peripheral id using the interrpt numbers.
  44 + *
  45 + * @param blob Device tree blob
  46 + * @param node FDT I2C node to find
  47 + * @return peripheral id if ok, PERIPH_ID_NONE on error
  48 + */
  49 +int pinmux_decode_periph_id(const void *blob, int node);
  50 +#endif
arch/arm/mach-s5pc1xx/include/mach/power.h
Diff comments   View file @ 225f5ee
  1 +/*
  2 + * Copyright (c) 2009 Samsung Electronics
  3 + * Kyungmin Park <kyungmin.park@samsung.com>
  4 + * Minkyu Kang <mk7.kang@samsung.com>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef __ASM_ARM_ARCH_POWER_H_
  10 +#define __ASM_ARM_ARCH_POWER_H_
  11 +
  12 +/*
  13 + * Power control
  14 + */
  15 +#define S5PC100_OTHERS 0xE0108200
  16 +#define S5PC100_RST_STAT 0xE0108300
  17 +#define S5PC100_SLEEP_WAKEUP (1 << 3)
  18 +#define S5PC100_WAKEUP_STAT 0xE0108304
  19 +#define S5PC100_INFORM0 0xE0108400
  20 +
  21 +#define S5PC110_RST_STAT 0xE010A000
  22 +#define S5PC110_SLEEP_WAKEUP (1 << 3)
  23 +#define S5PC110_WAKEUP_STAT 0xE010C200
  24 +#define S5PC110_OTHERS 0xE010E000
  25 +#define S5PC110_USB_PHY_CON 0xE010E80C
  26 +#define S5PC110_INFORM0 0xE010F000
  27 +
  28 +#endif
arch/arm/mach-s5pc1xx/include/mach/pwm.h
Diff comments   View file @ 225f5ee
  1 +/*
  2 + * Copyright (C) 2009 Samsung Electronics
  3 + * Kyungmin Park <kyungmin.park@samsung.com>
  4 + * Minkyu Kang <mk7.kang@samsung.com>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef __ASM_ARM_ARCH_PWM_H_
  10 +#define __ASM_ARM_ARCH_PWM_H_
  11 +
  12 +#define PRESCALER_0 (8 - 1) /* prescaler of timer 0, 1 */
  13 +#define PRESCALER_1 (16 - 1) /* prescaler of timer 2, 3, 4 */
  14 +
  15 +/* Divider MUX */
  16 +#define MUX_DIV_1 0 /* 1/1 period */
  17 +#define MUX_DIV_2 1 /* 1/2 period */
  18 +#define MUX_DIV_4 2 /* 1/4 period */
  19 +#define MUX_DIV_8 3 /* 1/8 period */
  20 +#define MUX_DIV_16 4 /* 1/16 period */
  21 +
  22 +#define MUX_DIV_SHIFT(x) (x * 4)
  23 +
  24 +#define TCON_OFFSET(x) ((x + 1) * (!!x) << 2)
  25 +
  26 +#define TCON_START(x) (1 << TCON_OFFSET(x))
  27 +#define TCON_UPDATE(x) (1 << (TCON_OFFSET(x) + 1))
  28 +#define TCON_INVERTER(x) (1 << (TCON_OFFSET(x) + 2))
  29 +#define TCON_AUTO_RELOAD(x) (1 << (TCON_OFFSET(x) + 3))
  30 +#define TCON4_AUTO_RELOAD (1 << 22)
  31 +
  32 +#ifndef __ASSEMBLY__
  33 +struct s5p_timer {
  34 + unsigned int tcfg0;
  35 + unsigned int tcfg1;
  36 + unsigned int tcon;
  37 + unsigned int tcntb0;
  38 + unsigned int tcmpb0;
  39 + unsigned int tcnto0;
  40 + unsigned int tcntb1;
  41 + unsigned int tcmpb1;
  42 + unsigned int tcnto1;
  43 + unsigned int tcntb2;
  44 + unsigned int tcmpb2;
  45 + unsigned int tcnto2;
  46 + unsigned int tcntb3;
  47 + unsigned int res1;
  48 + unsigned int tcnto3;
  49 + unsigned int tcntb4;
  50 + unsigned int tcnto4;
  51 + unsigned int tintcstat;
  52 +};
  53 +#endif /* __ASSEMBLY__ */
  54 +
  55 +#endif
arch/arm/mach-s5pc1xx/include/mach/sromc.h
Diff comments   View file @ 225f5ee
  1 +/*
  2 + * (C) Copyright 2010 Samsung Electronics
  3 + * Naveen Krishna Ch <ch.naveen@samsung.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + *
  7 + * Note: This file contains the register description for Memory subsystem
  8 + * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
  9 + *
  10 + * Only SROMC is defined as of now
  11 + */
  12 +
  13 +#ifndef __ASM_ARCH_SROMC_H_
  14 +#define __ASM_ARCH_SROMC_H_
  15 +
  16 +#define SMC_DATA16_WIDTH(x) (1<<((x*4)+0))
  17 +#define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/
  18 + /* 1-> Byte base address*/
  19 +#define SMC_WAIT_ENABLE(x) (1<<((x*4)+2))
  20 +#define SMC_BYTE_ENABLE(x) (1<<((x*4)+3))
  21 +
  22 +#define SMC_BC_TACS(x) (x << 28) /* 0clk address set-up */
  23 +#define SMC_BC_TCOS(x) (x << 24) /* 4clk chip selection set-up */
  24 +#define SMC_BC_TACC(x) (x << 16) /* 14clk access cycle */
  25 +#define SMC_BC_TCOH(x) (x << 12) /* 1clk chip selection hold */
  26 +#define SMC_BC_TAH(x) (x << 8) /* 4clk address holding time */
  27 +#define SMC_BC_TACP(x) (x << 4) /* 6clk page mode access cycle */
  28 +#define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
  29 +
  30 +#ifndef __ASSEMBLY__
  31 +struct s5p_sromc {
  32 + unsigned int bw;
  33 + unsigned int bc[6];
  34 +};
  35 +#endif /* __ASSEMBLY__ */
  36 +
  37 +/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
  38 +void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
  39 +
  40 +#endif /* __ASM_ARCH_SMC_H_ */
arch/arm/mach-s5pc1xx/include/mach/sys_proto.h
Diff comments   View file @ 225f5ee
  1 +/*
  2 + * Copyright (C) 2009 Samsung Electrnoics
  3 + * Minkyu Kang <mk7.kang@samsung.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef _SYS_PROTO_H_
  9 +#define _SYS_PROTO_H_
  10 +
  11 +u32 get_device_type(void);
  12 +
  13 +#endif
arch/arm/mach-s5pc1xx/include/mach/uart.h
Diff comments   View file @ 225f5ee
  1 +/*
  2 + * (C) Copyright 2009 Samsung Electronics
  3 + * Minkyu Kang <mk7.kang@samsung.com>
  4 + * Heungjun Kim <riverful.kim@samsung.com>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef __ASM_ARCH_UART_H_
  10 +#define __ASM_ARCH_UART_H_
  11 +
  12 +#ifndef __ASSEMBLY__
  13 +/* baudrate rest value */
  14 +union br_rest {
  15 + unsigned short slot; /* udivslot */
  16 + unsigned char value; /* ufracval */
  17 +};
  18 +
  19 +struct s5p_uart {
  20 + unsigned int ulcon;
  21 + unsigned int ucon;
  22 + unsigned int ufcon;
  23 + unsigned int umcon;
  24 + unsigned int utrstat;
  25 + unsigned int uerstat;
  26 + unsigned int ufstat;
  27 + unsigned int umstat;
  28 + unsigned char utxh;
  29 + unsigned char res1[3];
  30 + unsigned char urxh;
  31 + unsigned char res2[3];
  32 + unsigned int ubrdiv;
  33 + union br_rest rest;
  34 + unsigned char res3[0x3d0];
  35 +};
  36 +
  37 +static inline int s5p_uart_divslot(void)
  38 +{
  39 + return 1;
  40 +}
  41 +
  42 +#endif /* __ASSEMBLY__ */
  43 +
  44 +#endif
arch/arm/mach-s5pc1xx/include/mach/watchdog.h
Diff comments   View file @ 225f5ee
  1 +/*
  2 + * Copyright (C) 2011 Samsung Electronics
  3 + * Heungjun Kim <riverful.kim@samsung.com>
  4 + * Minkyu Kang <mk7.kang@samsung.com>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef __ASM_ARM_ARCH_WATCHDOG_H_
  10 +#define __ASM_ARM_ARCH_WATCHDOG_H_
  11 +
  12 +#define WTCON_RESET_OFFSET 0
  13 +#define WTCON_INTEN_OFFSET 2
  14 +#define WTCON_CLKSEL_OFFSET 3
  15 +#define WTCON_EN_OFFSET 5
  16 +#define WTCON_PRE_OFFSET 8
  17 +
  18 +#define WTCON_CLK_16 0x0
  19 +#define WTCON_CLK_32 0x1
  20 +#define WTCON_CLK_64 0x2
  21 +#define WTCON_CLK_128 0x3
  22 +
  23 +#define WTCON_CLK(x) ((x & 0x3) << WTCON_CLKSEL_OFFSET)
  24 +#define WTCON_PRESCALER(x) ((x) << WTCON_PRE_OFFSET)
  25 +#define WTCON_EN (0x1 << WTCON_EN_OFFSET)
  26 +#define WTCON_RESET (0x1 << WTCON_RESET_OFFSET)
  27 +#define WTCON_INT (0x1 << WTCON_INTEN_OFFSET)
  28 +
  29 +#ifndef __ASSEMBLY__
  30 +struct s5p_watchdog {
  31 + unsigned int wtcon;
  32 + unsigned int wtdat;
  33 + unsigned int wtcnt;
  34 + unsigned int wtclrint;
  35 +};
  36 +
  37 +/* functions */
  38 +void wdt_stop(void);
  39 +void wdt_start(unsigned int timeout);
  40 +#endif /* __ASSEMBLY__ */
  41 +
  42 +#endif
arch/arm/mach-s5pc1xx/reset.S
Diff comments   View file @ 225f5ee
  1 +/*
  2 + * Copyright (c) 2009 Samsung Electronics.
  3 + * Minkyu Kang <mk7.kang@samsung.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <asm/arch/cpu.h>
  9 +#include <linux/linkage.h>
  10 +
  11 +#define S5PC100_SWRESET 0xE0200000
  12 +#define S5PC110_SWRESET 0xE0102000
  13 +
  14 +ENTRY(reset_cpu)
  15 + ldr r1, =S5PC100_PRO_ID
  16 + ldr r2, [r1]
  17 + ldr r4, =0x00010000
  18 + and r4, r2, r4
  19 + cmp r4, #0
  20 + bne 110f
  21 + /* S5PC100 */
  22 + ldr r1, =S5PC100_SWRESET
  23 + ldr r2, =0xC100
  24 + b 200f
  25 +110: /* S5PC110 */
  26 + ldr r1, =S5PC110_SWRESET
  27 + mov r2, #1
  28 +200:
  29 + str r2, [r1]
  30 +_loop_forever:
  31 + b _loop_forever
  32 +ENDPROC(reset_cpu)