Eric Lee / smarc-uboot

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Commit 2290fe06421720d1c54523a9acf1052181bc6e87

Authored by Hannes Schmelzer
Committed by Tom Rini
1 parent 8ada4e0ee6
Exists in v2017.01-smarct4x and in 25 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2017.01-smarct3x, v2017.01-smarct3x-emmc

board/BuR: rename tseries board to brppt1 

Rename B&R tseries board to brppt1

Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Tom Rini <trini@konsulko.com>

Showing 19 changed files with 888 additions and 888 deletions Side-by-side Diff

... ... @@ -309,8 +309,8 @@
309 309 select CPU_V7
310 310 select SUPPORT_SPL
311 311  
312   -config TARGET_TSERIES
313   - bool "Support tseries"
  312 +config TARGET_BRPPT1
  313 + bool "Support BRPPT1"
314 314 select CPU_V7
315 315 select SUPPORT_SPL
316 316  
... ... @@ -909,7 +909,7 @@
909 909  
910 910 source "board/bosch/shc/Kconfig"
911 911 source "board/BuR/kwb/Kconfig"
912   -source "board/BuR/tseries/Kconfig"
  912 +source "board/BuR/brppt1/Kconfig"
913 913 source "board/CarMediaLab/flea3/Kconfig"
914 914 source "board/Marvell/aspenite/Kconfig"
915 915 source "board/Marvell/gplugd/Kconfig"
board/BuR/brppt1/Kconfig
Diff comments   View file @ 2290fe0
  1 +if TARGET_BRPPT1
  2 +
  3 +config SYS_BOARD
  4 + default "brppt1"
  5 +
  6 +config SYS_VENDOR
  7 + default "BuR"
  8 +
  9 +config SYS_SOC
  10 + default "am33xx"
  11 +
  12 +config SYS_CONFIG_NAME
  13 + default "brppt1"
  14 +
  15 +endif
board/BuR/brppt1/MAINTAINERS
Diff comments   View file @ 2290fe0
  1 +BRPPT1 BOARD
  2 +M: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
  3 +S: Maintained
  4 +F: board/BuR/brppt1/
  5 +F: include/configs/brppt1.h
  6 +F: configs/brppt1_mmc_defconfig
  7 +F: configs/brppt1_nand_defconfig
  8 +F: configs/brppt1_spi_defconfig
board/BuR/brppt1/Makefile
Diff comments   View file @ 2290fe0
  1 +#
  2 +# Makefile
  3 +#
  4 +# Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
  5 +# Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
  6 +#
  7 +# SPDX-License-Identifier: GPL-2.0+
  8 +#
  9 +
  10 +ifeq ($(CONFIG_SPL_BUILD),y)
  11 +obj-y := mux.o
  12 +endif
  13 +obj-y += ../common/common.o
  14 +obj-y += board.o
board/BuR/brppt1/board.c
Diff comments   View file @ 2290fe0
  1 +/*
  2 + * board.c
  3 + *
  4 + * Board functions for B&R BRPPT1
  5 + *
  6 + * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
  7 + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
  8 + *
  9 + * SPDX-License-Identifier: GPL-2.0+
  10 + *
  11 + */
  12 +
  13 +#include <common.h>
  14 +#include <errno.h>
  15 +#include <spl.h>
  16 +#include <asm/arch/cpu.h>
  17 +#include <asm/arch/hardware.h>
  18 +#include <asm/arch/omap.h>
  19 +#include <asm/arch/ddr_defs.h>
  20 +#include <asm/arch/clock.h>
  21 +#include <asm/arch/gpio.h>
  22 +#include <asm/arch/sys_proto.h>
  23 +#include <asm/arch/mem.h>
  24 +#include <asm/io.h>
  25 +#include <asm/emif.h>
  26 +#include <asm/gpio.h>
  27 +#include <i2c.h>
  28 +#include <power/tps65217.h>
  29 +#include "../common/bur_common.h"
  30 +#include <lcd.h>
  31 +#include <watchdog.h>
  32 +
  33 +DECLARE_GLOBAL_DATA_PTR;
  34 +
  35 +/* --------------------------------------------------------------------------*/
  36 +/* -- defines for GPIO -- */
  37 +#define REPSWITCH (0+20) /* GPIO0_20 */
  38 +
  39 +#if defined(CONFIG_SPL_BUILD)
  40 +/* TODO: check ram-timing ! */
  41 +static const struct ddr_data ddr3_data = {
  42 + .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  43 + .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  44 + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  45 + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  46 +};
  47 +
  48 +static const struct cmd_control ddr3_cmd_ctrl_data = {
  49 + .cmd0csratio = MT41K256M16HA125E_RATIO,
  50 + .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  51 +
  52 + .cmd1csratio = MT41K256M16HA125E_RATIO,
  53 + .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  54 +
  55 + .cmd2csratio = MT41K256M16HA125E_RATIO,
  56 + .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  57 +};
  58 +
  59 +static struct emif_regs ddr3_emif_reg_data = {
  60 + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  61 + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  62 + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  63 + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  64 + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  65 + .zq_config = MT41K256M16HA125E_ZQ_CFG,
  66 + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  67 +};
  68 +
  69 +static const struct ctrl_ioregs ddr3_ioregs = {
  70 + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  71 + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  72 + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  73 + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  74 + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  75 +};
  76 +
  77 +#ifdef CONFIG_SPL_OS_BOOT
  78 +/*
  79 + * called from spl_nand.c
  80 + * return 0 for loading linux, return 1 for loading u-boot
  81 + */
  82 +int spl_start_uboot(void)
  83 +{
  84 + if (0 == gpio_get_value(REPSWITCH)) {
  85 + mdelay(1000);
  86 + printf("SPL: entering u-boot instead kernel image.\n");
  87 + return 1;
  88 + }
  89 + return 0;
  90 +}
  91 +#endif /* CONFIG_SPL_OS_BOOT */
  92 +
  93 +#define OSC (V_OSCK/1000000)
  94 +static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
  95 +
  96 +void am33xx_spl_board_init(void)
  97 +{
  98 + struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
  99 + /*struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;*/
  100 + struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
  101 +
  102 + /*
  103 + * in TRM they write a reset value of 1 (=CLK_M_OSC) for the
  104 + * CLKSEL_TIMER6_CLK Register, in fact reset value is 0, so we need set
  105 + * the source of timer6 clk to CLK_M_OSC
  106 + */
  107 + writel(0x01, &cmdpll->clktimer6clk);
  108 +
  109 + /* enable additional clocks of modules which are accessed later */
  110 + u32 *const clk_domains[] = {
  111 + &cmper->lcdcclkstctrl,
  112 + 0
  113 + };
  114 +
  115 + u32 *const clk_modules_tsspecific[] = {
  116 + &cmper->lcdclkctrl,
  117 + &cmper->timer5clkctrl,
  118 + &cmper->timer6clkctrl,
  119 + 0
  120 + };
  121 + do_enable_clocks(clk_domains, clk_modules_tsspecific, 1);
  122 +
  123 + /* setup LCD-Pixel Clock */
  124 + writel(0x2, &cmdpll->clklcdcpixelclk); /* clock comes from perPLL M2 */
  125 +
  126 + /* setup I2C */
  127 + enable_i2c_pin_mux();
  128 + i2c_set_bus_num(0);
  129 + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  130 + pmicsetup(0);
  131 +
  132 + gpio_direction_output(64+29, 1); /* switch NAND_RnB to GPMC_WAIT1 */
  133 + gpio_direction_output(64+28, 1); /* switch MII2_CRS to GPMC_WAIT0 */
  134 +}
  135 +
  136 +const struct dpll_params *get_dpll_ddr_params(void)
  137 +{
  138 + return &dpll_ddr3;
  139 +}
  140 +
  141 +void sdram_init(void)
  142 +{
  143 + config_ddr(400, &ddr3_ioregs,
  144 + &ddr3_data,
  145 + &ddr3_cmd_ctrl_data,
  146 + &ddr3_emif_reg_data, 0);
  147 +}
  148 +#endif /* CONFIG_SPL_BUILD */
  149 +
  150 +/* Basic board specific setup. Pinmux has been handled already. */
  151 +int board_init(void)
  152 +{
  153 +#if defined(CONFIG_HW_WATCHDOG)
  154 + hw_watchdog_init();
  155 +#endif
  156 + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  157 +#ifdef CONFIG_NAND
  158 + gpmc_init();
  159 +#endif
  160 + return 0;
  161 +}
  162 +
  163 +#ifdef CONFIG_BOARD_LATE_INIT
  164 +int board_late_init(void)
  165 +{
  166 + if (0 == gpio_get_value(REPSWITCH)) {
  167 + lcd_position_cursor(1, 8);
  168 + lcd_puts(
  169 + "switching to network-console ... ");
  170 + setenv("bootcmd", "run netconsole");
  171 + }
  172 + return 0;
  173 +}
  174 +#endif /* CONFIG_BOARD_LATE_INIT */
board/BuR/brppt1/mux.c
Diff comments   View file @ 2290fe0
  1 +/*
  2 + * mux.c
  3 + *
  4 + * Pinmux Setting for B&R BRPPT1 Board(s)
  5 + *
  6 + * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
  7 + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
  8 + *
  9 + * SPDX-License-Identifier: GPL-2.0+
  10 + */
  11 +
  12 +#include <common.h>
  13 +#include <asm/arch/sys_proto.h>
  14 +#include <asm/arch/hardware.h>
  15 +#include <asm/arch/mux.h>
  16 +#include <asm/io.h>
  17 +#include <i2c.h>
  18 +
  19 +static struct module_pin_mux uart0_pin_mux[] = {
  20 + /* UART0_RTS */
  21 + {OFFSET(uart0_rtsn), (MODE(0) | PULLUDEN)},
  22 + /* UART0_CTS */
  23 + {OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  24 + /* UART0_RXD */
  25 + {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  26 + /* UART0_TXD */
  27 + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
  28 + {-1},
  29 +};
  30 +static struct module_pin_mux uart1_pin_mux[] = {
  31 + /* UART1_RTS as I2C2-SCL */
  32 + {OFFSET(uart1_rtsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  33 + /* UART1_CTS as I2C2-SDA */
  34 + {OFFSET(uart1_ctsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  35 + /* UART1_RXD */
  36 + {OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  37 + /* UART1_TXD */
  38 + {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
  39 + {-1},
  40 +};
  41 +#ifdef CONFIG_MMC
  42 +static struct module_pin_mux mmc1_pin_mux[] = {
  43 + {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
  44 + {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
  45 + {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */
  46 + {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */
  47 +
  48 + {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
  49 + {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
  50 + {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
  51 + {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
  52 + {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
  53 + {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
  54 + {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
  55 + {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
  56 + {-1},
  57 +};
  58 +#endif
  59 +static struct module_pin_mux i2c0_pin_mux[] = {
  60 + /* I2C_DATA */
  61 + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
  62 + /* I2C_SCLK */
  63 + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
  64 + {-1},
  65 +};
  66 +
  67 +static struct module_pin_mux spi0_pin_mux[] = {
  68 + /* SPI0_SCLK */
  69 + {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
  70 + /* SPI0_D0 */
  71 + {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
  72 + /* SPI0_D1 */
  73 + {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
  74 + /* SPI0_CS0 */
  75 + {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
  76 + {-1},
  77 +};
  78 +
  79 +static struct module_pin_mux mii1_pin_mux[] = {
  80 + {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */
  81 + {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */
  82 + {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
  83 + {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
  84 + {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
  85 + {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
  86 + {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
  87 + {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
  88 + {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
  89 + {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
  90 + {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
  91 + {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
  92 + {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
  93 + {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
  94 + {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
  95 + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
  96 + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
  97 + {-1},
  98 +};
  99 +
  100 +static struct module_pin_mux mii2_pin_mux[] = {
  101 + {OFFSET(gpmc_a0), MODE(1)}, /* MII2_TXEN */
  102 + {OFFSET(gpmc_a1), MODE(1) | RXACTIVE}, /* MII2_RXDV */
  103 + {OFFSET(gpmc_a2), MODE(1)}, /* MII2_TXD3 */
  104 + {OFFSET(gpmc_a3), MODE(1)}, /* MII2_TXD2 */
  105 + {OFFSET(gpmc_a4), MODE(1)}, /* MII2_TXD1 */
  106 + {OFFSET(gpmc_a5), MODE(1)}, /* MII2_TXD0 */
  107 + {OFFSET(gpmc_a6), MODE(1) | RXACTIVE}, /* MII2_TXCLK */
  108 + {OFFSET(gpmc_a7), MODE(1) | RXACTIVE}, /* MII2_RXCLK */
  109 + {OFFSET(gpmc_a8), MODE(1) | RXACTIVE}, /* MII2_RXD3 */
  110 + {OFFSET(gpmc_a9), MODE(1) | RXACTIVE}, /* MII2_RXD2 */
  111 + {OFFSET(gpmc_a10), MODE(1) | RXACTIVE}, /* MII2_RXD1 */
  112 + {OFFSET(gpmc_a11), MODE(1) | RXACTIVE}, /* MII2_RXD0 */
  113 + {OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */
  114 + {OFFSET(gpmc_wait0), (MODE(1) | RXACTIVE | PULLUP_EN)},
  115 + /*
  116 + * MII2_CRS is shared with
  117 + * NAND_WAIT0
  118 + */
  119 + {OFFSET(gpmc_be1n), (MODE(1) | RXACTIVE)},/* MII1_COL */
  120 + {-1},
  121 +};
  122 +#ifdef CONFIG_NAND
  123 +static struct module_pin_mux nand_pin_mux[] = {
  124 + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
  125 + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
  126 + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
  127 + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
  128 + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
  129 + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
  130 + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
  131 + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
  132 + {OFFSET(gpmc_clk), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
  133 + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
  134 + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
  135 + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
  136 + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
  137 + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
  138 + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
  139 + {-1},
  140 +};
  141 +#endif
  142 +static struct module_pin_mux gpIOs[] = {
  143 + /* GPIO0_6 (SPI0_CS1) - 3v3_PWR_nEN (Display Power Supply) */
  144 + {OFFSET(spi0_cs1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  145 + /* TIMER5 (MMC0_DAT3) - TIMER5 (Buzzer) */
  146 + {OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)},
  147 + /* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3 */
  148 + {OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN | RXACTIVE)},
  149 + /* GPIO2_28 (MMC0_DAT1) - MII_nNAND */
  150 + {OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)},
  151 + /* GPIO2_29 (MMC0_DAT0) - NAND_1n0 */
  152 + {OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)},
  153 + /* GPIO2_30 (MMC0_CLK) - nRESET (PHY) */
  154 + {OFFSET(mmc0_clk), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  155 + /* GPIO3_18 (MCASP0_ACLKR) - CPLD JTAG TDI */
  156 + {OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  157 + /* GPIO3_19 (MCASP0_FSR) - CPLD JTAG TMS */
  158 + {OFFSET(mcasp0_fsr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  159 + /* GPIO3_20 (MCASP0_AXR1) - CPLD JTAG TCK */
  160 + {OFFSET(mcasp0_axr1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  161 + /* GPIO3_21 (MCASP0_AHCLKX) - CPLD JTAG TDO */
  162 + {OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  163 + /* GPIO2_0 (GPMC_nCS3) - DCOK */
  164 + {OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
  165 + /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
  166 + {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS | RXACTIVE) },
  167 + /*
  168 + * GPIO0_7 (PWW0 OUT)
  169 + * DISPLAY_ONOFF (Backlight Enable at LVDS Versions)
  170 + */
  171 + {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | RXACTIVE)},
  172 + /* GPIO0_19 (DMA_INTR0) - DISPLAY_MODE (CPLD) */
  173 + {OFFSET(xdma_event_intr0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  174 + /* GPIO0_20 (DMA_INTR1) - REP-Switch */
  175 + {OFFSET(xdma_event_intr1), (MODE(7) | PULLUP_EN | RXACTIVE)},
  176 + /* GPIO3_14 (MCASP0_ACLKX) - frei / PP709 */
  177 + {OFFSET(mcasp0_aclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
  178 + /* GPIO3_15 (MCASP0_FSX) - PMIC_nRESET */
  179 + {OFFSET(mcasp0_fsx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
  180 + /* GPIO3_16 (MCASP0_AXR0) - ETH1_LEDY */
  181 + {OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS) },
  182 + /* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */
  183 + {OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS) },
  184 +#ifndef CONFIG_NAND
  185 + /* GPIO2_3 - NAND_OE */
  186 + {OFFSET(gpmc_oen_ren), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
  187 + /* GPIO2_4 - NAND_WEN */
  188 + {OFFSET(gpmc_wen), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
  189 + /* GPIO2_5 - NAND_BE_CLE */
  190 + {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
  191 +#endif
  192 + {-1},
  193 +};
  194 +
  195 +static struct module_pin_mux lcd_pin_mux[] = {
  196 + {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */
  197 + {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */
  198 + {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */
  199 + {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */
  200 + {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */
  201 + {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */
  202 + {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */
  203 + {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */
  204 + {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */
  205 + {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */
  206 + {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */
  207 + {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */
  208 + {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */
  209 + {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */
  210 + {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */
  211 + {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */
  212 +
  213 + {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */
  214 + {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */
  215 + {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */
  216 + {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */
  217 + {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */
  218 + {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */
  219 + {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */
  220 + {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */
  221 +
  222 + {OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */
  223 + {OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */
  224 + {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
  225 + {OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */
  226 +
  227 + {-1},
  228 +};
  229 +
  230 +void enable_uart0_pin_mux(void)
  231 +{
  232 + configure_module_pin_mux(uart0_pin_mux);
  233 +}
  234 +
  235 +void enable_i2c_pin_mux(void)
  236 +{
  237 + configure_module_pin_mux(i2c0_pin_mux);
  238 +}
  239 +
  240 +void enable_board_pin_mux(void)
  241 +{
  242 + configure_module_pin_mux(i2c0_pin_mux);
  243 + configure_module_pin_mux(mii1_pin_mux);
  244 + configure_module_pin_mux(mii2_pin_mux);
  245 +#ifdef CONFIG_NAND
  246 + configure_module_pin_mux(nand_pin_mux);
  247 +#elif defined(CONFIG_MMC)
  248 + configure_module_pin_mux(mmc1_pin_mux);
  249 +#endif
  250 + configure_module_pin_mux(spi0_pin_mux);
  251 + configure_module_pin_mux(lcd_pin_mux);
  252 + configure_module_pin_mux(uart1_pin_mux);
  253 + configure_module_pin_mux(gpIOs);
  254 +}
board/BuR/tseries/Kconfig
View file @ 2290fe0
1   -if TARGET_TSERIES
2   -
3   -config SYS_BOARD
4   - default "tseries"
5   -
6   -config SYS_VENDOR
7   - default "BuR"
8   -
9   -config SYS_SOC
10   - default "am33xx"
11   -
12   -config SYS_CONFIG_NAME
13   - default "tseries"
14   -
15   -endif
board/BuR/tseries/MAINTAINERS
View file @ 2290fe0
1   -TSERIES BOARD
2   -M: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
3   -S: Maintained
4   -F: board/BuR/tseries/
5   -F: include/configs/tseries.h
6   -F: configs/tseries_mmc_defconfig
7   -F: configs/tseries_nand_defconfig
8   -F: configs/tseries_spi_defconfig
board/BuR/tseries/Makefile
View file @ 2290fe0
1   -#
2   -# Makefile
3   -#
4   -# Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
5   -# Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
6   -#
7   -# SPDX-License-Identifier: GPL-2.0+
8   -#
9   -
10   -ifeq ($(CONFIG_SPL_BUILD),y)
11   -obj-y := mux.o
12   -endif
13   -obj-y += ../common/common.o
14   -obj-y += board.o
board/BuR/tseries/board.c
View file @ 2290fe0
1   -/*
2   - * board.c
3   - *
4   - * Board functions for B&R LEIT Board
5   - *
6   - * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
7   - * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
8   - *
9   - * SPDX-License-Identifier: GPL-2.0+
10   - *
11   - */
12   -
13   -#include <common.h>
14   -#include <errno.h>
15   -#include <spl.h>
16   -#include <asm/arch/cpu.h>
17   -#include <asm/arch/hardware.h>
18   -#include <asm/arch/omap.h>
19   -#include <asm/arch/ddr_defs.h>
20   -#include <asm/arch/clock.h>
21   -#include <asm/arch/gpio.h>
22   -#include <asm/arch/sys_proto.h>
23   -#include <asm/arch/mem.h>
24   -#include <asm/io.h>
25   -#include <asm/emif.h>
26   -#include <asm/gpio.h>
27   -#include <i2c.h>
28   -#include <power/tps65217.h>
29   -#include "../common/bur_common.h"
30   -#include <lcd.h>
31   -#include <watchdog.h>
32   -
33   -DECLARE_GLOBAL_DATA_PTR;
34   -
35   -/* --------------------------------------------------------------------------*/
36   -/* -- defines for GPIO -- */
37   -#define REPSWITCH (0+20) /* GPIO0_20 */
38   -
39   -#if defined(CONFIG_SPL_BUILD)
40   -/* TODO: check ram-timing ! */
41   -static const struct ddr_data ddr3_data = {
42   - .datardsratio0 = MT41K256M16HA125E_RD_DQS,
43   - .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
44   - .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
45   - .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
46   -};
47   -
48   -static const struct cmd_control ddr3_cmd_ctrl_data = {
49   - .cmd0csratio = MT41K256M16HA125E_RATIO,
50   - .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
51   -
52   - .cmd1csratio = MT41K256M16HA125E_RATIO,
53   - .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
54   -
55   - .cmd2csratio = MT41K256M16HA125E_RATIO,
56   - .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
57   -};
58   -
59   -static struct emif_regs ddr3_emif_reg_data = {
60   - .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
61   - .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
62   - .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
63   - .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
64   - .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
65   - .zq_config = MT41K256M16HA125E_ZQ_CFG,
66   - .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
67   -};
68   -
69   -static const struct ctrl_ioregs ddr3_ioregs = {
70   - .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
71   - .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
72   - .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
73   - .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
74   - .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
75   -};
76   -
77   -#ifdef CONFIG_SPL_OS_BOOT
78   -/*
79   - * called from spl_nand.c
80   - * return 0 for loading linux, return 1 for loading u-boot
81   - */
82   -int spl_start_uboot(void)
83   -{
84   - if (0 == gpio_get_value(REPSWITCH)) {
85   - mdelay(1000);
86   - printf("SPL: entering u-boot instead kernel image.\n");
87   - return 1;
88   - }
89   - return 0;
90   -}
91   -#endif /* CONFIG_SPL_OS_BOOT */
92   -
93   -#define OSC (V_OSCK/1000000)
94   -static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
95   -
96   -void am33xx_spl_board_init(void)
97   -{
98   - struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
99   - /*struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;*/
100   - struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
101   -
102   - /*
103   - * in TRM they write a reset value of 1 (=CLK_M_OSC) for the
104   - * CLKSEL_TIMER6_CLK Register, in fact reset value is 0, so we need set
105   - * the source of timer6 clk to CLK_M_OSC
106   - */
107   - writel(0x01, &cmdpll->clktimer6clk);
108   -
109   - /* enable additional clocks of modules which are accessed later */
110   - u32 *const clk_domains[] = {
111   - &cmper->lcdcclkstctrl,
112   - 0
113   - };
114   -
115   - u32 *const clk_modules_tsspecific[] = {
116   - &cmper->lcdclkctrl,
117   - &cmper->timer5clkctrl,
118   - &cmper->timer6clkctrl,
119   - 0
120   - };
121   - do_enable_clocks(clk_domains, clk_modules_tsspecific, 1);
122   -
123   - /* setup LCD-Pixel Clock */
124   - writel(0x2, &cmdpll->clklcdcpixelclk); /* clock comes from perPLL M2 */
125   -
126   - /* setup I2C */
127   - enable_i2c_pin_mux();
128   - i2c_set_bus_num(0);
129   - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
130   - pmicsetup(0);
131   -
132   - gpio_direction_output(64+29, 1); /* switch NAND_RnB to GPMC_WAIT1 */
133   - gpio_direction_output(64+28, 1); /* switch MII2_CRS to GPMC_WAIT0 */
134   -}
135   -
136   -const struct dpll_params *get_dpll_ddr_params(void)
137   -{
138   - return &dpll_ddr3;
139   -}
140   -
141   -void sdram_init(void)
142   -{
143   - config_ddr(400, &ddr3_ioregs,
144   - &ddr3_data,
145   - &ddr3_cmd_ctrl_data,
146   - &ddr3_emif_reg_data, 0);
147   -}
148   -#endif /* CONFIG_SPL_BUILD */
149   -
150   -/* Basic board specific setup. Pinmux has been handled already. */
151   -int board_init(void)
152   -{
153   -#if defined(CONFIG_HW_WATCHDOG)
154   - hw_watchdog_init();
155   -#endif
156   - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
157   -#ifdef CONFIG_NAND
158   - gpmc_init();
159   -#endif
160   - return 0;
161   -}
162   -
163   -#ifdef CONFIG_BOARD_LATE_INIT
164   -int board_late_init(void)
165   -{
166   - if (0 == gpio_get_value(REPSWITCH)) {
167   - lcd_position_cursor(1, 8);
168   - lcd_puts(
169   - "switching to network-console ... ");
170   - setenv("bootcmd", "run netconsole");
171   - }
172   - return 0;
173   -}
174   -#endif /* CONFIG_BOARD_LATE_INIT */
board/BuR/tseries/mux.c
View file @ 2290fe0
1   -/*
2   - * mux.c
3   - *
4   - * Pinmux Setting for B&R LEIT Board(s)
5   - *
6   - * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
7   - * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
8   - *
9   - * SPDX-License-Identifier: GPL-2.0+
10   - */
11   -
12   -#include <common.h>
13   -#include <asm/arch/sys_proto.h>
14   -#include <asm/arch/hardware.h>
15   -#include <asm/arch/mux.h>
16   -#include <asm/io.h>
17   -#include <i2c.h>
18   -
19   -static struct module_pin_mux uart0_pin_mux[] = {
20   - /* UART0_RTS */
21   - {OFFSET(uart0_rtsn), (MODE(0) | PULLUDEN)},
22   - /* UART0_CTS */
23   - {OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
24   - /* UART0_RXD */
25   - {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
26   - /* UART0_TXD */
27   - {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
28   - {-1},
29   -};
30   -static struct module_pin_mux uart1_pin_mux[] = {
31   - /* UART1_RTS as I2C2-SCL */
32   - {OFFSET(uart1_rtsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
33   - /* UART1_CTS as I2C2-SDA */
34   - {OFFSET(uart1_ctsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
35   - /* UART1_RXD */
36   - {OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
37   - /* UART1_TXD */
38   - {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
39   - {-1},
40   -};
41   -#ifdef CONFIG_MMC
42   -static struct module_pin_mux mmc1_pin_mux[] = {
43   - {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
44   - {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
45   - {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */
46   - {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */
47   -
48   - {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
49   - {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
50   - {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
51   - {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
52   - {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
53   - {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
54   - {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
55   - {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
56   - {-1},
57   -};
58   -#endif
59   -static struct module_pin_mux i2c0_pin_mux[] = {
60   - /* I2C_DATA */
61   - {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
62   - /* I2C_SCLK */
63   - {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
64   - {-1},
65   -};
66   -
67   -static struct module_pin_mux spi0_pin_mux[] = {
68   - /* SPI0_SCLK */
69   - {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
70   - /* SPI0_D0 */
71   - {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
72   - /* SPI0_D1 */
73   - {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
74   - /* SPI0_CS0 */
75   - {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
76   - {-1},
77   -};
78   -
79   -static struct module_pin_mux mii1_pin_mux[] = {
80   - {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */
81   - {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */
82   - {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
83   - {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
84   - {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
85   - {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
86   - {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
87   - {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
88   - {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
89   - {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
90   - {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
91   - {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
92   - {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
93   - {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
94   - {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
95   - {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
96   - {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
97   - {-1},
98   -};
99   -
100   -static struct module_pin_mux mii2_pin_mux[] = {
101   - {OFFSET(gpmc_a0), MODE(1)}, /* MII2_TXEN */
102   - {OFFSET(gpmc_a1), MODE(1) | RXACTIVE}, /* MII2_RXDV */
103   - {OFFSET(gpmc_a2), MODE(1)}, /* MII2_TXD3 */
104   - {OFFSET(gpmc_a3), MODE(1)}, /* MII2_TXD2 */
105   - {OFFSET(gpmc_a4), MODE(1)}, /* MII2_TXD1 */
106   - {OFFSET(gpmc_a5), MODE(1)}, /* MII2_TXD0 */
107   - {OFFSET(gpmc_a6), MODE(1) | RXACTIVE}, /* MII2_TXCLK */
108   - {OFFSET(gpmc_a7), MODE(1) | RXACTIVE}, /* MII2_RXCLK */
109   - {OFFSET(gpmc_a8), MODE(1) | RXACTIVE}, /* MII2_RXD3 */
110   - {OFFSET(gpmc_a9), MODE(1) | RXACTIVE}, /* MII2_RXD2 */
111   - {OFFSET(gpmc_a10), MODE(1) | RXACTIVE}, /* MII2_RXD1 */
112   - {OFFSET(gpmc_a11), MODE(1) | RXACTIVE}, /* MII2_RXD0 */
113   - {OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */
114   - {OFFSET(gpmc_wait0), (MODE(1) | RXACTIVE | PULLUP_EN)},
115   - /*
116   - * MII2_CRS is shared with
117   - * NAND_WAIT0
118   - */
119   - {OFFSET(gpmc_be1n), (MODE(1) | RXACTIVE)},/* MII1_COL */
120   - {-1},
121   -};
122   -#ifdef CONFIG_NAND
123   -static struct module_pin_mux nand_pin_mux[] = {
124   - {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
125   - {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
126   - {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
127   - {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
128   - {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
129   - {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
130   - {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
131   - {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
132   - {OFFSET(gpmc_clk), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
133   - {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
134   - {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
135   - {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
136   - {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
137   - {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
138   - {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
139   - {-1},
140   -};
141   -#endif
142   -static struct module_pin_mux gpIOs[] = {
143   - /* GPIO0_6 (SPI0_CS1) - 3v3_PWR_nEN (Display Power Supply) */
144   - {OFFSET(spi0_cs1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
145   - /* TIMER5 (MMC0_DAT3) - TIMER5 (Buzzer) */
146   - {OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)},
147   - /* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3 */
148   - {OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN | RXACTIVE)},
149   - /* GPIO2_28 (MMC0_DAT1) - MII_nNAND */
150   - {OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)},
151   - /* GPIO2_29 (MMC0_DAT0) - NAND_1n0 */
152   - {OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)},
153   - /* GPIO2_30 (MMC0_CLK) - nRESET (PHY) */
154   - {OFFSET(mmc0_clk), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
155   - /* GPIO3_18 (MCASP0_ACLKR) - CPLD JTAG TDI */
156   - {OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
157   - /* GPIO3_19 (MCASP0_FSR) - CPLD JTAG TMS */
158   - {OFFSET(mcasp0_fsr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
159   - /* GPIO3_20 (MCASP0_AXR1) - CPLD JTAG TCK */
160   - {OFFSET(mcasp0_axr1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
161   - /* GPIO3_21 (MCASP0_AHCLKX) - CPLD JTAG TDO */
162   - {OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
163   - /* GPIO2_0 (GPMC_nCS3) - DCOK */
164   - {OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
165   - /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
166   - {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS | RXACTIVE) },
167   - /*
168   - * GPIO0_7 (PWW0 OUT)
169   - * DISPLAY_ONOFF (Backlight Enable at LVDS Versions)
170   - */
171   - {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | RXACTIVE)},
172   - /* GPIO0_19 (DMA_INTR0) - DISPLAY_MODE (CPLD) */
173   - {OFFSET(xdma_event_intr0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
174   - /* GPIO0_20 (DMA_INTR1) - REP-Switch */
175   - {OFFSET(xdma_event_intr1), (MODE(7) | PULLUP_EN | RXACTIVE)},
176   - /* GPIO3_14 (MCASP0_ACLKX) - frei / PP709 */
177   - {OFFSET(mcasp0_aclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
178   - /* GPIO3_15 (MCASP0_FSX) - PMIC_nRESET */
179   - {OFFSET(mcasp0_fsx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
180   - /* GPIO3_16 (MCASP0_AXR0) - ETH1_LEDY */
181   - {OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS) },
182   - /* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */
183   - {OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS) },
184   -#ifndef CONFIG_NAND
185   - /* GPIO2_3 - NAND_OE */
186   - {OFFSET(gpmc_oen_ren), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
187   - /* GPIO2_4 - NAND_WEN */
188   - {OFFSET(gpmc_wen), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
189   - /* GPIO2_5 - NAND_BE_CLE */
190   - {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
191   -#endif
192   - {-1},
193   -};
194   -
195   -static struct module_pin_mux lcd_pin_mux[] = {
196   - {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */
197   - {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */
198   - {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */
199   - {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */
200   - {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */
201   - {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */
202   - {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */
203   - {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */
204   - {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */
205   - {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */
206   - {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */
207   - {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */
208   - {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */
209   - {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */
210   - {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */
211   - {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */
212   -
213   - {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */
214   - {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */
215   - {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */
216   - {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */
217   - {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */
218   - {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */
219   - {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */
220   - {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */
221   -
222   - {OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */
223   - {OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */
224   - {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
225   - {OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */
226   -
227   - {-1},
228   -};
229   -
230   -void enable_uart0_pin_mux(void)
231   -{
232   - configure_module_pin_mux(uart0_pin_mux);
233   -}
234   -
235   -void enable_i2c_pin_mux(void)
236   -{
237   - configure_module_pin_mux(i2c0_pin_mux);
238   -}
239   -
240   -void enable_board_pin_mux(void)
241   -{
242   - configure_module_pin_mux(i2c0_pin_mux);
243   - configure_module_pin_mux(mii1_pin_mux);
244   - configure_module_pin_mux(mii2_pin_mux);
245   -#ifdef CONFIG_NAND
246   - configure_module_pin_mux(nand_pin_mux);
247   -#elif defined(CONFIG_MMC)
248   - configure_module_pin_mux(mmc1_pin_mux);
249   -#endif
250   - configure_module_pin_mux(spi0_pin_mux);
251   - configure_module_pin_mux(lcd_pin_mux);
252   - configure_module_pin_mux(uart1_pin_mux);
253   - configure_module_pin_mux(gpIOs);
254   -}
configs/brppt1_mmc_defconfig
Diff comments   View file @ 2290fe0
  1 +CONFIG_ARM=y
  2 +CONFIG_TARGET_BRPPT1=y
  3 +CONFIG_SPL=y
  4 +CONFIG_OF_BOARD_SETUP=y
  5 +CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT"
  6 +CONFIG_BOOTDELAY=0
  7 +CONFIG_HUSH_PARSER=y
  8 +CONFIG_CMD_BOOTZ=y
  9 +# CONFIG_CMD_IMI is not set
  10 +# CONFIG_CMD_IMLS is not set
  11 +# CONFIG_CMD_XIMG is not set
  12 +# CONFIG_CMD_EDITENV is not set
  13 +# CONFIG_CMD_CRC32 is not set
  14 +# CONFIG_CMD_LOADB is not set
  15 +# CONFIG_CMD_LOADS is not set
  16 +# CONFIG_CMD_FLASH is not set
  17 +CONFIG_CMD_MMC=y
  18 +CONFIG_CMD_I2C=y
  19 +CONFIG_CMD_USB=y
  20 +# CONFIG_CMD_FPGA is not set
  21 +CONFIG_CMD_GPIO=y
  22 +# CONFIG_CMD_ITEST is not set
  23 +# CONFIG_CMD_SETEXPR is not set
  24 +CONFIG_CMD_DHCP=y
  25 +# CONFIG_CMD_NFS is not set
  26 +CONFIG_CMD_PING=y
  27 +CONFIG_CMD_TIME=y
  28 +CONFIG_CMD_EXT4=y
  29 +CONFIG_CMD_EXT4_WRITE=y
  30 +CONFIG_CMD_FAT=y
  31 +CONFIG_CMD_FS_GENERIC=y
  32 +CONFIG_NETCONSOLE=y
  33 +CONFIG_SYS_NS16550=y
  34 +CONFIG_USB=y
  35 +CONFIG_USB_MUSB_HOST=y
  36 +CONFIG_USB_STORAGE=y
  37 +CONFIG_OF_LIBFDT=y
configs/brppt1_nand_defconfig
Diff comments   View file @ 2290fe0
  1 +CONFIG_ARM=y
  2 +CONFIG_TARGET_BRPPT1=y
  3 +CONFIG_SPL=y
  4 +CONFIG_OF_BOARD_SETUP=y
  5 +CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
  6 +CONFIG_BOOTDELAY=0
  7 +CONFIG_HUSH_PARSER=y
  8 +CONFIG_CMD_BOOTZ=y
  9 +# CONFIG_CMD_IMI is not set
  10 +# CONFIG_CMD_IMLS is not set
  11 +# CONFIG_CMD_XIMG is not set
  12 +# CONFIG_CMD_EDITENV is not set
  13 +# CONFIG_CMD_CRC32 is not set
  14 +# CONFIG_CMD_LOADB is not set
  15 +# CONFIG_CMD_LOADS is not set
  16 +# CONFIG_CMD_FLASH is not set
  17 +CONFIG_CMD_NAND=y
  18 +CONFIG_CMD_I2C=y
  19 +CONFIG_CMD_USB=y
  20 +# CONFIG_CMD_FPGA is not set
  21 +CONFIG_CMD_GPIO=y
  22 +# CONFIG_CMD_ITEST is not set
  23 +# CONFIG_CMD_SETEXPR is not set
  24 +CONFIG_CMD_DHCP=y
  25 +# CONFIG_CMD_NFS is not set
  26 +CONFIG_CMD_PING=y
  27 +CONFIG_CMD_TIME=y
  28 +CONFIG_CMD_EXT4=y
  29 +CONFIG_CMD_EXT4_WRITE=y
  30 +CONFIG_CMD_FAT=y
  31 +CONFIG_CMD_FS_GENERIC=y
  32 +CONFIG_NETCONSOLE=y
  33 +CONFIG_SYS_NS16550=y
  34 +CONFIG_USB=y
  35 +CONFIG_USB_MUSB_HOST=y
  36 +CONFIG_USB_STORAGE=y
  37 +CONFIG_OF_LIBFDT=y
configs/brppt1_spi_defconfig
Diff comments   View file @ 2290fe0
  1 +CONFIG_ARM=y
  2 +CONFIG_TARGET_BRPPT1=y
  3 +CONFIG_SPL=y
  4 +CONFIG_OF_BOARD_SETUP=y
  5 +CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT"
  6 +CONFIG_BOOTDELAY=0
  7 +CONFIG_HUSH_PARSER=y
  8 +CONFIG_CMD_BOOTZ=y
  9 +# CONFIG_CMD_IMI is not set
  10 +# CONFIG_CMD_IMLS is not set
  11 +# CONFIG_CMD_XIMG is not set
  12 +# CONFIG_CMD_EDITENV is not set
  13 +# CONFIG_CMD_CRC32 is not set
  14 +# CONFIG_CMD_LOADB is not set
  15 +# CONFIG_CMD_LOADS is not set
  16 +# CONFIG_CMD_FLASH is not set
  17 +CONFIG_CMD_MMC=y
  18 +CONFIG_CMD_SF=y
  19 +CONFIG_CMD_SPI=y
  20 +CONFIG_CMD_I2C=y
  21 +CONFIG_CMD_USB=y
  22 +# CONFIG_CMD_FPGA is not set
  23 +CONFIG_CMD_GPIO=y
  24 +# CONFIG_CMD_ITEST is not set
  25 +# CONFIG_CMD_SETEXPR is not set
  26 +CONFIG_CMD_DHCP=y
  27 +# CONFIG_CMD_NFS is not set
  28 +CONFIG_CMD_PING=y
  29 +CONFIG_CMD_TIME=y
  30 +CONFIG_CMD_EXT4=y
  31 +CONFIG_CMD_EXT4_WRITE=y
  32 +CONFIG_CMD_FAT=y
  33 +CONFIG_CMD_FS_GENERIC=y
  34 +CONFIG_NETCONSOLE=y
  35 +CONFIG_SPI_FLASH=y
  36 +CONFIG_SPI_FLASH_STMICRO=y
  37 +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  38 +CONFIG_SYS_NS16550=y
  39 +CONFIG_USB=y
  40 +CONFIG_USB_MUSB_HOST=y
  41 +CONFIG_USB_STORAGE=y
  42 +CONFIG_OF_LIBFDT=y
configs/tseries_mmc_defconfig
View file @ 2290fe0
1   -CONFIG_ARM=y
2   -CONFIG_TARGET_TSERIES=y
3   -CONFIG_SPL=y
4   -CONFIG_OF_BOARD_SETUP=y
5   -CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT"
6   -CONFIG_BOOTDELAY=0
7   -CONFIG_HUSH_PARSER=y
8   -CONFIG_CMD_BOOTZ=y
9   -# CONFIG_CMD_IMI is not set
10   -# CONFIG_CMD_IMLS is not set
11   -# CONFIG_CMD_XIMG is not set
12   -# CONFIG_CMD_EDITENV is not set
13   -# CONFIG_CMD_CRC32 is not set
14   -# CONFIG_CMD_LOADB is not set
15   -# CONFIG_CMD_LOADS is not set
16   -# CONFIG_CMD_FLASH is not set
17   -CONFIG_CMD_MMC=y
18   -CONFIG_CMD_I2C=y
19   -CONFIG_CMD_USB=y
20   -# CONFIG_CMD_FPGA is not set
21   -CONFIG_CMD_GPIO=y
22   -# CONFIG_CMD_ITEST is not set
23   -# CONFIG_CMD_SETEXPR is not set
24   -CONFIG_CMD_DHCP=y
25   -# CONFIG_CMD_NFS is not set
26   -CONFIG_CMD_PING=y
27   -CONFIG_CMD_TIME=y
28   -CONFIG_CMD_EXT4=y
29   -CONFIG_CMD_EXT4_WRITE=y
30   -CONFIG_CMD_FAT=y
31   -CONFIG_CMD_FS_GENERIC=y
32   -CONFIG_NETCONSOLE=y
33   -CONFIG_SYS_NS16550=y
34   -CONFIG_USB=y
35   -CONFIG_USB_MUSB_HOST=y
36   -CONFIG_USB_STORAGE=y
37   -CONFIG_OF_LIBFDT=y
configs/tseries_nand_defconfig
View file @ 2290fe0
1   -CONFIG_ARM=y
2   -CONFIG_TARGET_TSERIES=y
3   -CONFIG_SPL=y
4   -CONFIG_OF_BOARD_SETUP=y
5   -CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
6   -CONFIG_BOOTDELAY=0
7   -CONFIG_HUSH_PARSER=y
8   -CONFIG_CMD_BOOTZ=y
9   -# CONFIG_CMD_IMI is not set
10   -# CONFIG_CMD_IMLS is not set
11   -# CONFIG_CMD_XIMG is not set
12   -# CONFIG_CMD_EDITENV is not set
13   -# CONFIG_CMD_CRC32 is not set
14   -# CONFIG_CMD_LOADB is not set
15   -# CONFIG_CMD_LOADS is not set
16   -# CONFIG_CMD_FLASH is not set
17   -CONFIG_CMD_NAND=y
18   -CONFIG_CMD_I2C=y
19   -CONFIG_CMD_USB=y
20   -# CONFIG_CMD_FPGA is not set
21   -CONFIG_CMD_GPIO=y
22   -# CONFIG_CMD_ITEST is not set
23   -# CONFIG_CMD_SETEXPR is not set
24   -CONFIG_CMD_DHCP=y
25   -# CONFIG_CMD_NFS is not set
26   -CONFIG_CMD_PING=y
27   -CONFIG_CMD_TIME=y
28   -CONFIG_CMD_EXT4=y
29   -CONFIG_CMD_EXT4_WRITE=y
30   -CONFIG_CMD_FAT=y
31   -CONFIG_CMD_FS_GENERIC=y
32   -CONFIG_NETCONSOLE=y
33   -CONFIG_SYS_NS16550=y
34   -CONFIG_USB=y
35   -CONFIG_USB_MUSB_HOST=y
36   -CONFIG_USB_STORAGE=y
37   -CONFIG_OF_LIBFDT=y
configs/tseries_spi_defconfig
View file @ 2290fe0
1   -CONFIG_ARM=y
2   -CONFIG_TARGET_TSERIES=y
3   -CONFIG_SPL=y
4   -CONFIG_OF_BOARD_SETUP=y
5   -CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT"
6   -CONFIG_BOOTDELAY=0
7   -CONFIG_HUSH_PARSER=y
8   -CONFIG_CMD_BOOTZ=y
9   -# CONFIG_CMD_IMI is not set
10   -# CONFIG_CMD_IMLS is not set
11   -# CONFIG_CMD_XIMG is not set
12   -# CONFIG_CMD_EDITENV is not set
13   -# CONFIG_CMD_CRC32 is not set
14   -# CONFIG_CMD_LOADB is not set
15   -# CONFIG_CMD_LOADS is not set
16   -# CONFIG_CMD_FLASH is not set
17   -CONFIG_CMD_MMC=y
18   -CONFIG_CMD_SF=y
19   -CONFIG_CMD_SPI=y
20   -CONFIG_CMD_I2C=y
21   -CONFIG_CMD_USB=y
22   -# CONFIG_CMD_FPGA is not set
23   -CONFIG_CMD_GPIO=y
24   -# CONFIG_CMD_ITEST is not set
25   -# CONFIG_CMD_SETEXPR is not set
26   -CONFIG_CMD_DHCP=y
27   -# CONFIG_CMD_NFS is not set
28   -CONFIG_CMD_PING=y
29   -CONFIG_CMD_TIME=y
30   -CONFIG_CMD_EXT4=y
31   -CONFIG_CMD_EXT4_WRITE=y
32   -CONFIG_CMD_FAT=y
33   -CONFIG_CMD_FS_GENERIC=y
34   -CONFIG_NETCONSOLE=y
35   -CONFIG_SPI_FLASH=y
36   -CONFIG_SPI_FLASH_STMICRO=y
37   -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
38   -CONFIG_SYS_NS16550=y
39   -CONFIG_USB=y
40   -CONFIG_USB_MUSB_HOST=y
41   -CONFIG_USB_STORAGE=y
42   -CONFIG_OF_LIBFDT=y
include/configs/brppt1.h
Diff comments   View file @ 2290fe0
  1 +/*
  2 + * brtpp1.h
  3 + *
  4 + * specific parts for B&R T-Series Motherboard
  5 + *
  6 + * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> -
  7 + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
  8 + *
  9 + * SPDX-License-Identifier: GPL-2.0+
  10 + */
  11 +
  12 +#ifndef __CONFIG_BRPPT1_H__
  13 +#define __CONFIG_BRPPT1_H__
  14 +
  15 +#include <configs/bur_cfg_common.h>
  16 +#include <configs/bur_am335x_common.h>
  17 +/* ------------------------------------------------------------------------- */
  18 +#define CONFIG_AM335X_LCD
  19 +#define CONFIG_LCD
  20 +#define CONFIG_LCD_ROTATION
  21 +#define CONFIG_LCD_DT_SIMPLEFB
  22 +#define CONFIG_SYS_WHITE_ON_BLACK
  23 +#define LCD_BPP LCD_COLOR32
  24 +
  25 +#define CONFIG_HW_WATCHDOG
  26 +#define CONFIG_OMAP_WATCHDOG
  27 +#define CONFIG_SPL_WATCHDOG_SUPPORT
  28 +
  29 +#define CONFIG_SPL_GPIO_SUPPORT
  30 +/* Bootcount using the RTC block */
  31 +#define CONFIG_SYS_BOOTCOUNT_ADDR 0x44E3E000
  32 +#define CONFIG_BOOTCOUNT_LIMIT
  33 +#define CONFIG_BOOTCOUNT_AM33XX
  34 +
  35 +/* memory */
  36 +#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024)
  37 +
  38 +/* Clock Defines */
  39 +#define V_OSCK 26000000 /* Clock output from T2 */
  40 +#define V_SCLK (V_OSCK)
  41 +
  42 +#define CONFIG_POWER_TPS65217
  43 +
  44 +/* Support both device trees and ATAGs. */
  45 +#define CONFIG_USE_FDT /* use fdt within board code */
  46 +#define CONFIG_CMDLINE_TAG
  47 +#define CONFIG_SETUP_MEMORY_TAGS
  48 +#define CONFIG_INITRD_TAG
  49 +/*#define CONFIG_MACH_TYPE 3589*/
  50 +#define CONFIG_MACH_TYPE 0xFFFFFFFF /* TODO: check with kernel*/
  51 +
  52 +/* MMC/SD IP block */
  53 +#if defined(CONFIG_EMMC_BOOT)
  54 + #define CONFIG_MMC
  55 + #define CONFIG_GENERIC_MMC
  56 + #define CONFIG_OMAP_HSMMC
  57 + #define CONFIG_SUPPORT_EMMC_BOOT
  58 +/* RAW SD card / eMMC locations. */
  59 + #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /*addr. 0x60000 */
  60 + #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
  61 + #define CONFIG_SPL_MMC_SUPPORT
  62 +#endif /* CONFIG_EMMC_BOOT */
  63 +
  64 +/*
  65 + * When we have SPI or NAND flash we expect to be making use of mtdparts,
  66 + * both for ease of use in U-Boot and for passing information on to
  67 + * the Linux kernel.
  68 + */
  69 +#if defined(CONFIG_SPI_BOOT) || defined(CONFIG_NAND)
  70 +#define CONFIG_MTD_DEVICE /* Required for mtdparts */
  71 +#define CONFIG_CMD_MTDPARTS
  72 +#endif /* CONFIG_SPI_BOOT, ... */
  73 +
  74 +#undef CONFIG_SPL_OS_BOOT
  75 +#ifdef CONFIG_SPL_OS_BOOT
  76 +#define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000
  77 +
  78 +/* RAW SD card / eMMC */
  79 +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */
  80 +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */
  81 +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
  82 +
  83 +/* NAND */
  84 +#ifdef CONFIG_NAND
  85 +#define CONFIG_CMD_SPL_NAND_OFS 0x080000 /* end of u-boot */
  86 +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x140000
  87 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
  88 +#endif /* CONFIG_NAND */
  89 +#endif /* CONFIG_SPL_OS_BOOT */
  90 +
  91 +#ifdef CONFIG_NAND
  92 +#define CONFIG_SPL_NAND_AM33XX_BCH /* OMAP4 and later ELM support */
  93 +#define CONFIG_SPL_NAND_SUPPORT
  94 +#define CONFIG_SPL_NAND_BASE
  95 +#define CONFIG_SPL_NAND_DRIVERS
  96 +#define CONFIG_SPL_NAND_ECC
  97 +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  98 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
  99 +#endif /* CONFIG_NAND */
  100 +
  101 +/* Always 64 KiB env size */
  102 +#define CONFIG_ENV_SIZE (64 << 10)
  103 +
  104 +#ifdef CONFIG_NAND
  105 +#define NANDARGS \
  106 + "mtdids=" MTDIDS_DEFAULT "\0" \
  107 + "mtdparts=" MTDPARTS_DEFAULT "\0" \
  108 + "nandargs=setenv bootargs console=${console} " \
  109 + "${optargs} " \
  110 + "${optargs_rot} " \
  111 + "root=mtd6 " \
  112 + "rootfstype=jffs2\0" \
  113 + "kernelsize=0x400000\0" \
  114 + "nandboot=echo booting from nand ...; " \
  115 + "run nandargs; " \
  116 + "nand read ${loadaddr} kernel ${kernelsize}; " \
  117 + "bootz ${loadaddr} - ${dtbaddr}\0" \
  118 + "defboot=run nandboot\0" \
  119 + "bootlimit=1\0" \
  120 + "simplefb=1\0 " \
  121 + "altbootcmd=run usbscript\0"
  122 +#else
  123 +#define NANDARGS ""
  124 +#endif /* CONFIG_NAND */
  125 +
  126 +#ifdef CONFIG_MMC
  127 +#define MMCARGS \
  128 +"dtbdev=mmc\0" \
  129 +"dtbpart=0:1\0" \
  130 +"mmcroot0=setenv bootargs ${optargs_rot} ${optargs} console=${console}\0" \
  131 +"mmcroot1=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \
  132 + "root=/dev/mmcblk0p2 rootfstype=ext4\0" \
  133 +"mmcboot0=echo booting Updatesystem from mmc (ext4-fs) ...; " \
  134 + "setenv simplefb 1; " \
  135 + "ext4load mmc 0:1 ${loadaddr} /${kernel}; " \
  136 + "ext4load mmc 0:1 ${ramaddr} /${ramdisk}; " \
  137 + "run mmcroot0; bootz ${loadaddr} ${ramaddr} ${dtbaddr};\0" \
  138 +"mmcboot1=echo booting PPT-OS from mmc (ext4-fs) ...; " \
  139 + "setenv simplefb 0; " \
  140 + "ext4load mmc 0:2 ${loadaddr} /boot/${kernel}; " \
  141 + "run mmcroot1; bootz ${loadaddr} - ${dtbaddr};\0" \
  142 +"defboot=ext4load mmc 0:2 ${loadaddr} /boot/PPTImage.md5 && run mmcboot1; " \
  143 + "ext4load mmc 0:1 ${dtbaddr} /$dtb && run mmcboot0; " \
  144 + "run ramboot; run usbscript;\0" \
  145 +"bootlimit=1\0" \
  146 +"altbootcmd=run mmcboot0;\0" \
  147 +"upduboot=dhcp; " \
  148 + "tftp ${loadaddr} MLO && mmc write ${loadaddr} 100 100; " \
  149 + "tftp ${loadaddr} u-boot.img && mmc write ${loadaddr} 300 400;\0"
  150 +#else
  151 +#define MMCARGS ""
  152 +#endif /* CONFIG_MMC */
  153 +
  154 +#ifndef CONFIG_SPL_BUILD
  155 +#define CONFIG_EXTRA_ENV_SETTINGS \
  156 +BUR_COMMON_ENV \
  157 +"verify=no\0" \
  158 +"autoload=0\0" \
  159 +"dtb=bur-ppt-ts30.dtb\0" \
  160 +"dtbaddr=0x80100000\0" \
  161 +"loadaddr=0x80200000\0" \
  162 +"ramaddr=0x80A00000\0" \
  163 +"kernel=zImage\0" \
  164 +"ramdisk=rootfs.cpio.uboot\0" \
  165 +"console=ttyO0,115200n8\0" \
  166 +"optargs=consoleblank=0 quiet panic=2\0" \
  167 +"nfsroot=/tftpboot/tseries/rootfs-small\0" \
  168 +"nfsopts=nolock\0" \
  169 +"ramargs=setenv bootargs ${optargs} console=${console} root=/dev/ram0\0" \
  170 +"netargs=setenv bootargs console=${console} " \
  171 + "${optargs} " \
  172 + "root=/dev/nfs " \
  173 + "nfsroot=${serverip}:${nfsroot},${nfsopts} rw " \
  174 + "ip=dhcp\0" \
  175 +"netboot=echo Booting from network ...; " \
  176 + "dhcp; " \
  177 + "tftp ${loadaddr} ${kernel}; " \
  178 + "tftp ${dtbaddr} ${dtb}; " \
  179 + "run netargs; " \
  180 + "bootz ${loadaddr} - ${dtbaddr}\0" \
  181 +"ramboot=echo Booting from network into RAM ...; "\
  182 + "if dhcp; then; " \
  183 + "tftp ${loadaddr} ${kernel}; " \
  184 + "tftp ${ramaddr} ${ramdisk}; " \
  185 + "if ext4load ${dtbdev} ${dtbpart} ${dtbaddr} /${dtb}; " \
  186 + "then; else tftp ${dtbaddr} ${dtb}; fi;" \
  187 + "run mmcroot0; " \
  188 + "bootz ${loadaddr} ${ramaddr} ${dtbaddr}; fi;\0" \
  189 +"netupdate=echo Updating UBOOT from Network (TFTP) ...; " \
  190 + "setenv autoload 0; " \
  191 + "dhcp && tftp 0x80000000 updateUBOOT.img && source;\0" \
  192 +NANDARGS \
  193 +MMCARGS
  194 +#endif /* !CONFIG_SPL_BUILD*/
  195 +
  196 +#define CONFIG_BOOTCOMMAND \
  197 + "run defboot;"
  198 +
  199 +#ifdef CONFIG_NAND
  200 +/*
  201 + * GPMC block. We support 1 device and the physical address to
  202 + * access CS0 at is 0x8000000.
  203 + */
  204 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
  205 +#define CONFIG_SYS_NAND_BASE 0x8000000
  206 +#define CONFIG_NAND_OMAP_GPMC
  207 +/* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */
  208 +#define CONFIG_NAND_OMAP_ELM
  209 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
  210 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
  211 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
  212 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048
  213 +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
  214 + CONFIG_SYS_NAND_PAGE_SIZE)
  215 +#define CONFIG_SYS_NAND_OOBSIZE 64
  216 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
  217 +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, \
  218 + 10, 11, 12, 13, 14, 15, 16, 17, \
  219 + 18, 19, 20, 21, 22, 23, 24, 25, \
  220 + 26, 27, 28, 29, 30, 31, 32, 33, \
  221 + 34, 35, 36, 37, 38, 39, 40, 41, \
  222 + 42, 43, 44, 45, 46, 47, 48, 49, \
  223 + 50, 51, 52, 53, 54, 55, 56, 57, }
  224 +
  225 +#define CONFIG_SYS_NAND_ECCSIZE 512
  226 +#define CONFIG_SYS_NAND_ECCBYTES 14
  227 +
  228 +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  229 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
  230 +
  231 +#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
  232 +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \
  233 + "128k(MLO)," \
  234 + "128k(MLO.backup)," \
  235 + "128k(dtb)," \
  236 + "128k(u-boot-env)," \
  237 + "512k(u-boot)," \
  238 + "4m(kernel),"\
  239 + "128m(rootfs),"\
  240 + "-(user)"
  241 +#define CONFIG_NAND_OMAP_GPMC_WSCFG 1
  242 +#endif /* CONFIG_NAND */
  243 +
  244 +/* USB configuration */
  245 +#define CONFIG_USB_MUSB_DSPS
  246 +#define CONFIG_ARCH_MISC_INIT
  247 +#define CONFIG_USB_MUSB_PIO_ONLY
  248 +#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
  249 +#define CONFIG_AM335X_USB0
  250 +#define CONFIG_AM335X_USB0_MODE MUSB_HOST
  251 +#define CONFIG_AM335X_USB1
  252 +#define CONFIG_AM335X_USB1_MODE MUSB_HOST
  253 +
  254 +#if defined(CONFIG_SPI_BOOT)
  255 +/* McSPI IP block */
  256 +#define CONFIG_SPI
  257 +#define CONFIG_OMAP3_SPI
  258 +#define CONFIG_SF_DEFAULT_SPEED 24000000
  259 +
  260 +#define CONFIG_SPL_SPI_SUPPORT
  261 +#define CONFIG_SPL_SPI_FLASH_SUPPORT
  262 +#define CONFIG_SPL_SPI_LOAD
  263 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
  264 +#undef CONFIG_ENV_IS_NOWHERE
  265 +#define CONFIG_ENV_IS_IN_SPI_FLASH
  266 +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
  267 +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
  268 +#define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */
  269 +#define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */
  270 +#define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */
  271 +
  272 +#elif defined(CONFIG_EMMC_BOOT)
  273 +#undef CONFIG_ENV_IS_NOWHERE
  274 +#define CONFIG_ENV_IS_IN_MMC
  275 +#define CONFIG_SYS_MMC_ENV_DEV 0
  276 +#define CONFIG_SYS_MMC_ENV_PART 2
  277 +#define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */
  278 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
  279 +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
  280 +
  281 +#elif defined(CONFIG_NAND)
  282 +/* No NAND env support in SPL */
  283 +#ifdef CONFIG_SPL_BUILD
  284 +#define CONFIG_ENV_IS_NOWHERE
  285 +#else
  286 +#define CONFIG_ENV_IS_IN_NAND
  287 +#endif
  288 +#define CONFIG_ENV_OFFSET 0x60000
  289 +#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_ENV_SIZE
  290 +#else
  291 +#error "no storage for Environment defined!"
  292 +#endif
  293 +/*
  294 + * Common filesystems support. When we have removable storage we
  295 + * enabled a number of useful commands and support.
  296 + */
  297 +#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE)
  298 +#define CONFIG_DOS_PARTITION
  299 +#define CONFIG_FAT_WRITE
  300 +#define CONFIG_FS_EXT4
  301 +#define CONFIG_EXT4_WRITE
  302 +#endif /* CONFIG_MMC, ... */
  303 +
  304 +#endif /* ! __CONFIG_BRPPT1_H__ */
include/configs/tseries.h
View file @ 2290fe0
1   -/*
2   - * tseries.h
3   - *
4   - * specific parts for B&R T-Series Motherboard
5   - *
6   - * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> -
7   - * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
8   - *
9   - * SPDX-License-Identifier: GPL-2.0+
10   - */
11   -
12   -#ifndef __CONFIG_TSERIES_H__
13   -#define __CONFIG_TSERIES_H__
14   -
15   -#include <configs/bur_cfg_common.h>
16   -#include <configs/bur_am335x_common.h>
17   -/* ------------------------------------------------------------------------- */
18   -#define CONFIG_AM335X_LCD
19   -#define CONFIG_LCD
20   -#define CONFIG_LCD_ROTATION
21   -#define CONFIG_LCD_DT_SIMPLEFB
22   -#define CONFIG_SYS_WHITE_ON_BLACK
23   -#define LCD_BPP LCD_COLOR32
24   -
25   -#define CONFIG_HW_WATCHDOG
26   -#define CONFIG_OMAP_WATCHDOG
27   -#define CONFIG_SPL_WATCHDOG_SUPPORT
28   -
29   -#define CONFIG_SPL_GPIO_SUPPORT
30   -/* Bootcount using the RTC block */
31   -#define CONFIG_SYS_BOOTCOUNT_ADDR 0x44E3E000
32   -#define CONFIG_BOOTCOUNT_LIMIT
33   -#define CONFIG_BOOTCOUNT_AM33XX
34   -
35   -/* memory */
36   -#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024)
37   -
38   -/* Clock Defines */
39   -#define V_OSCK 26000000 /* Clock output from T2 */
40   -#define V_SCLK (V_OSCK)
41   -
42   -#define CONFIG_POWER_TPS65217
43   -
44   -/* Support both device trees and ATAGs. */
45   -#define CONFIG_USE_FDT /* use fdt within board code */
46   -#define CONFIG_CMDLINE_TAG
47   -#define CONFIG_SETUP_MEMORY_TAGS
48   -#define CONFIG_INITRD_TAG
49   -/*#define CONFIG_MACH_TYPE 3589*/
50   -#define CONFIG_MACH_TYPE 0xFFFFFFFF /* TODO: check with kernel*/
51   -
52   -/* MMC/SD IP block */
53   -#if defined(CONFIG_EMMC_BOOT)
54   - #define CONFIG_MMC
55   - #define CONFIG_GENERIC_MMC
56   - #define CONFIG_OMAP_HSMMC
57   - #define CONFIG_SUPPORT_EMMC_BOOT
58   -/* RAW SD card / eMMC locations. */
59   - #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /*addr. 0x60000 */
60   - #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
61   - #define CONFIG_SPL_MMC_SUPPORT
62   -#endif /* CONFIG_EMMC_BOOT */
63   -
64   -/*
65   - * When we have SPI or NAND flash we expect to be making use of mtdparts,
66   - * both for ease of use in U-Boot and for passing information on to
67   - * the Linux kernel.
68   - */
69   -#if defined(CONFIG_SPI_BOOT) || defined(CONFIG_NAND)
70   -#define CONFIG_MTD_DEVICE /* Required for mtdparts */
71   -#define CONFIG_CMD_MTDPARTS
72   -#endif /* CONFIG_SPI_BOOT, ... */
73   -
74   -#undef CONFIG_SPL_OS_BOOT
75   -#ifdef CONFIG_SPL_OS_BOOT
76   -#define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000
77   -
78   -/* RAW SD card / eMMC */
79   -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */
80   -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */
81   -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
82   -
83   -/* NAND */
84   -#ifdef CONFIG_NAND
85   -#define CONFIG_CMD_SPL_NAND_OFS 0x080000 /* end of u-boot */
86   -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x140000
87   -#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
88   -#endif /* CONFIG_NAND */
89   -#endif /* CONFIG_SPL_OS_BOOT */
90   -
91   -#ifdef CONFIG_NAND
92   -#define CONFIG_SPL_NAND_AM33XX_BCH /* OMAP4 and later ELM support */
93   -#define CONFIG_SPL_NAND_SUPPORT
94   -#define CONFIG_SPL_NAND_BASE
95   -#define CONFIG_SPL_NAND_DRIVERS
96   -#define CONFIG_SPL_NAND_ECC
97   -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
98   -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
99   -#endif /* CONFIG_NAND */
100   -
101   -/* Always 64 KiB env size */
102   -#define CONFIG_ENV_SIZE (64 << 10)
103   -
104   -#ifdef CONFIG_NAND
105   -#define NANDARGS \
106   - "mtdids=" MTDIDS_DEFAULT "\0" \
107   - "mtdparts=" MTDPARTS_DEFAULT "\0" \
108   - "nandargs=setenv bootargs console=${console} " \
109   - "${optargs} " \
110   - "${optargs_rot} " \
111   - "root=mtd6 " \
112   - "rootfstype=jffs2\0" \
113   - "kernelsize=0x400000\0" \
114   - "nandboot=echo booting from nand ...; " \
115   - "run nandargs; " \
116   - "nand read ${loadaddr} kernel ${kernelsize}; " \
117   - "bootz ${loadaddr} - ${dtbaddr}\0" \
118   - "defboot=run nandboot\0" \
119   - "bootlimit=1\0" \
120   - "simplefb=1\0 " \
121   - "altbootcmd=run usbscript\0"
122   -#else
123   -#define NANDARGS ""
124   -#endif /* CONFIG_NAND */
125   -
126   -#ifdef CONFIG_MMC
127   -#define MMCARGS \
128   -"dtbdev=mmc\0" \
129   -"dtbpart=0:1\0" \
130   -"mmcroot0=setenv bootargs ${optargs_rot} ${optargs} console=${console}\0" \
131   -"mmcroot1=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \
132   - "root=/dev/mmcblk0p2 rootfstype=ext4\0" \
133   -"mmcboot0=echo booting Updatesystem from mmc (ext4-fs) ...; " \
134   - "setenv simplefb 1; " \
135   - "ext4load mmc 0:1 ${loadaddr} /${kernel}; " \
136   - "ext4load mmc 0:1 ${ramaddr} /${ramdisk}; " \
137   - "run mmcroot0; bootz ${loadaddr} ${ramaddr} ${dtbaddr};\0" \
138   -"mmcboot1=echo booting PPT-OS from mmc (ext4-fs) ...; " \
139   - "setenv simplefb 0; " \
140   - "ext4load mmc 0:2 ${loadaddr} /boot/${kernel}; " \
141   - "run mmcroot1; bootz ${loadaddr} - ${dtbaddr};\0" \
142   -"defboot=ext4load mmc 0:2 ${loadaddr} /boot/PPTImage.md5 && run mmcboot1; " \
143   - "ext4load mmc 0:1 ${dtbaddr} /$dtb && run mmcboot0; " \
144   - "run ramboot; run usbscript;\0" \
145   -"bootlimit=1\0" \
146   -"altbootcmd=run mmcboot0;\0" \
147   -"upduboot=dhcp; " \
148   - "tftp ${loadaddr} MLO && mmc write ${loadaddr} 100 100; " \
149   - "tftp ${loadaddr} u-boot.img && mmc write ${loadaddr} 300 400;\0"
150   -#else
151   -#define MMCARGS ""
152   -#endif /* CONFIG_MMC */
153   -
154   -#ifndef CONFIG_SPL_BUILD
155   -#define CONFIG_EXTRA_ENV_SETTINGS \
156   -BUR_COMMON_ENV \
157   -"verify=no\0" \
158   -"autoload=0\0" \
159   -"dtb=bur-ppt-ts30.dtb\0" \
160   -"dtbaddr=0x80100000\0" \
161   -"loadaddr=0x80200000\0" \
162   -"ramaddr=0x80A00000\0" \
163   -"kernel=zImage\0" \
164   -"ramdisk=rootfs.cpio.uboot\0" \
165   -"console=ttyO0,115200n8\0" \
166   -"optargs=consoleblank=0 quiet panic=2\0" \
167   -"nfsroot=/tftpboot/tseries/rootfs-small\0" \
168   -"nfsopts=nolock\0" \
169   -"ramargs=setenv bootargs ${optargs} console=${console} root=/dev/ram0\0" \
170   -"netargs=setenv bootargs console=${console} " \
171   - "${optargs} " \
172   - "root=/dev/nfs " \
173   - "nfsroot=${serverip}:${nfsroot},${nfsopts} rw " \
174   - "ip=dhcp\0" \
175   -"netboot=echo Booting from network ...; " \
176   - "dhcp; " \
177   - "tftp ${loadaddr} ${kernel}; " \
178   - "tftp ${dtbaddr} ${dtb}; " \
179   - "run netargs; " \
180   - "bootz ${loadaddr} - ${dtbaddr}\0" \
181   -"ramboot=echo Booting from network into RAM ...; "\
182   - "if dhcp; then; " \
183   - "tftp ${loadaddr} ${kernel}; " \
184   - "tftp ${ramaddr} ${ramdisk}; " \
185   - "if ext4load ${dtbdev} ${dtbpart} ${dtbaddr} /${dtb}; " \
186   - "then; else tftp ${dtbaddr} ${dtb}; fi;" \
187   - "run mmcroot0; " \
188   - "bootz ${loadaddr} ${ramaddr} ${dtbaddr}; fi;\0" \
189   -"netupdate=echo Updating UBOOT from Network (TFTP) ...; " \
190   - "setenv autoload 0; " \
191   - "dhcp && tftp 0x80000000 updateUBOOT.img && source;\0" \
192   -NANDARGS \
193   -MMCARGS
194   -#endif /* !CONFIG_SPL_BUILD*/
195   -
196   -#define CONFIG_BOOTCOMMAND \
197   - "run defboot;"
198   -
199   -#ifdef CONFIG_NAND
200   -/*
201   - * GPMC block. We support 1 device and the physical address to
202   - * access CS0 at is 0x8000000.
203   - */
204   -#define CONFIG_SYS_MAX_NAND_DEVICE 1
205   -#define CONFIG_SYS_NAND_BASE 0x8000000
206   -#define CONFIG_NAND_OMAP_GPMC
207   -/* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */
208   -#define CONFIG_NAND_OMAP_ELM
209   -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
210   -#define CONFIG_SYS_NAND_5_ADDR_CYCLE
211   -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
212   -#define CONFIG_SYS_NAND_PAGE_SIZE 2048
213   -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
214   - CONFIG_SYS_NAND_PAGE_SIZE)
215   -#define CONFIG_SYS_NAND_OOBSIZE 64
216   -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
217   -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, \
218   - 10, 11, 12, 13, 14, 15, 16, 17, \
219   - 18, 19, 20, 21, 22, 23, 24, 25, \
220   - 26, 27, 28, 29, 30, 31, 32, 33, \
221   - 34, 35, 36, 37, 38, 39, 40, 41, \
222   - 42, 43, 44, 45, 46, 47, 48, 49, \
223   - 50, 51, 52, 53, 54, 55, 56, 57, }
224   -
225   -#define CONFIG_SYS_NAND_ECCSIZE 512
226   -#define CONFIG_SYS_NAND_ECCBYTES 14
227   -
228   -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
229   -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
230   -
231   -#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
232   -#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \
233   - "128k(MLO)," \
234   - "128k(MLO.backup)," \
235   - "128k(dtb)," \
236   - "128k(u-boot-env)," \
237   - "512k(u-boot)," \
238   - "4m(kernel),"\
239   - "128m(rootfs),"\
240   - "-(user)"
241   -#define CONFIG_NAND_OMAP_GPMC_WSCFG 1
242   -#endif /* CONFIG_NAND */
243   -
244   -/* USB configuration */
245   -#define CONFIG_USB_MUSB_DSPS
246   -#define CONFIG_ARCH_MISC_INIT
247   -#define CONFIG_USB_MUSB_PIO_ONLY
248   -#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
249   -#define CONFIG_AM335X_USB0
250   -#define CONFIG_AM335X_USB0_MODE MUSB_HOST
251   -#define CONFIG_AM335X_USB1
252   -#define CONFIG_AM335X_USB1_MODE MUSB_HOST
253   -
254   -#if defined(CONFIG_SPI_BOOT)
255   -/* McSPI IP block */
256   -#define CONFIG_SPI
257   -#define CONFIG_OMAP3_SPI
258   -#define CONFIG_SF_DEFAULT_SPEED 24000000
259   -
260   -#define CONFIG_SPL_SPI_SUPPORT
261   -#define CONFIG_SPL_SPI_FLASH_SUPPORT
262   -#define CONFIG_SPL_SPI_LOAD
263   -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
264   -#undef CONFIG_ENV_IS_NOWHERE
265   -#define CONFIG_ENV_IS_IN_SPI_FLASH
266   -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
267   -#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
268   -#define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */
269   -#define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */
270   -#define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */
271   -
272   -#elif defined(CONFIG_EMMC_BOOT)
273   -#undef CONFIG_ENV_IS_NOWHERE
274   -#define CONFIG_ENV_IS_IN_MMC
275   -#define CONFIG_SYS_MMC_ENV_DEV 0
276   -#define CONFIG_SYS_MMC_ENV_PART 2
277   -#define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */
278   -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
279   -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
280   -
281   -#elif defined(CONFIG_NAND)
282   -/* No NAND env support in SPL */
283   -#ifdef CONFIG_SPL_BUILD
284   -#define CONFIG_ENV_IS_NOWHERE
285   -#else
286   -#define CONFIG_ENV_IS_IN_NAND
287   -#endif
288   -#define CONFIG_ENV_OFFSET 0x60000
289   -#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_ENV_SIZE
290   -#else
291   -#error "no storage for Environment defined!"
292   -#endif
293   -/*
294   - * Common filesystems support. When we have removable storage we
295   - * enabled a number of useful commands and support.
296   - */
297   -#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE)
298   -#define CONFIG_DOS_PARTITION
299   -#define CONFIG_FAT_WRITE
300   -#define CONFIG_FS_EXT4
301   -#define CONFIG_EXT4_WRITE
302   -#endif /* CONFIG_MMC, ... */
303   -
304   -#endif /* ! __CONFIG_TSERIES_H__ */