ARMv8: Adjust MMU setup

Make MMU function reusable. Platform code can setup its own MMU tables. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn>

ARMv8: Adjust MMU setup
Make MMU function reusable. Platform code can setup its own MMU tables. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn>
York Sun · Albert ARIBAUD
1 parent 0d031e046c
Showing 2 changed files with 44 additions and 30 deletions Side-by-side Diff
arch/arm/cpu/armv8/cache_v8.c
arch/arm/include/asm/armv8/mmu.h
@@ -12,15 +12,14 @@
 DECLARE_GLOBAL_DATA_PTR;
  
 #ifndef CONFIG_SYS_DCACHE_OFF
-
-static void set_pgtable_section(u64 section, u64 memory_type)
+void set_pgtable_section(u64 *page_table, u64 index, u64 section,
+			 u64 memory_type)
 {
-	u64 *page_table = (u64 *)gd->arch.tlb_addr;
 	u64 value;
  
-	value = (section << SECTION_SHIFT) | PMD_TYPE_SECT | PMD_SECT_AF;
+	value = section | PMD_TYPE_SECT | PMD_SECT_AF;
 	value |= PMD_ATTRINDX(memory_type);
-	page_table[section] = value;
+	page_table[index] = value;
 }
  
 /* to activate the MMU we need to set up virtual memory */
  
@@ -28,10 +27,13 @@
 {
 	int i, j, el;
 	bd_t *bd = gd->bd;
+	u64 *page_table = (u64 *)gd->arch.tlb_addr;
  
 	/* Setup an identity-mapping for all spaces */
-	for (i = 0; i < (PGTABLE_SIZE >> 3); i++)
-		set_pgtable_section(i, MT_DEVICE_NGNRNE);
+	for (i = 0; i < (PGTABLE_SIZE >> 3); i++) {
+		set_pgtable_section(page_table, i, i << SECTION_SHIFT,
+				    MT_DEVICE_NGNRNE);
+	}
  
 	/* Setup an identity-mapping for all RAM space */
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  
  
  
  
@@ -39,38 +41,26 @@
 		ulong end = bd->bi_dram[i].start + bd->bi_dram[i].size;
 		for (j = start >> SECTION_SHIFT;
 		     j < end >> SECTION_SHIFT; j++) {
-			set_pgtable_section(j, MT_NORMAL);
+			set_pgtable_section(page_table, j, j << SECTION_SHIFT,
+					    MT_NORMAL);
 		}
 	}
  
 	/* load TTBR0 */
 	el = current_el();
 	if (el == 1) {
-		asm volatile("msr ttbr0_el1, %0"
-			     : : "r" (gd->arch.tlb_addr) : "memory");
-		asm volatile("msr tcr_el1, %0"
-			     : : "r" (TCR_FLAGS | TCR_EL1_IPS_BITS)
-			     : "memory");
-		asm volatile("msr mair_el1, %0"
-			     : : "r" (MEMORY_ATTRIBUTES) : "memory");
+		set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
+				  TCR_FLAGS | TCR_EL1_IPS_BITS,
+				  MEMORY_ATTRIBUTES);
 	} else if (el == 2) {
-		asm volatile("msr ttbr0_el2, %0"
-			     : : "r" (gd->arch.tlb_addr) : "memory");
-		asm volatile("msr tcr_el2, %0"
-			     : : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS)
-			     : "memory");
-		asm volatile("msr mair_el2, %0"
-			     : : "r" (MEMORY_ATTRIBUTES) : "memory");
+		set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
+				  TCR_FLAGS | TCR_EL2_IPS_BITS,
+				  MEMORY_ATTRIBUTES);
 	} else {
-		asm volatile("msr ttbr0_el3, %0"
-			     : : "r" (gd->arch.tlb_addr) : "memory");
-		asm volatile("msr tcr_el3, %0"
-			     : : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS)
-			     : "memory");
-		asm volatile("msr mair_el3, %0"
-			     : : "r" (MEMORY_ATTRIBUTES) : "memory");
+		set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
+				  TCR_FLAGS | TCR_EL3_IPS_BITS,
+				  MEMORY_ATTRIBUTES);
 	}
-
 	/* enable the mmu */
 	set_sctlr(get_sctlr() | CR_M);
 }
@@ -108,5 +108,29 @@
 				TCR_IRGN_WBWA |		\
 				TCR_T0SZ(VA_BITS))
  
+#ifndef __ASSEMBLY__
+void set_pgtable_section(u64 *page_table, u64 index,
+			 u64 section, u64 memory_type);
+static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
+{
+	asm volatile("dsb sy");
+	if (el == 1) {
+		asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory");
+		asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory");
+		asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory");
+	} else if (el == 2) {
+		asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory");
+		asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory");
+		asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory");
+	} else if (el == 3) {
+		asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory");
+		asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory");
+		asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory");
+	} else {
+		hang();
+	}
+	asm volatile("isb");
+}
+#endif
 #endif /* _ASM_ARMV8_MMU_H_ */
...	...	@@ -12,15 +12,14 @@
12	12	DECLARE_GLOBAL_DATA_PTR;
13	13
14	14	#ifndef CONFIG_SYS_DCACHE_OFF
15		-
16		-static void set_pgtable_section(u64 section, u64 memory_type)
	15	+void set_pgtable_section(u64 *page_table, u64 index, u64 section,
	16	+ u64 memory_type)
17	17	{
18		- u64 page_table = (u64 )gd->arch.tlb_addr;
19	18	u64 value;
20	19
21		- value = (section << SECTION_SHIFT) \| PMD_TYPE_SECT \| PMD_SECT_AF;
	20	+ value = section \| PMD_TYPE_SECT \| PMD_SECT_AF;
22	21	value \|= PMD_ATTRINDX(memory_type);
23		- page_table[section] = value;
	22	+ page_table[index] = value;
24	23	}
25	24
26	25	/* to activate the MMU we need to set up virtual memory */
27	26
...	...	@@ -28,10 +27,13 @@
28	27	{
29	28	int i, j, el;
30	29	bd_t *bd = gd->bd;
	30	+ u64 page_table = (u64 )gd->arch.tlb_addr;
31	31
32	32	/* Setup an identity-mapping for all spaces */
33		- for (i = 0; i < (PGTABLE_SIZE >> 3); i++)
34		- set_pgtable_section(i, MT_DEVICE_NGNRNE);
	33	+ for (i = 0; i < (PGTABLE_SIZE >> 3); i++) {
	34	+ set_pgtable_section(page_table, i, i << SECTION_SHIFT,
	35	+ MT_DEVICE_NGNRNE);
	36	+ }
35	37
36	38	/* Setup an identity-mapping for all RAM space */
37	39	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
38	40
39	41
40	42
41	43
...	...	@@ -39,38 +41,26 @@
39	41	ulong end = bd->bi_dram[i].start + bd->bi_dram[i].size;
40	42	for (j = start >> SECTION_SHIFT;
41	43	j < end >> SECTION_SHIFT; j++) {
42		- set_pgtable_section(j, MT_NORMAL);
	44	+ set_pgtable_section(page_table, j, j << SECTION_SHIFT,
	45	+ MT_NORMAL);
43	46	}
44	47	}
45	48
46	49	/* load TTBR0 */
47	50	el = current_el();
48	51	if (el == 1) {
49		- asm volatile("msr ttbr0_el1, %0"
50		- : : "r" (gd->arch.tlb_addr) : "memory");
51		- asm volatile("msr tcr_el1, %0"
52		- : : "r" (TCR_FLAGS \| TCR_EL1_IPS_BITS)
53		- : "memory");
54		- asm volatile("msr mair_el1, %0"
55		- : : "r" (MEMORY_ATTRIBUTES) : "memory");
	52	+ set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
	53	+ TCR_FLAGS \| TCR_EL1_IPS_BITS,
	54	+ MEMORY_ATTRIBUTES);
56	55	} else if (el == 2) {
57		- asm volatile("msr ttbr0_el2, %0"
58		- : : "r" (gd->arch.tlb_addr) : "memory");
59		- asm volatile("msr tcr_el2, %0"
60		- : : "r" (TCR_FLAGS \| TCR_EL2_IPS_BITS)
61		- : "memory");
62		- asm volatile("msr mair_el2, %0"
63		- : : "r" (MEMORY_ATTRIBUTES) : "memory");
	56	+ set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
	57	+ TCR_FLAGS \| TCR_EL2_IPS_BITS,
	58	+ MEMORY_ATTRIBUTES);
64	59	} else {
65		- asm volatile("msr ttbr0_el3, %0"
66		- : : "r" (gd->arch.tlb_addr) : "memory");
67		- asm volatile("msr tcr_el3, %0"
68		- : : "r" (TCR_FLAGS \| TCR_EL2_IPS_BITS)
69		- : "memory");
70		- asm volatile("msr mair_el3, %0"
71		- : : "r" (MEMORY_ATTRIBUTES) : "memory");
	60	+ set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
	61	+ TCR_FLAGS \| TCR_EL3_IPS_BITS,
	62	+ MEMORY_ATTRIBUTES);
72	63	}
73		-
74	64	/* enable the mmu */
75	65	set_sctlr(get_sctlr() \| CR_M);
76	66	}
...	...	@@ -108,5 +108,29 @@
108	108	TCR_IRGN_WBWA \| \
109	109	TCR_T0SZ(VA_BITS))
110	110
	111	+#ifndef __ASSEMBLY__
	112	+void set_pgtable_section(u64 *page_table, u64 index,
	113	+ u64 section, u64 memory_type);
	114	+static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
	115	+{
	116	+ asm volatile("dsb sy");
	117	+ if (el == 1) {
	118	+ asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory");
	119	+ asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory");
	120	+ asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory");
	121	+ } else if (el == 2) {
	122	+ asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory");
	123	+ asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory");
	124	+ asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory");
	125	+ } else if (el == 3) {
	126	+ asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory");
	127	+ asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory");
	128	+ asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory");
	129	+ } else {
	130	+ hang();
	131	+ }
	132	+ asm volatile("isb");
	133	+}
	134	+#endif
111	135	#endif /* _ASM_ARMV8_MMU_H_ */