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Commit 234d89dac61a4f57a0f7cb136a6c442f37a6c9b8

Authored by Tim Harvey
Committed by Stefano Babic
1 parent 5e2f01772a
Exists in v2017.01-smarct4x and in 40 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

ventana: Add support for the LTC3676 PMIC 

The LTC3676 PMIC is used instead of the PFUZE100 PMIC on the
GW51xx/GW52xx/GW53xx Ventana baseboards. In order to support the IMX6Q SoC
at 1GHz on those baseboards, we need to adjust the voltage scaling for the SW1
and SW3 DC/DC converters on the LTC3676 for 1225mV. Note that the scalar
values for the LTC3676 are board-specific as they relate to a resistor devider
chosen by the board design.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

Showing 2 changed files with 59 additions and 23 deletions Side-by-side Diff

board/gateworks/gw_ventana/gw_ventana.c
Diff comments   View file @ 234d89d
... ... @@ -30,6 +30,7 @@
30 30 #include <mtd_node.h>
31 31 #include <netdev.h>
32 32 #include <power/pmic.h>
  33 +#include <power/ltc3676_pmic.h>
33 34 #include <power/pfuze100_pmic.h>
34 35 #include <fdt_support.h>
35 36 #include <jffs2/load_kernel.h>
... ... @@ -732,6 +733,62 @@
732 733 },
733 734 };
734 735  
  736 +/* setup board specific PMIC */
  737 +int power_init_board(void)
  738 +{
  739 + struct pmic *p;
  740 + u32 reg;
  741 +
  742 + /* configure PFUZE100 PMIC */
  743 + if (board_type == GW54xx || board_type == GW54proto) {
  744 + power_pfuze100_init(I2C_PMIC);
  745 + p = pmic_get("PFUZE100_PMIC");
  746 + if (p && !pmic_probe(p)) {
  747 + pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
  748 + printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
  749 +
  750 + /* Set VGEN1 to 1.5V and enable */
  751 + pmic_reg_read(p, PFUZE100_VGEN1VOL, &reg);
  752 + reg &= ~(LDO_VOL_MASK);
  753 + reg |= (LDOA_1_50V | LDO_EN);
  754 + pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
  755 +
  756 + /* Set SWBST to 5.0V and enable */
  757 + pmic_reg_read(p, PFUZE100_SWBSTCON1, &reg);
  758 + reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
  759 + reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
  760 + pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
  761 + }
  762 + }
  763 +
  764 + /* configure LTC3676 PMIC */
  765 + else {
  766 + power_ltc3676_init(I2C_PMIC);
  767 + p = pmic_get("LTC3676_PMIC");
  768 + if (p && !pmic_probe(p)) {
  769 + puts("PMIC: LTC3676\n");
  770 + /* set board-specific scalar to 1225mV for IMX6Q@1GHz */
  771 + if (is_cpu_type(MXC_CPU_MX6Q)) {
  772 + /* mask PGOOD during SW1 transition */
  773 + reg = 0x1d | LTC3676_PGOOD_MASK;
  774 + pmic_reg_write(p, LTC3676_DVB1B, reg);
  775 + /* set SW1 (VDD_SOC) to 1259mV */
  776 + reg = 0x1d;
  777 + pmic_reg_write(p, LTC3676_DVB1A, reg);
  778 +
  779 + /* mask PGOOD during SW3 transition */
  780 + reg = 0x1d | LTC3676_PGOOD_MASK;
  781 + pmic_reg_write(p, LTC3676_DVB3B, reg);
  782 + /*set SW3 (VDD_ARM) to 1259mV */
  783 + reg = 0x1d;
  784 + pmic_reg_write(p, LTC3676_DVB3A, reg);
  785 + }
  786 + }
  787 + }
  788 +
  789 + return 0;
  790 +}
  791 +
735 792 /* setup GPIO pinmux and default configuration per baseboard */
736 793 static void setup_board_gpio(int board)
737 794 {
... ... @@ -1075,29 +1132,6 @@
1075 1132 setenv("serial#", str);
1076 1133 }
1077 1134  
1078   - /* configure PFUZE100 PMIC (not used on all Ventana baseboards) */
1079   - power_pfuze100_init(I2C_PMIC);
1080   - if (board_type == GW54xx || board_type == GW54proto) {
1081   - struct pmic *p = pmic_get("PFUZE100_PMIC");
1082   - u32 reg;
1083   -
1084   - if (p && !pmic_probe(p)) {
1085   - pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
1086   - printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
1087   -
1088   - /* Set VGEN1 to 1.5V and enable */
1089   - pmic_reg_read(p, PFUZE100_VGEN1VOL, &reg);
1090   - reg &= ~(LDO_VOL_MASK);
1091   - reg |= (LDOA_1_50V | LDO_EN);
1092   - pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
1093   -
1094   - /* Set SWBST to 5.0V and enable */
1095   - pmic_reg_read(p, PFUZE100_SWBSTCON1, &reg);
1096   - reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
1097   - reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
1098   - pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
1099   - }
1100   - }
1101 1135  
1102 1136 /* setup baseboard specific GPIO pinmux and config */
1103 1137 setup_board_gpio(board_type);
include/configs/gw_ventana.h
Diff comments   View file @ 234d89d
... ... @@ -136,6 +136,8 @@
136 136 #define CONFIG_POWER_I2C
137 137 #define CONFIG_POWER_PFUZE100
138 138 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
  139 +#define CONFIG_POWER_LTC3676
  140 +#define CONFIG_POWER_LTC3676_I2C_ADDR 0x3c
139 141  
140 142 /* Various command support */
141 143 #include <config_cmd_default.h>