Eric Lee / smarc-uboot

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Commit 23650e03d6908e3462102103908a2dba0d7a03ee

Authored by Fugang Duan
Committed by Ye Li
1 parent 120b0893b9
Exists in smarc_8mq_lf_v2020.04 and in 4 other branches pitx_8mp_lf_v2020.04, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mp_lf_v2020.04

MLK-23165-15 net: dwc_eth_qos: add dwc eqos for imx support 

Add dwc eqos for imx support.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
(cherry picked from commit 52751a41c92a719891c8154cfc488165cc42f713)

Showing 1 changed file with 173 additions and 14 deletions Side-by-side Diff

drivers/net/dwc_eth_qos.c
Diff comments   View file @ 23650e0
... ... @@ -81,6 +81,7 @@
81 81 #define EQOS_MAC_CONFIGURATION_PS BIT(15)
82 82 #define EQOS_MAC_CONFIGURATION_FES BIT(14)
83 83 #define EQOS_MAC_CONFIGURATION_DM BIT(13)
  84 +#define EQOS_MAC_CONFIGURATION_LM BIT(12)
84 85 #define EQOS_MAC_CONFIGURATION_TE BIT(1)
85 86 #define EQOS_MAC_CONFIGURATION_RE BIT(0)
86 87  
87 88  
... ... @@ -102,11 +103,19 @@
102 103 #define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
103 104 #define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff
104 105  
  106 +#define EQOS_MAC_HW_FEATURE0_MMCSEL_SHIFT 8
  107 +#define EQOS_MAC_HW_FEATURE0_HDSEL_SHIFT 2
  108 +#define EQOS_MAC_HW_FEATURE0_GMIISEL_SHIFT 1
  109 +#define EQOS_MAC_HW_FEATURE0_MIISEL_SHIFT 0
  110 +
105 111 #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6
106 112 #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f
107 113 #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0
108 114 #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f
109 115  
  116 +#define EQOS_MAC_HW_FEATURE3_ASP_SHIFT 28
  117 +#define EQOS_MAC_HW_FEATURE3_ASP_MASK 0x3
  118 +
110 119 #define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
111 120 #define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16
112 121 #define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
... ... @@ -154,6 +163,8 @@
154 163 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f
155 164 #define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7)
156 165 #define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5)
  166 +#define EQOS_MTL_RXQ0_OPERATION_MODE_FEP BIT(4)
  167 +#define EQOS_MTL_RXQ0_OPERATION_MODE_FUP BIT(3)
157 168  
158 169 #define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16
159 170 #define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK 0x7fff
... ... @@ -366,7 +377,7 @@
366 377 #endif
367 378 }
368 379  
369   -static void eqos_inval_desc_stm32(void *desc)
  380 +static void eqos_inval_desc_generic(void *desc)
370 381 {
371 382 #ifndef CONFIG_SYS_NONCACHED_MEMORY
372 383 unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN);
... ... @@ -384,7 +395,7 @@
384 395 #endif
385 396 }
386 397  
387   -static void eqos_flush_desc_stm32(void *desc)
  398 +static void eqos_flush_desc_generic(void *desc)
388 399 {
389 400 #ifndef CONFIG_SYS_NONCACHED_MEMORY
390 401 unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN);
... ... @@ -403,7 +414,7 @@
403 414 invalidate_dcache_range(start, end);
404 415 }
405 416  
406   -static void eqos_inval_buffer_stm32(void *buf, size_t size)
  417 +static void eqos_inval_buffer_generic(void *buf, size_t size)
407 418 {
408 419 unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
409 420 unsigned long end = roundup((unsigned long)buf + size,
... ... @@ -417,7 +428,7 @@
417 428 flush_cache((unsigned long)buf, size);
418 429 }
419 430  
420   -static void eqos_flush_buffer_stm32(void *buf, size_t size)
  431 +static void eqos_flush_buffer_generic(void *buf, size_t size)
421 432 {
422 433 unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
423 434 unsigned long end = roundup((unsigned long)buf + size,
... ... @@ -520,6 +531,7 @@
520 531  
521 532 static int eqos_start_clks_tegra186(struct udevice *dev)
522 533 {
  534 +#ifdef CONFIG_CLK
523 535 struct eqos_priv *eqos = dev_get_priv(dev);
524 536 int ret;
525 537  
526 538  
... ... @@ -560,10 +572,12 @@
560 572 pr_err("clk_enable(clk_tx) failed: %d", ret);
561 573 goto err_disable_clk_ptp_ref;
562 574 }
  575 +#endif
563 576  
564 577 debug("%s: OK\n", __func__);
565 578 return 0;
566 579  
  580 +#ifdef CONFIG_CLK
567 581 err_disable_clk_ptp_ref:
568 582 clk_disable(&eqos->clk_ptp_ref);
569 583 err_disable_clk_rx:
570 584  
... ... @@ -575,10 +589,12 @@
575 589 err:
576 590 debug("%s: FAILED: %d\n", __func__, ret);
577 591 return ret;
  592 +#endif
578 593 }
579 594  
580 595 static int eqos_start_clks_stm32(struct udevice *dev)
581 596 {
  597 +#ifdef CONFIG_CLK
582 598 struct eqos_priv *eqos = dev_get_priv(dev);
583 599 int ret;
584 600  
585 601  
... ... @@ -609,10 +625,12 @@
609 625 goto err_disable_clk_tx;
610 626 }
611 627 }
  628 +#endif
612 629  
613 630 debug("%s: OK\n", __func__);
614 631 return 0;
615 632  
  633 +#ifdef CONFIG_CLK
616 634 err_disable_clk_tx:
617 635 clk_disable(&eqos->clk_tx);
618 636 err_disable_clk_rx:
619 637  
620 638  
... ... @@ -622,10 +640,17 @@
622 640 err:
623 641 debug("%s: FAILED: %d\n", __func__, ret);
624 642 return ret;
  643 +#endif
625 644 }
626 645  
  646 +static int eqos_start_clks_imx(struct udevice *dev)
  647 +{
  648 + return 0;
  649 +}
  650 +
627 651 static void eqos_stop_clks_tegra186(struct udevice *dev)
628 652 {
  653 +#ifdef CONFIG_CLK
629 654 struct eqos_priv *eqos = dev_get_priv(dev);
630 655  
631 656 debug("%s(dev=%p):\n", __func__, dev);
632 657  
... ... @@ -635,12 +660,14 @@
635 660 clk_disable(&eqos->clk_rx);
636 661 clk_disable(&eqos->clk_master_bus);
637 662 clk_disable(&eqos->clk_slave_bus);
  663 +#endif
638 664  
639 665 debug("%s: OK\n", __func__);
640 666 }
641 667  
642 668 static void eqos_stop_clks_stm32(struct udevice *dev)
643 669 {
  670 +#ifdef CONFIG_CLK
644 671 struct eqos_priv *eqos = dev_get_priv(dev);
645 672  
646 673 debug("%s(dev=%p):\n", __func__, dev);
647 674  
... ... @@ -650,10 +677,16 @@
650 677 clk_disable(&eqos->clk_master_bus);
651 678 if (clk_valid(&eqos->clk_ck))
652 679 clk_disable(&eqos->clk_ck);
  680 +#endif
653 681  
654 682 debug("%s: OK\n", __func__);
655 683 }
656 684  
  685 +static void eqos_stop_clks_imx(struct udevice *dev)
  686 +{
  687 + /* empty */
  688 +}
  689 +
657 690 static int eqos_start_resets_tegra186(struct udevice *dev)
658 691 {
659 692 struct eqos_priv *eqos = dev_get_priv(dev);
... ... @@ -698,6 +731,11 @@
698 731 return 0;
699 732 }
700 733  
  734 +static int eqos_start_resets_imx(struct udevice *dev)
  735 +{
  736 + return 0;
  737 +}
  738 +
701 739 static int eqos_stop_resets_tegra186(struct udevice *dev)
702 740 {
703 741 struct eqos_priv *eqos = dev_get_priv(dev);
... ... @@ -713,6 +751,11 @@
713 751 return 0;
714 752 }
715 753  
  754 +static int eqos_stop_resets_imx(struct udevice *dev)
  755 +{
  756 + return 0;
  757 +}
  758 +
716 759 static int eqos_calibrate_pads_tegra186(struct udevice *dev)
717 760 {
718 761 struct eqos_priv *eqos = dev_get_priv(dev);
719 762  
720 763  
721 764  
722 765  
723 766  
724 767  
... ... @@ -767,28 +810,52 @@
767 810  
768 811 static ulong eqos_get_tick_clk_rate_tegra186(struct udevice *dev)
769 812 {
  813 +#ifdef CONFIG_CLK
770 814 struct eqos_priv *eqos = dev_get_priv(dev);
771 815  
772 816 return clk_get_rate(&eqos->clk_slave_bus);
  817 +#else
  818 + return 0;
  819 +#endif
773 820 }
774 821  
775 822 static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev)
776 823 {
  824 +#ifdef CONFIG_CLK
777 825 struct eqos_priv *eqos = dev_get_priv(dev);
778 826  
779 827 return clk_get_rate(&eqos->clk_master_bus);
  828 +#else
  829 + return 0;
  830 +#endif
780 831 }
781 832  
  833 +static ulong eqos_get_tick_clk_rate_imx(struct udevice *dev)
  834 +{
  835 + /* TODO: retrieve from CSR clock */
  836 + return 100 * 1000000;
  837 +}
  838 +
782 839 static int eqos_calibrate_pads_stm32(struct udevice *dev)
783 840 {
784 841 return 0;
785 842 }
786 843  
  844 +static int eqos_calibrate_pads_imx(struct udevice *dev)
  845 +{
  846 + return 0;
  847 +}
  848 +
787 849 static int eqos_disable_calibration_stm32(struct udevice *dev)
788 850 {
789 851 return 0;
790 852 }
791 853  
  854 +static int eqos_disable_calibration_imx(struct udevice *dev)
  855 +{
  856 + return 0;
  857 +}
  858 +
792 859 static int eqos_set_full_duplex(struct udevice *dev)
793 860 {
794 861 struct eqos_priv *eqos = dev_get_priv(dev);
... ... @@ -853,6 +920,7 @@
853 920  
854 921 static int eqos_set_tx_clk_speed_tegra186(struct udevice *dev)
855 922 {
  923 +#ifdef CONFIG_CLK
856 924 struct eqos_priv *eqos = dev_get_priv(dev);
857 925 ulong rate;
858 926 int ret;
... ... @@ -879,6 +947,7 @@
879 947 pr_err("clk_set_rate(tx_clk, %lu) failed: %d", rate, ret);
880 948 return ret;
881 949 }
  950 +#endif
882 951  
883 952 return 0;
884 953 }
... ... @@ -888,6 +957,11 @@
888 957 return 0;
889 958 }
890 959  
  960 +static int eqos_set_tx_clk_speed_imx(struct udevice *dev)
  961 +{
  962 + return 0;
  963 +}
  964 +
891 965 static int eqos_adjust_link(struct udevice *dev)
892 966 {
893 967 struct eqos_priv *eqos = dev_get_priv(dev);
... ... @@ -1085,6 +1159,7 @@
1085 1159 }
1086 1160  
1087 1161 /* Configure MTL */
  1162 + writel(0x60, &eqos->mtl_regs->txq0_quantum_weight - 0x100);
1088 1163  
1089 1164 /* Enable Store and Forward mode for TX */
1090 1165 /* Program Tx operating mode */
... ... @@ -1098,7 +1173,9 @@
1098 1173  
1099 1174 /* Enable Store and Forward mode for RX, since no jumbo frame */
1100 1175 setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1101   - EQOS_MTL_RXQ0_OPERATION_MODE_RSF);
  1176 + EQOS_MTL_RXQ0_OPERATION_MODE_RSF |
  1177 + EQOS_MTL_RXQ0_OPERATION_MODE_FEP |
  1178 + EQOS_MTL_RXQ0_OPERATION_MODE_FUP);
1102 1179  
1103 1180 /* Transmit/Receive queue fifo size; use all RAM for 1 queue */
1104 1181 val = readl(&eqos->mac_regs->hw_feature1);
... ... @@ -1174,6 +1251,19 @@
1174 1251 eqos->config->config_mac <<
1175 1252 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
1176 1253  
  1254 + clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0,
  1255 + EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK <<
  1256 + EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT,
  1257 + 0x2 <<
  1258 + EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
  1259 +
  1260 + /* Multicast and Broadcast Queue Enable */
  1261 + setbits_le32(&eqos->mac_regs->unused_0a4,
  1262 + 0x00100000);
  1263 + /* enable promise mode */
  1264 + setbits_le32(&eqos->mac_regs->unused_004[1],
  1265 + 0x1);
  1266 +
1177 1267 /* Set TX flow control parameters */
1178 1268 /* Set Pause Time */
1179 1269 setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl,
... ... @@ -1251,6 +1341,11 @@
1251 1341 rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
1252 1342 (i * EQOS_MAX_PACKET_SIZE));
1253 1343 rx_desc->des3 |= EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
  1344 + mb();
  1345 + eqos->config->ops->eqos_flush_desc(rx_desc);
  1346 + eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf +
  1347 + (i * EQOS_MAX_PACKET_SIZE),
  1348 + EQOS_MAX_PACKET_SIZE);
1254 1349 }
1255 1350 eqos->config->ops->eqos_flush_desc(eqos->descs);
1256 1351  
1257 1352  
... ... @@ -1265,14 +1360,12 @@
1265 1360 &eqos->dma_regs->ch0_rxdesc_ring_length);
1266 1361  
1267 1362 /* Enable everything */
1268   -
1269   - setbits_le32(&eqos->mac_regs->configuration,
1270   - EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
1271   -
1272 1363 setbits_le32(&eqos->dma_regs->ch0_tx_control,
1273 1364 EQOS_DMA_CH0_TX_CONTROL_ST);
1274 1365 setbits_le32(&eqos->dma_regs->ch0_rx_control,
1275 1366 EQOS_DMA_CH0_RX_CONTROL_SR);
  1367 + setbits_le32(&eqos->mac_regs->configuration,
  1368 + EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
1276 1369  
1277 1370 /* TX tail pointer not written until we need to TX a packet */
1278 1371 /*
... ... @@ -1404,6 +1497,7 @@
1404 1497 debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags);
1405 1498  
1406 1499 rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
  1500 + eqos->config->ops->eqos_inval_desc(rx_desc);
1407 1501 if (rx_desc->des3 & EQOS_DESC3_OWN) {
1408 1502 debug("%s: RX packet not available\n", __func__);
1409 1503 return -EAGAIN;
... ... @@ -1435,6 +1529,8 @@
1435 1529 return -EINVAL;
1436 1530 }
1437 1531  
  1532 + eqos->config->ops->eqos_inval_buffer(packet, length);
  1533 +
1438 1534 rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
1439 1535 rx_desc->des0 = (u32)(ulong)packet;
1440 1536 rx_desc->des1 = 0;
1441 1537  
1442 1538  
... ... @@ -1682,17 +1778,42 @@
1682 1778 return PHY_INTERFACE_MODE_MII;
1683 1779 }
1684 1780  
  1781 +static int eqos_probe_resources_imx(struct udevice *dev)
  1782 +{
  1783 + struct eqos_priv *eqos = dev_get_priv(dev);
  1784 + phy_interface_t interface;
  1785 +
  1786 + debug("%s(dev=%p):\n", __func__, dev);
  1787 +
  1788 + interface = eqos->config->interface(dev);
  1789 +
  1790 + if (interface == PHY_INTERFACE_MODE_NONE) {
  1791 + pr_err("Invalid PHY interface\n");
  1792 + return -EINVAL;
  1793 + }
  1794 +
  1795 + debug("%s: OK\n", __func__);
  1796 + return 0;
  1797 +}
  1798 +
  1799 +static phy_interface_t eqos_get_interface_imx(struct udevice *dev)
  1800 +{
  1801 + return PHY_INTERFACE_MODE_RGMII;
  1802 +}
  1803 +
1685 1804 static int eqos_remove_resources_tegra186(struct udevice *dev)
1686 1805 {
1687 1806 struct eqos_priv *eqos = dev_get_priv(dev);
1688 1807  
1689 1808 debug("%s(dev=%p):\n", __func__, dev);
1690 1809  
  1810 +#ifdef CONFIG_CLK
1691 1811 clk_free(&eqos->clk_tx);
1692 1812 clk_free(&eqos->clk_ptp_ref);
1693 1813 clk_free(&eqos->clk_rx);
1694 1814 clk_free(&eqos->clk_slave_bus);
1695 1815 clk_free(&eqos->clk_master_bus);
  1816 +#endif
1696 1817 dm_gpio_free(dev, &eqos->phy_reset_gpio);
1697 1818 reset_free(&eqos->reset_ctl);
1698 1819  
... ... @@ -1702,6 +1823,7 @@
1702 1823  
1703 1824 static int eqos_remove_resources_stm32(struct udevice *dev)
1704 1825 {
  1826 +#ifdef CONFIG_CLK
1705 1827 struct eqos_priv *eqos = dev_get_priv(dev);
1706 1828  
1707 1829 debug("%s(dev=%p):\n", __func__, dev);
1708 1830  
... ... @@ -1711,11 +1833,17 @@
1711 1833 clk_free(&eqos->clk_master_bus);
1712 1834 if (clk_valid(&eqos->clk_ck))
1713 1835 clk_free(&eqos->clk_ck);
  1836 +#endif
1714 1837  
1715 1838 debug("%s: OK\n", __func__);
1716 1839 return 0;
1717 1840 }
1718 1841  
  1842 +static int eqos_remove_resources_imx(struct udevice *dev)
  1843 +{
  1844 + return 0;
  1845 +}
  1846 +
1719 1847 static int eqos_probe(struct udevice *dev)
1720 1848 {
1721 1849 struct eqos_priv *eqos = dev_get_priv(dev);
... ... @@ -1841,10 +1969,10 @@
1841 1969 };
1842 1970  
1843 1971 static struct eqos_ops eqos_stm32_ops = {
1844   - .eqos_inval_desc = eqos_inval_desc_stm32,
1845   - .eqos_flush_desc = eqos_flush_desc_stm32,
1846   - .eqos_inval_buffer = eqos_inval_buffer_stm32,
1847   - .eqos_flush_buffer = eqos_flush_buffer_stm32,
  1972 + .eqos_inval_desc = eqos_inval_desc_generic,
  1973 + .eqos_flush_desc = eqos_flush_desc_generic,
  1974 + .eqos_inval_buffer = eqos_inval_buffer_generic,
  1975 + .eqos_flush_buffer = eqos_flush_buffer_generic,
1848 1976 .eqos_probe_resources = eqos_probe_resources_stm32,
1849 1977 .eqos_remove_resources = eqos_remove_resources_stm32,
1850 1978 .eqos_stop_resets = eqos_stop_resets_stm32,
... ... @@ -1867,6 +1995,33 @@
1867 1995 .ops = &eqos_stm32_ops
1868 1996 };
1869 1997  
  1998 +static struct eqos_ops eqos_imx_ops = {
  1999 + .eqos_inval_desc = eqos_inval_desc_generic,
  2000 + .eqos_flush_desc = eqos_flush_desc_generic,
  2001 + .eqos_inval_buffer = eqos_inval_buffer_generic,
  2002 + .eqos_flush_buffer = eqos_flush_buffer_generic,
  2003 + .eqos_probe_resources = eqos_probe_resources_imx,
  2004 + .eqos_remove_resources = eqos_remove_resources_imx,
  2005 + .eqos_stop_resets = eqos_stop_resets_imx,
  2006 + .eqos_start_resets = eqos_start_resets_imx,
  2007 + .eqos_stop_clks = eqos_stop_clks_imx,
  2008 + .eqos_start_clks = eqos_start_clks_imx,
  2009 + .eqos_calibrate_pads = eqos_calibrate_pads_imx,
  2010 + .eqos_disable_calibration = eqos_disable_calibration_imx,
  2011 + .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_imx,
  2012 + .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx
  2013 +};
  2014 +
  2015 +struct eqos_config eqos_imx_config = {
  2016 + .reg_access_always_ok = false,
  2017 + .mdio_wait = 10000,
  2018 + .swr_wait = 50,
  2019 + .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
  2020 + .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
  2021 + .interface = eqos_get_interface_imx,
  2022 + .ops = &eqos_imx_ops
  2023 +};
  2024 +
1870 2025 static const struct udevice_id eqos_ids[] = {
1871 2026 {
1872 2027 .compatible = "nvidia,tegra186-eqos",
... ... @@ -1876,6 +2031,10 @@
1876 2031 .compatible = "snps,dwmac-4.20a",
1877 2032 .data = (ulong)&eqos_stm32_config
1878 2033 },
  2034 + {
  2035 + .compatible = "fsl,imx-eqos",
  2036 + .data = (ulong)&eqos_imx_config
  2037 + },
1879 2038  
1880 2039 { }
1881 2040 };
... ... @@ -1883,7 +2042,7 @@
1883 2042 U_BOOT_DRIVER(eth_eqos) = {
1884 2043 .name = "eth_eqos",
1885 2044 .id = UCLASS_ETH,
1886   - .of_match = eqos_ids,
  2045 + .of_match = of_match_ptr(eqos_ids),
1887 2046 .probe = eqos_probe,
1888 2047 .remove = eqos_remove,
1889 2048 .ops = &eqos_ops,