powerpc/mpc8xxx: Allow override DDR read-to-write turnaround time

Add this option to allow boards to override the default read-to-write turnaround time for better performance. Signed-off-by: York Sun <yorksun@freescale.com>

powerpc/mpc8xxx: Allow override DDR read-to-write turnaround time
Add this option to allow boards to override the default read-to-write turnaround time for better performance. Signed-off-by: York Sun <yorksun@freescale.com>
York Sun · Kumar Gala
1 parent 86dda50484
Showing 2 changed files with 6 additions and 0 deletions Side-by-side Diff
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
arch/powerpc/include/asm/fsl_ddr_sdram.h
@@ -267,6 +267,9 @@
 	tmrd_mclk = 2;
 #endif
  
+	if (popts->trwt_override)
+		trwt_mclk = popts->trwt;
+
 	ddr->timing_cfg_0 = (0
 		| ((trwt_mclk & 0x3) << 30)	/* RWT */
 		| ((twrt_mclk & 0x3) << 28)	/* WRT */
@@ -271,6 +271,9 @@
 	unsigned int rcw_2;
 	/* control register 1 */
 	unsigned int ddr_cdr1;
+
+	unsigned int trwt_override;
+	unsigned int trwt;			/* read-to-write turnaround */
 } memctl_options_t;
  
 extern phys_size_t fsl_ddr_sdram(void);
...	...	@@ -267,6 +267,9 @@
267	267	tmrd_mclk = 2;
268	268	#endif
269	269
	270	+ if (popts->trwt_override)
	271	+ trwt_mclk = popts->trwt;
	272	+
270	273	ddr->timing_cfg_0 = (0
271	274	\| ((trwt_mclk & 0x3) << 30) /* RWT */
272	275	\| ((twrt_mclk & 0x3) << 28) /* WRT */
...	...	@@ -271,6 +271,9 @@
271	271	unsigned int rcw_2;
272	272	/* control register 1 */
273	273	unsigned int ddr_cdr1;
	274	+
	275	+ unsigned int trwt_override;
	276	+ unsigned int trwt; /* read-to-write turnaround */
274	277	} memctl_options_t;
275	278
276	279	extern phys_size_t fsl_ddr_sdram(void);