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Commit 2404124c4777aa917ad95d25e78ca3ab03636132

Authored by Matthias Fuchs
Committed by Tom Rini
1 parent b5e7c84f72
Exists in v2017.01-smarct4x and in 38 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

ppc4xx: remove CMS700 board 

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>

Showing 9 changed files with 1 additions and 626 deletions Side-by-side Diff

arch/powerpc/cpu/ppc4xx/Kconfig
Diff comments   View file @ 2404124
... ... @@ -110,9 +110,6 @@
110 110 config TARGET_PPCHAMELEONEVB
111 111 bool "Support PPChameleonEVB"
112 112  
113   -config TARGET_CMS700
114   - bool "Support CMS700"
115   -
116 113 config TARGET_CPCI2DP
117 114 bool "Support CPCI2DP"
118 115  
... ... @@ -248,7 +245,6 @@
248 245 source "board/csb272/Kconfig"
249 246 source "board/csb472/Kconfig"
250 247 source "board/dave/PPChameleonEVB/Kconfig"
251   -source "board/esd/cms700/Kconfig"
252 248 source "board/esd/cpci2dp/Kconfig"
253 249 source "board/esd/cpci405/Kconfig"
254 250 source "board/esd/cpciiser4/Kconfig"
board/esd/cms700/Kconfig
View file @ 2404124
1   -if TARGET_CMS700
2   -
3   -config SYS_BOARD
4   - default "cms700"
5   -
6   -config SYS_VENDOR
7   - default "esd"
8   -
9   -config SYS_CONFIG_NAME
10   - default "CMS700"
11   -
12   -endif
board/esd/cms700/MAINTAINERS
View file @ 2404124
1   -CMS700 BOARD
2   -M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
3   -S: Maintained
4   -F: board/esd/cms700/
5   -F: include/configs/CMS700.h
6   -F: configs/CMS700_defconfig
board/esd/cms700/Makefile
View file @ 2404124
1   -#
2   -# (C) Copyright 2000-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -# Objects for Xilinx JTAG programming (CPLD)
9   -CPLD = ../common/xilinx_jtag/lenval.o \
10   - ../common/xilinx_jtag/micro.o \
11   - ../common/xilinx_jtag/ports.o
12   -
13   -obj-y = cms700.o flash.o \
14   - ../common/misc.o \
15   - $(CPLD) \
16   - ../common/esd405ep_nand.o \
board/esd/cms700/cms700.c
View file @ 2404124
1   -/*
2   - * (C) Copyright 2005-2007
3   - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -#include <asm/processor.h>
10   -#include <asm/io.h>
11   -#include <command.h>
12   -#include <malloc.h>
13   -
14   -DECLARE_GLOBAL_DATA_PTR;
15   -
16   -extern void lxt971_no_sleep(void);
17   -
18   -int board_early_init_f (void)
19   -{
20   - /*
21   - * IRQ 0-15 405GP internally generated; active high; level sensitive
22   - * IRQ 16 405GP internally generated; active low; level sensitive
23   - * IRQ 17-24 RESERVED
24   - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
25   - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
26   - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
27   - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
28   - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
29   - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
30   - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
31   - */
32   - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
33   - mtdcr(UIC0ER, 0x00000000); /* disable all ints */
34   - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
35   - mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
36   - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
37   - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
38   - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
39   -
40   - /*
41   - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
42   - */
43   - mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
44   -
45   - /*
46   - * Reset CPLD via GPIO12 (CS3) pin
47   - */
48   - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_PLD_RESET);
49   - udelay(1000); /* wait 1ms */
50   - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_PLD_RESET);
51   - udelay(1000); /* wait 1ms */
52   -
53   - return 0;
54   -}
55   -
56   -int misc_init_r (void)
57   -{
58   - /* adjust flash start and offset */
59   - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
60   - gd->bd->bi_flashoffset = 0;
61   -
62   - /*
63   - * Setup and enable EEPROM write protection
64   - */
65   - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
66   -
67   - return (0);
68   -}
69   -
70   -
71   -/*
72   - * Check Board Identity:
73   - */
74   -#define LED_REG (CONFIG_SYS_PLD_BASE + 0x1000)
75   -int checkboard (void)
76   -{
77   - char str[64];
78   - int flashcnt;
79   - int delay;
80   -
81   - puts ("Board: ");
82   -
83   - if (getenv_f("serial#", str, sizeof(str)) == -1) {
84   - puts ("### No HW ID - assuming CMS700");
85   - } else {
86   - puts(str);
87   - }
88   -
89   - printf(" (PLD-Version=%02d)\n",
90   - in_8((void *)(CONFIG_SYS_PLD_BASE + 0x1001)));
91   -
92   - /*
93   - * Flash LEDs
94   - */
95   - for (flashcnt = 0; flashcnt < 3; flashcnt++) {
96   - out_8((void *)LED_REG, 0x00); /* LEDs off */
97   - for (delay = 0; delay < 100; delay++)
98   - udelay(1000);
99   - out_8((void *)LED_REG, 0x0f); /* LEDs on */
100   - for (delay = 0; delay < 50; delay++)
101   - udelay(1000);
102   - }
103   - out_8((void *)LED_REG, 0x70);
104   -
105   - return 0;
106   -}
107   -
108   -/* ------------------------------------------------------------------------- */
109   -
110   -#if defined(CONFIG_SYS_EEPROM_WREN)
111   -/* Input: <dev_addr> I2C address of EEPROM device to enable.
112   - * <state> -1: deliver current state
113   - * 0: disable write
114   - * 1: enable write
115   - * Returns: -1: wrong device address
116   - * 0: dis-/en- able done
117   - * 0/1: current state if <state> was -1.
118   - */
119   -int eeprom_write_enable (unsigned dev_addr, int state)
120   -{
121   - if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
122   - return -1;
123   - } else {
124   - switch (state) {
125   - case 1:
126   - /* Enable write access, clear bit GPIO_SINT2. */
127   - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
128   - state = 0;
129   - break;
130   - case 0:
131   - /* Disable write access, set bit GPIO_SINT2. */
132   - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
133   - state = 0;
134   - break;
135   - default:
136   - /* Read current status back. */
137   - state = (0 == (in_be32((void *)GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
138   - break;
139   - }
140   - }
141   - return state;
142   -}
143   -
144   -int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
145   -{
146   - int query = argc == 1;
147   - int state = 0;
148   -
149   - if (query) {
150   - /* Query write access state. */
151   - state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
152   - if (state < 0) {
153   - puts ("Query of write access state failed.\n");
154   - } else {
155   - printf ("Write access for device 0x%0x is %sabled.\n",
156   - CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
157   - state = 0;
158   - }
159   - } else {
160   - if ('0' == argv[1][0]) {
161   - /* Disable write access. */
162   - state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
163   - } else {
164   - /* Enable write access. */
165   - state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
166   - }
167   - if (state < 0) {
168   - puts ("Setup of write access state failed.\n");
169   - }
170   - }
171   -
172   - return state;
173   -}
174   -
175   -U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
176   - "Enable / disable / query EEPROM write access",
177   - ""
178   -);
179   -#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
180   -
181   -/* ------------------------------------------------------------------------- */
182   -
183   -void reset_phy(void)
184   -{
185   -#ifdef CONFIG_LXT971_NO_SLEEP
186   -
187   - /*
188   - * Disable sleep mode in LXT971
189   - */
190   - lxt971_no_sleep();
191   -#endif
192   -}
board/esd/cms700/flash.c
View file @ 2404124
1   -/*
2   - * (C) Copyright 2001
3   - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -#include <asm/ppc4xx.h>
10   -#include <asm/processor.h>
11   -
12   -/*
13   - * include common flash code (for esd boards)
14   - */
15   -#include "../common/flash.c"
16   -
17   -/*-----------------------------------------------------------------------
18   - * Functions
19   - */
20   -static ulong flash_get_size (vu_long * addr, flash_info_t * info);
21   -static void flash_get_offsets (ulong base, flash_info_t * info);
22   -
23   -/*-----------------------------------------------------------------------
24   - */
25   -
26   -unsigned long flash_init (void)
27   -{
28   - unsigned long size_b0;
29   - int i;
30   - uint pbcr;
31   - unsigned long base_b0;
32   - int size_val = 0;
33   -
34   - /* Init: no FLASHes known */
35   - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
36   - flash_info[i].flash_id = FLASH_UNKNOWN;
37   - }
38   -
39   - /* Static FLASH Bank configuration here - FIXME XXX */
40   -
41   - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
42   -
43   - if (flash_info[0].flash_id == FLASH_UNKNOWN) {
44   - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
45   - size_b0, size_b0<<20);
46   - }
47   -
48   - /* Setup offsets */
49   - flash_get_offsets (-size_b0, &flash_info[0]);
50   -
51   - /* Re-do sizing to get full correct info */
52   - mtdcr(EBC0_CFGADDR, PB0CR);
53   - pbcr = mfdcr(EBC0_CFGDATA);
54   - mtdcr(EBC0_CFGADDR, PB0CR);
55   - base_b0 = -size_b0;
56   - switch (size_b0) {
57   - case 1 << 20:
58   - size_val = 0;
59   - break;
60   - case 2 << 20:
61   - size_val = 1;
62   - break;
63   - case 4 << 20:
64   - size_val = 2;
65   - break;
66   - case 8 << 20:
67   - size_val = 3;
68   - break;
69   - case 16 << 20:
70   - size_val = 4;
71   - break;
72   - }
73   - pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
74   - mtdcr(EBC0_CFGDATA, pbcr);
75   -
76   - /* Monitor protection ON by default */
77   - (void)flash_protect(FLAG_PROTECT_SET,
78   - -CONFIG_SYS_MONITOR_LEN,
79   - 0xffffffff,
80   - &flash_info[0]);
81   -
82   - flash_info[0].size = size_b0;
83   -
84   - return (size_b0);
85   -}
configs/CMS700_defconfig
View file @ 2404124
1   -CONFIG_PPC=y
2   -CONFIG_4xx=y
3   -CONFIG_TARGET_CMS700=y
doc/README.scrapyard
Diff comments   View file @ 2404124
... ... @@ -12,6 +12,7 @@
12 12  
13 13 Board Arch CPU Commit Removed Last known maintainer/contact
14 14 =================================================================================================
  15 +CMS700 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs@esd.eu>
15 16 ASH405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs@esd.eu>
16 17 AR405 ppc4xx 405gpr - - Matthias Fuchs <matthias.fuchs@esd.eu>
17 18 APC405 ppc4xx 405gpr - - Matthias Fuchs <matthias.fuchs@esd.eu>
include/configs/CMS700.h
View file @ 2404124
1   -/*
2   - * (C) Copyright 2005
3   - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -/*
9   - * CMS700.h - configuration options, board specific
10   - */
11   -
12   -#ifndef __CONFIG_H
13   -#define __CONFIG_H
14   -
15   -/*
16   - * High Level Configuration Options
17   - * (easy to change)
18   - */
19   -
20   -#define CONFIG_405EP 1 /* This is a PPC405 CPU */
21   -#define CONFIG_VOM405 1 /* ...on a VOM405 board */
22   -
23   -#define CONFIG_SYS_TEXT_BASE 0xFFFC8000
24   -
25   -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
26   -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
27   -
28   -#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
29   -
30   -#define CONFIG_BAUDRATE 9600
31   -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
32   -
33   -#undef CONFIG_BOOTARGS
34   -#undef CONFIG_BOOTCOMMAND
35   -
36   -#define CONFIG_PREBOOT /* enable preboot variable */
37   -
38   -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
39   -
40   -#define CONFIG_PPC4xx_EMAC
41   -#undef CONFIG_HAS_ETH1
42   -
43   -#define CONFIG_MII 1 /* MII PHY management */
44   -#define CONFIG_PHY_ADDR 0 /* PHY address */
45   -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
46   -#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
47   -
48   -/*
49   - * BOOTP options
50   - */
51   -#define CONFIG_BOOTP_SUBNETMASK
52   -#define CONFIG_BOOTP_GATEWAY
53   -#define CONFIG_BOOTP_HOSTNAME
54   -#define CONFIG_BOOTP_BOOTPATH
55   -#define CONFIG_BOOTP_DNS
56   -#define CONFIG_BOOTP_DNS2
57   -#define CONFIG_BOOTP_SEND_HOSTNAME
58   -
59   -
60   -/*
61   - * Command line configuration.
62   - */
63   -#include <config_cmd_default.h>
64   -
65   -#define CONFIG_CMD_DHCP
66   -#define CONFIG_CMD_BSP
67   -#define CONFIG_CMD_ELF
68   -#define CONFIG_CMD_NAND
69   -#define CONFIG_CMD_I2C
70   -#define CONFIG_CMD_DATE
71   -#define CONFIG_CMD_MII
72   -#define CONFIG_CMD_PING
73   -#define CONFIG_CMD_EEPROM
74   -
75   -
76   -#undef CONFIG_WATCHDOG /* watchdog disabled */
77   -
78   -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
79   -
80   -#undef CONFIG_PRAM /* no "protected RAM" */
81   -
82   -/*
83   - * Miscellaneous configurable options
84   - */
85   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
86   -
87   -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
88   -
89   -#if defined(CONFIG_CMD_KGDB)
90   -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
91   -#else
92   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
93   -#endif
94   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
95   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
96   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
97   -
98   -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
99   -
100   -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
101   -
102   -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
103   -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
104   -
105   -#define CONFIG_CONS_INDEX 2 /* Use UART1 */
106   -#define CONFIG_SYS_NS16550
107   -#define CONFIG_SYS_NS16550_SERIAL
108   -#define CONFIG_SYS_NS16550_REG_SIZE 1
109   -#define CONFIG_SYS_NS16550_CLK get_serial_clock()
110   -
111   -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
112   -#define CONFIG_SYS_BASE_BAUD 691200
113   -
114   -/* The following table includes the supported baudrates */
115   -#define CONFIG_SYS_BAUDRATE_TABLE \
116   - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
117   - 57600, 115200, 230400, 460800, 921600 }
118   -
119   -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
120   -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
121   -
122   -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
123   -
124   -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
125   -
126   -#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
127   -
128   -/*-----------------------------------------------------------------------
129   - * RTC stuff
130   - *-----------------------------------------------------------------------
131   - */
132   -#define CONFIG_RTC_DS1337
133   -#define CONFIG_SYS_I2C_RTC_ADDR 0x68
134   -
135   -/*-----------------------------------------------------------------------
136   - * NAND-FLASH stuff
137   - *-----------------------------------------------------------------------
138   - */
139   -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
140   -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
141   -#define NAND_BIG_DELAY_US 25
142   -
143   -#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
144   -#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
145   -#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
146   -#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
147   -
148   -#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
149   -#define CONFIG_SYS_NAND_QUIET 1
150   -
151   -#define CONFIG_SYS_NAND_MAX_OOBFREE 2
152   -#define CONFIG_SYS_NAND_MAX_ECCPOS 48
153   -
154   -/*
155   - * For booting Linux, the board info and command line data
156   - * have to be in the first 8 MB of memory, since this is
157   - * the maximum mapped by the Linux kernel during initialization.
158   - */
159   -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
160   -/*-----------------------------------------------------------------------
161   - * FLASH organization
162   - */
163   -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
164   -
165   -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
166   -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
167   -
168   -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
169   -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
170   -
171   -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
172   -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
173   -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
174   -/*
175   - * The following defines are added for buggy IOP480 byte interface.
176   - * All other boards should use the standard values (CPCI405 etc.)
177   - */
178   -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
179   -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
180   -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
181   -
182   -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
183   -
184   -/*-----------------------------------------------------------------------
185   - * Start addresses for the final memory configuration
186   - * (Set up by the startup code)
187   - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
188   - */
189   -#define CONFIG_SYS_SDRAM_BASE 0x00000000
190   -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
191   -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
192   -#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
193   -#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
194   -
195   -#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
196   -# define CONFIG_SYS_RAMBOOT 1
197   -#else
198   -# undef CONFIG_SYS_RAMBOOT
199   -#endif
200   -
201   -/*-----------------------------------------------------------------------
202   - * Environment Variable setup
203   - */
204   -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
205   -#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
206   -#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
207   - /* total size of a CAT24WC16 is 2048 bytes */
208   -
209   -/*-----------------------------------------------------------------------
210   - * I2C EEPROM (CAT24WC16) for environment
211   - */
212   -#define CONFIG_SYS_I2C
213   -#define CONFIG_SYS_I2C_PPC4XX
214   -#define CONFIG_SYS_I2C_PPC4XX_CH0
215   -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
216   -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
217   -
218   -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
219   -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
220   -/* mask of address bits that overflow into the "EEPROM chip address" */
221   -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
222   -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
223   - /* 16 byte page write mode using*/
224   - /* last 4 bits of the address */
225   -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
226   -
227   -#define CONFIG_SYS_EEPROM_WREN 1
228   -
229   -/*-----------------------------------------------------------------------
230   - * External Bus Controller (EBC) Setup
231   - */
232   -#define CONFIG_SYS_PLD_BASE 0xf0000000
233   -#define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
234   -
235   -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
236   -#define CONFIG_SYS_EBC_PB0AP 0x92015480
237   -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
238   -
239   -/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
240   -#define CONFIG_SYS_EBC_PB1AP 0x92015480
241   -#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
242   -
243   -/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
244   -#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
245   -#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
246   -
247   -/*-----------------------------------------------------------------------
248   - * FPGA stuff
249   - */
250   -#define CONFIG_SYS_XSVF_DEFAULT_ADDR 0xfffc0000
251   -
252   -/* FPGA program pin configuration */
253   -#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */
254   -#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */
255   -#define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */
256   -#define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */
257   -#define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */
258   -
259   -/*-----------------------------------------------------------------------
260   - * Definitions for initial stack pointer and data area (in data cache)
261   - */
262   -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
263   -#define CONFIG_SYS_TEMP_STACK_OCM 1
264   -
265   -/* On Chip Memory location */
266   -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
267   -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
268   -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
269   -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
270   -
271   -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
272   -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
273   -
274   -/*-----------------------------------------------------------------------
275   - * Definitions for GPIO setup (PPC405EP specific)
276   - *
277   - * GPIO0[0] - External Bus Controller BLAST output
278   - * GPIO0[1-9] - Instruction trace outputs -> GPIO
279   - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
280   - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
281   - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
282   - * GPIO0[24-27] - UART0 control signal inputs/outputs
283   - * GPIO0[28-29] - UART1 data signal input/output
284   - * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
285   - */
286   -/* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */
287   -/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */
288   -/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */
289   -/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
290   -#define CONFIG_SYS_GPIO0_OSRL 0x40000500 /* 0 ... 15 */
291   -#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */
292   -#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */
293   -#define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */
294   -#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */
295   -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */
296   -#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */
297   -
298   -#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */
299   -#define CONFIG_SYS_PLD_RESET (0x80000000 >> 12) /* GPIO12 */
300   -
301   -/*
302   - * Default speed selection (cpu_plb_opb_ebc) in mhz.
303   - * This value will be set if iic boot eprom is disabled.
304   - */
305   -#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
306   -#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
307   -
308   -#endif /* __CONFIG_H */