Eric Lee / smarc-uboot

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Commit 2459afb1a783e34d37c0f7aeec43c77f4de4d480

Authored by Qianyu Gong
Committed by York Sun
1 parent 9f3e1b8a55
Exists in v2017.01-smarct4x and in 30 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

qe: move drivers/qe/qe.h to include/fsl_qe.h 

As the QE firmware struct is shared with Fman, move the header file
out of drivers/qe/.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

Showing 16 changed files with 313 additions and 313 deletions Side-by-side Diff

arch/powerpc/cpu/mpc85xx/cpu_init.c
Diff comments   View file @ 2459afb
... ... @@ -48,7 +48,7 @@
48 48  
49 49 #include "../../../../drivers/block/fsl_sata.h"
50 50 #ifdef CONFIG_U_QE
51   -#include "../../../../drivers/qe/qe.h"
  51 +#include <fsl_qe.h>
52 52 #endif
53 53  
54 54 DECLARE_GLOBAL_DATA_PTR;
arch/powerpc/cpu/mpc85xx/fdt.c
Diff comments   View file @ 2459afb
... ... @@ -19,7 +19,7 @@
19 19 #ifdef CONFIG_FSL_ESDHC
20 20 #include <fsl_esdhc.h>
21 21 #endif
22   -#include "../../../../drivers/qe/qe.h" /* For struct qe_firmware */
  22 +#include <fsl_qe.h> /* For struct qe_firmware */
23 23  
24 24 DECLARE_GLOBAL_DATA_PTR;
25 25  
board/freescale/common/arm_sleep.c
Diff comments   View file @ 2459afb
... ... @@ -19,7 +19,7 @@
19 19  
20 20 #include "sleep.h"
21 21 #ifdef CONFIG_U_QE
22   -#include "../../../drivers/qe/qe.h"
  22 +#include <fsl_qe.h>
23 23 #endif
24 24  
25 25 DECLARE_GLOBAL_DATA_PTR;
board/freescale/common/mpc85xx_sleep.c
Diff comments   View file @ 2459afb
... ... @@ -8,7 +8,7 @@
8 8 #include <asm/immap_85xx.h>
9 9 #include "sleep.h"
10 10 #ifdef CONFIG_U_QE
11   -#include "../../../drivers/qe/qe.h"
  11 +#include <fsl_qe.h>
12 12 #endif
13 13  
14 14 DECLARE_GLOBAL_DATA_PTR;
board/freescale/ls1021aqds/ls1021aqds.c
Diff comments   View file @ 2459afb
... ... @@ -28,7 +28,7 @@
28 28 #include "../common/qixis.h"
29 29 #include "ls1021aqds_qixis.h"
30 30 #ifdef CONFIG_U_QE
31   -#include "../../../drivers/qe/qe.h"
  31 +#include <fsl_qe.h>
32 32 #endif
33 33  
34 34 #define PIN_MUX_SEL_CAN 0x03
board/freescale/ls1021atwr/ls1021atwr.c
Diff comments   View file @ 2459afb
... ... @@ -28,7 +28,7 @@
28 28 #include <spl.h>
29 29 #include "../common/sleep.h"
30 30 #ifdef CONFIG_U_QE
31   -#include "../../../drivers/qe/qe.h"
  31 +#include <fsl_qe.h>
32 32 #endif
33 33 #include <fsl_validate.h>
34 34  
... ... @@ -10,7 +10,7 @@
10 10 #include <asm/errno.h>
11 11  
12 12 #include "fm.h"
13   -#include "../../qe/qe.h" /* For struct qe_firmware */
  13 +#include <fsl_qe.h> /* For struct qe_firmware */
14 14  
15 15 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
16 16 #include <nand.h>
... ... @@ -10,7 +10,7 @@
10 10 #include <common.h>
11 11 #include <libfdt.h>
12 12 #include <fdt_support.h>
13   -#include "qe.h"
  13 +#include <fsl_qe.h>
14 14  
15 15 #ifdef CONFIG_QE
16 16 DECLARE_GLOBAL_DATA_PTR;
... ... @@ -12,7 +12,7 @@
12 12 #include "asm/errno.h"
13 13 #include "asm/io.h"
14 14 #include "linux/immap_qe.h"
15   -#include "qe.h"
  15 +#include <fsl_qe.h>
16 16 #ifdef CONFIG_LS102XA
17 17 #include <asm/arch/immap_ls102xa.h>
18 18 #endif
drivers/qe/qe.h
View file @ 2459afb
1   -/*
2   - * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
3   - *
4   - * Dave Liu <daveliu@freescale.com>
5   - * based on source code of Shlomi Gridish
6   - *
7   - * SPDX-License-Identifier: GPL-2.0+
8   - */
9   -
10   -#ifndef __QE_H__
11   -#define __QE_H__
12   -
13   -#include "common.h"
14   -#ifdef CONFIG_U_QE
15   -#include <linux/immap_qe.h>
16   -#endif
17   -
18   -#define QE_NUM_OF_BRGS 16
19   -#define UCC_MAX_NUM 8
20   -
21   -#define QE_DATAONLY_BASE 0
22   -#define QE_DATAONLY_SIZE (QE_MURAM_SIZE - QE_DATAONLY_BASE)
23   -
24   -/* QE threads SNUM
25   -*/
26   -typedef enum qe_snum_state {
27   - QE_SNUM_STATE_USED, /* used */
28   - QE_SNUM_STATE_FREE /* free */
29   -} qe_snum_state_e;
30   -
31   -typedef struct qe_snum {
32   - u8 num; /* snum */
33   - qe_snum_state_e state; /* state */
34   -} qe_snum_t;
35   -
36   -/* QE RISC allocation
37   -*/
38   -#define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
39   -#define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
40   -#define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
41   -#define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */
42   -#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \
43   - QE_RISC_ALLOCATION_RISC2)
44   -#define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \
45   - QE_RISC_ALLOCATION_RISC2 | \
46   - QE_RISC_ALLOCATION_RISC3 | \
47   - QE_RISC_ALLOCATION_RISC4)
48   -
49   -/* QE CECR commands for UCC fast.
50   -*/
51   -#define QE_CR_FLG 0x00010000
52   -#define QE_RESET 0x80000000
53   -#define QE_INIT_TX_RX 0x00000000
54   -#define QE_INIT_RX 0x00000001
55   -#define QE_INIT_TX 0x00000002
56   -#define QE_ENTER_HUNT_MODE 0x00000003
57   -#define QE_STOP_TX 0x00000004
58   -#define QE_GRACEFUL_STOP_TX 0x00000005
59   -#define QE_RESTART_TX 0x00000006
60   -#define QE_SWITCH_COMMAND 0x00000007
61   -#define QE_SET_GROUP_ADDRESS 0x00000008
62   -#define QE_INSERT_CELL 0x00000009
63   -#define QE_ATM_TRANSMIT 0x0000000a
64   -#define QE_CELL_POOL_GET 0x0000000b
65   -#define QE_CELL_POOL_PUT 0x0000000c
66   -#define QE_IMA_HOST_CMD 0x0000000d
67   -#define QE_ATM_MULTI_THREAD_INIT 0x00000011
68   -#define QE_ASSIGN_PAGE 0x00000012
69   -#define QE_START_FLOW_CONTROL 0x00000014
70   -#define QE_STOP_FLOW_CONTROL 0x00000015
71   -#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016
72   -#define QE_GRACEFUL_STOP_RX 0x0000001a
73   -#define QE_RESTART_RX 0x0000001b
74   -
75   -/* QE CECR Sub Block Code - sub block code of QE command.
76   -*/
77   -#define QE_CR_SUBBLOCK_INVALID 0x00000000
78   -#define QE_CR_SUBBLOCK_USB 0x03200000
79   -#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000
80   -#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000
81   -#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000
82   -#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000
83   -#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000
84   -#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000
85   -#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000
86   -#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000
87   -#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000
88   -#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000
89   -#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000
90   -#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000
91   -#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000
92   -#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000
93   -#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000
94   -#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000
95   -#define QE_CR_SUBBLOCK_MCC1 0x03800000
96   -#define QE_CR_SUBBLOCK_MCC2 0x03a00000
97   -#define QE_CR_SUBBLOCK_MCC3 0x03000000
98   -#define QE_CR_SUBBLOCK_IDMA1 0x02800000
99   -#define QE_CR_SUBBLOCK_IDMA2 0x02a00000
100   -#define QE_CR_SUBBLOCK_IDMA3 0x02c00000
101   -#define QE_CR_SUBBLOCK_IDMA4 0x02e00000
102   -#define QE_CR_SUBBLOCK_HPAC 0x01e00000
103   -#define QE_CR_SUBBLOCK_SPI1 0x01400000
104   -#define QE_CR_SUBBLOCK_SPI2 0x01600000
105   -#define QE_CR_SUBBLOCK_RAND 0x01c00000
106   -#define QE_CR_SUBBLOCK_TIMER 0x01e00000
107   -#define QE_CR_SUBBLOCK_GENERAL 0x03c00000
108   -
109   -/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command.
110   -*/
111   -#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */
112   -#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
113   -#define QE_CR_PROTOCOL_ATM_POS 0x0A
114   -#define QE_CR_PROTOCOL_ETHERNET 0x0C
115   -#define QE_CR_PROTOCOL_L2_SWITCH 0x0D
116   -#define QE_CR_PROTOCOL_SHIFT 6
117   -
118   -/* QE ASSIGN PAGE command
119   -*/
120   -#define QE_CR_ASSIGN_PAGE_SNUM_SHIFT 17
121   -
122   -/* Communication Direction.
123   -*/
124   -typedef enum comm_dir {
125   - COMM_DIR_NONE = 0,
126   - COMM_DIR_RX = 1,
127   - COMM_DIR_TX = 2,
128   - COMM_DIR_RX_AND_TX = 3
129   -} comm_dir_e;
130   -
131   -/* Clocks and BRG's
132   -*/
133   -typedef enum qe_clock {
134   - QE_CLK_NONE = 0,
135   - QE_BRG1, /* Baud Rate Generator 1 */
136   - QE_BRG2, /* Baud Rate Generator 2 */
137   - QE_BRG3, /* Baud Rate Generator 3 */
138   - QE_BRG4, /* Baud Rate Generator 4 */
139   - QE_BRG5, /* Baud Rate Generator 5 */
140   - QE_BRG6, /* Baud Rate Generator 6 */
141   - QE_BRG7, /* Baud Rate Generator 7 */
142   - QE_BRG8, /* Baud Rate Generator 8 */
143   - QE_BRG9, /* Baud Rate Generator 9 */
144   - QE_BRG10, /* Baud Rate Generator 10 */
145   - QE_BRG11, /* Baud Rate Generator 11 */
146   - QE_BRG12, /* Baud Rate Generator 12 */
147   - QE_BRG13, /* Baud Rate Generator 13 */
148   - QE_BRG14, /* Baud Rate Generator 14 */
149   - QE_BRG15, /* Baud Rate Generator 15 */
150   - QE_BRG16, /* Baud Rate Generator 16 */
151   - QE_CLK1, /* Clock 1 */
152   - QE_CLK2, /* Clock 2 */
153   - QE_CLK3, /* Clock 3 */
154   - QE_CLK4, /* Clock 4 */
155   - QE_CLK5, /* Clock 5 */
156   - QE_CLK6, /* Clock 6 */
157   - QE_CLK7, /* Clock 7 */
158   - QE_CLK8, /* Clock 8 */
159   - QE_CLK9, /* Clock 9 */
160   - QE_CLK10, /* Clock 10 */
161   - QE_CLK11, /* Clock 11 */
162   - QE_CLK12, /* Clock 12 */
163   - QE_CLK13, /* Clock 13 */
164   - QE_CLK14, /* Clock 14 */
165   - QE_CLK15, /* Clock 15 */
166   - QE_CLK16, /* Clock 16 */
167   - QE_CLK17, /* Clock 17 */
168   - QE_CLK18, /* Clock 18 */
169   - QE_CLK19, /* Clock 19 */
170   - QE_CLK20, /* Clock 20 */
171   - QE_CLK21, /* Clock 21 */
172   - QE_CLK22, /* Clock 22 */
173   - QE_CLK23, /* Clock 23 */
174   - QE_CLK24, /* Clock 24 */
175   - QE_CLK_DUMMY
176   -} qe_clock_e;
177   -
178   -/* QE CMXGCR register
179   -*/
180   -#define QE_CMXGCR_MII_ENET_MNG_MASK 0x00007000
181   -#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12
182   -
183   -/* QE CMXUCR registers
184   - */
185   -#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F
186   -
187   -/* QE BRG configuration register
188   -*/
189   -#define QE_BRGC_ENABLE 0x00010000
190   -#define QE_BRGC_DIVISOR_SHIFT 1
191   -#define QE_BRGC_DIVISOR_MAX 0xFFF
192   -#define QE_BRGC_DIV16 1
193   -
194   -/* QE SDMA registers
195   -*/
196   -#define QE_SDSR_BER1 0x02000000
197   -#define QE_SDSR_BER2 0x01000000
198   -
199   -#define QE_SDMR_GLB_1_MSK 0x80000000
200   -#define QE_SDMR_ADR_SEL 0x20000000
201   -#define QE_SDMR_BER1_MSK 0x02000000
202   -#define QE_SDMR_BER2_MSK 0x01000000
203   -#define QE_SDMR_EB1_MSK 0x00800000
204   -#define QE_SDMR_ER1_MSK 0x00080000
205   -#define QE_SDMR_ER2_MSK 0x00040000
206   -#define QE_SDMR_CEN_MASK 0x0000E000
207   -#define QE_SDMR_SBER_1 0x00000200
208   -#define QE_SDMR_SBER_2 0x00000200
209   -#define QE_SDMR_EB1_PR_MASK 0x000000C0
210   -#define QE_SDMR_ER1_PR 0x00000008
211   -
212   -#define QE_SDMR_CEN_SHIFT 13
213   -#define QE_SDMR_EB1_PR_SHIFT 6
214   -
215   -#define QE_SDTM_MSNUM_SHIFT 24
216   -
217   -#define QE_SDEBCR_BA_MASK 0x01FFFFFF
218   -
219   -/* Communication Processor */
220   -#define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */
221   -#define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */
222   -#define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */
223   -
224   -/* I-RAM */
225   -#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */
226   -#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */
227   -#define QE_IRAM_READY 0x80000000
228   -
229   -/* Structure that defines QE firmware binary files.
230   - *
231   - * See doc/README.qe_firmware for a description of these fields.
232   - */
233   -struct qe_firmware {
234   - struct qe_header {
235   - u32 length; /* Length of the entire structure, in bytes */
236   - u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */
237   - u8 version; /* Version of this layout. First ver is '1' */
238   - } header;
239   - u8 id[62]; /* Null-terminated identifier string */
240   - u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
241   - u8 count; /* Number of microcode[] structures */
242   - struct {
243   - u16 model; /* The SOC model */
244   - u8 major; /* The SOC revision major */
245   - u8 minor; /* The SOC revision minor */
246   - } __attribute__ ((packed)) soc;
247   - u8 padding[4]; /* Reserved, for alignment */
248   - u64 extended_modes; /* Extended modes */
249   - u32 vtraps[8]; /* Virtual trap addresses */
250   - u8 reserved[4]; /* Reserved, for future expansion */
251   - struct qe_microcode {
252   - u8 id[32]; /* Null-terminated identifier */
253   - u32 traps[16]; /* Trap addresses, 0 == ignore */
254   - u32 eccr; /* The value for the ECCR register */
255   - u32 iram_offset;/* Offset into I-RAM for the code */
256   - u32 count; /* Number of 32-bit words of the code */
257   - u32 code_offset;/* Offset of the actual microcode */
258   - u8 major; /* The microcode version major */
259   - u8 minor; /* The microcode version minor */
260   - u8 revision; /* The microcode version revision */
261   - u8 padding; /* Reserved, for alignment */
262   - u8 reserved[4]; /* Reserved, for future expansion */
263   - } __attribute__ ((packed)) microcode[1];
264   - /* All microcode binaries should be located here */
265   - /* CRC32 should be located here, after the microcode binaries */
266   -} __attribute__ ((packed));
267   -
268   -struct qe_firmware_info {
269   - char id[64]; /* Firmware name */
270   - u32 vtraps[8]; /* Virtual trap addresses */
271   - u64 extended_modes; /* Extended modes */
272   -};
273   -
274   -void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign);
275   -void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data);
276   -uint qe_muram_alloc(uint size, uint align);
277   -void *qe_muram_addr(uint offset);
278   -int qe_get_snum(void);
279   -void qe_put_snum(u8 snum);
280   -void qe_init(uint qe_base);
281   -void qe_reset(void);
282   -void qe_assign_page(uint snum, uint para_ram_base);
283   -int qe_set_brg(uint brg, uint rate);
284   -int qe_set_mii_clk_src(int ucc_num);
285   -int qe_upload_firmware(const struct qe_firmware *firmware);
286   -struct qe_firmware_info *qe_get_firmware_info(void);
287   -void ft_qe_setup(void *blob);
288   -void qe_init(uint qe_base);
289   -void qe_reset(void);
290   -
291   -#ifdef CONFIG_U_QE
292   -void u_qe_init(void);
293   -int u_qe_upload_firmware(const struct qe_firmware *firmware);
294   -void u_qe_resume(void);
295   -int u_qe_firmware_resume(const struct qe_firmware *firmware,
296   - qe_map_t *qe_immrr);
297   -#endif
298   -
299   -#endif /* __QE_H__ */
... ... @@ -12,8 +12,8 @@
12 12 #include "asm/errno.h"
13 13 #include "asm/io.h"
14 14 #include "linux/immap_qe.h"
15   -#include "qe.h"
16 15 #include "uccf.h"
  16 +#include <fsl_qe.h>
17 17  
18 18 void ucc_fast_transmit_on_demand(ucc_fast_private_t *uccf)
19 19 {
... ... @@ -11,8 +11,8 @@
11 11 #define __UCCF_H__
12 12  
13 13 #include "common.h"
14   -#include "qe.h"
15 14 #include "linux/immap_qe.h"
  15 +#include <fsl_qe.h>
16 16  
17 17 /* Fast or Giga ethernet
18 18 */
... ... @@ -12,11 +12,11 @@
12 12 #include "asm/errno.h"
13 13 #include "asm/io.h"
14 14 #include "linux/immap_qe.h"
15   -#include "qe.h"
16 15 #include "uccf.h"
17 16 #include "uec.h"
18 17 #include "uec_phy.h"
19 18 #include "miiphy.h"
  19 +#include <fsl_qe.h>
20 20 #include <phy.h>
21 21  
22 22 /* Default UTBIPAR SMI address */
... ... @@ -10,8 +10,8 @@
10 10 #ifndef __UEC_H__
11 11 #define __UEC_H__
12 12  
13   -#include "qe.h"
14 13 #include "uccf.h"
  14 +#include <fsl_qe.h>
15 15 #include <phy.h>
16 16  
17 17 #define MAX_TX_THREADS 8
drivers/qe/uec_phy.c
Diff comments   View file @ 2459afb
... ... @@ -16,11 +16,11 @@
16 16 #include "asm/errno.h"
17 17 #include "linux/immap_qe.h"
18 18 #include "asm/io.h"
19   -#include "qe.h"
20 19 #include "uccf.h"
21 20 #include "uec.h"
22 21 #include "uec_phy.h"
23 22 #include "miiphy.h"
  23 +#include <fsl_qe.h>
24 24 #include <phy.h>
25 25  
26 26 #define ugphy_printk(format, arg...) \
  1 +/*
  2 + * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
  3 + *
  4 + * Dave Liu <daveliu@freescale.com>
  5 + * based on source code of Shlomi Gridish
  6 + *
  7 + * SPDX-License-Identifier: GPL-2.0+
  8 + */
  9 +
  10 +#ifndef __QE_H__
  11 +#define __QE_H__
  12 +
  13 +#include "common.h"
  14 +#ifdef CONFIG_U_QE
  15 +#include <linux/immap_qe.h>
  16 +#endif
  17 +
  18 +#define QE_NUM_OF_BRGS 16
  19 +#define UCC_MAX_NUM 8
  20 +
  21 +#define QE_DATAONLY_BASE 0
  22 +#define QE_DATAONLY_SIZE (QE_MURAM_SIZE - QE_DATAONLY_BASE)
  23 +
  24 +/* QE threads SNUM
  25 +*/
  26 +typedef enum qe_snum_state {
  27 + QE_SNUM_STATE_USED, /* used */
  28 + QE_SNUM_STATE_FREE /* free */
  29 +} qe_snum_state_e;
  30 +
  31 +typedef struct qe_snum {
  32 + u8 num; /* snum */
  33 + qe_snum_state_e state; /* state */
  34 +} qe_snum_t;
  35 +
  36 +/* QE RISC allocation
  37 +*/
  38 +#define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
  39 +#define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
  40 +#define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
  41 +#define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */
  42 +#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \
  43 + QE_RISC_ALLOCATION_RISC2)
  44 +#define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \
  45 + QE_RISC_ALLOCATION_RISC2 | \
  46 + QE_RISC_ALLOCATION_RISC3 | \
  47 + QE_RISC_ALLOCATION_RISC4)
  48 +
  49 +/* QE CECR commands for UCC fast.
  50 +*/
  51 +#define QE_CR_FLG 0x00010000
  52 +#define QE_RESET 0x80000000
  53 +#define QE_INIT_TX_RX 0x00000000
  54 +#define QE_INIT_RX 0x00000001
  55 +#define QE_INIT_TX 0x00000002
  56 +#define QE_ENTER_HUNT_MODE 0x00000003
  57 +#define QE_STOP_TX 0x00000004
  58 +#define QE_GRACEFUL_STOP_TX 0x00000005
  59 +#define QE_RESTART_TX 0x00000006
  60 +#define QE_SWITCH_COMMAND 0x00000007
  61 +#define QE_SET_GROUP_ADDRESS 0x00000008
  62 +#define QE_INSERT_CELL 0x00000009
  63 +#define QE_ATM_TRANSMIT 0x0000000a
  64 +#define QE_CELL_POOL_GET 0x0000000b
  65 +#define QE_CELL_POOL_PUT 0x0000000c
  66 +#define QE_IMA_HOST_CMD 0x0000000d
  67 +#define QE_ATM_MULTI_THREAD_INIT 0x00000011
  68 +#define QE_ASSIGN_PAGE 0x00000012
  69 +#define QE_START_FLOW_CONTROL 0x00000014
  70 +#define QE_STOP_FLOW_CONTROL 0x00000015
  71 +#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016
  72 +#define QE_GRACEFUL_STOP_RX 0x0000001a
  73 +#define QE_RESTART_RX 0x0000001b
  74 +
  75 +/* QE CECR Sub Block Code - sub block code of QE command.
  76 +*/
  77 +#define QE_CR_SUBBLOCK_INVALID 0x00000000
  78 +#define QE_CR_SUBBLOCK_USB 0x03200000
  79 +#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000
  80 +#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000
  81 +#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000
  82 +#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000
  83 +#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000
  84 +#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000
  85 +#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000
  86 +#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000
  87 +#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000
  88 +#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000
  89 +#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000
  90 +#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000
  91 +#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000
  92 +#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000
  93 +#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000
  94 +#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000
  95 +#define QE_CR_SUBBLOCK_MCC1 0x03800000
  96 +#define QE_CR_SUBBLOCK_MCC2 0x03a00000
  97 +#define QE_CR_SUBBLOCK_MCC3 0x03000000
  98 +#define QE_CR_SUBBLOCK_IDMA1 0x02800000
  99 +#define QE_CR_SUBBLOCK_IDMA2 0x02a00000
  100 +#define QE_CR_SUBBLOCK_IDMA3 0x02c00000
  101 +#define QE_CR_SUBBLOCK_IDMA4 0x02e00000
  102 +#define QE_CR_SUBBLOCK_HPAC 0x01e00000
  103 +#define QE_CR_SUBBLOCK_SPI1 0x01400000
  104 +#define QE_CR_SUBBLOCK_SPI2 0x01600000
  105 +#define QE_CR_SUBBLOCK_RAND 0x01c00000
  106 +#define QE_CR_SUBBLOCK_TIMER 0x01e00000
  107 +#define QE_CR_SUBBLOCK_GENERAL 0x03c00000
  108 +
  109 +/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command.
  110 +*/
  111 +#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */
  112 +#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
  113 +#define QE_CR_PROTOCOL_ATM_POS 0x0A
  114 +#define QE_CR_PROTOCOL_ETHERNET 0x0C
  115 +#define QE_CR_PROTOCOL_L2_SWITCH 0x0D
  116 +#define QE_CR_PROTOCOL_SHIFT 6
  117 +
  118 +/* QE ASSIGN PAGE command
  119 +*/
  120 +#define QE_CR_ASSIGN_PAGE_SNUM_SHIFT 17
  121 +
  122 +/* Communication Direction.
  123 +*/
  124 +typedef enum comm_dir {
  125 + COMM_DIR_NONE = 0,
  126 + COMM_DIR_RX = 1,
  127 + COMM_DIR_TX = 2,
  128 + COMM_DIR_RX_AND_TX = 3
  129 +} comm_dir_e;
  130 +
  131 +/* Clocks and BRG's
  132 +*/
  133 +typedef enum qe_clock {
  134 + QE_CLK_NONE = 0,
  135 + QE_BRG1, /* Baud Rate Generator 1 */
  136 + QE_BRG2, /* Baud Rate Generator 2 */
  137 + QE_BRG3, /* Baud Rate Generator 3 */
  138 + QE_BRG4, /* Baud Rate Generator 4 */
  139 + QE_BRG5, /* Baud Rate Generator 5 */
  140 + QE_BRG6, /* Baud Rate Generator 6 */
  141 + QE_BRG7, /* Baud Rate Generator 7 */
  142 + QE_BRG8, /* Baud Rate Generator 8 */
  143 + QE_BRG9, /* Baud Rate Generator 9 */
  144 + QE_BRG10, /* Baud Rate Generator 10 */
  145 + QE_BRG11, /* Baud Rate Generator 11 */
  146 + QE_BRG12, /* Baud Rate Generator 12 */
  147 + QE_BRG13, /* Baud Rate Generator 13 */
  148 + QE_BRG14, /* Baud Rate Generator 14 */
  149 + QE_BRG15, /* Baud Rate Generator 15 */
  150 + QE_BRG16, /* Baud Rate Generator 16 */
  151 + QE_CLK1, /* Clock 1 */
  152 + QE_CLK2, /* Clock 2 */
  153 + QE_CLK3, /* Clock 3 */
  154 + QE_CLK4, /* Clock 4 */
  155 + QE_CLK5, /* Clock 5 */
  156 + QE_CLK6, /* Clock 6 */
  157 + QE_CLK7, /* Clock 7 */
  158 + QE_CLK8, /* Clock 8 */
  159 + QE_CLK9, /* Clock 9 */
  160 + QE_CLK10, /* Clock 10 */
  161 + QE_CLK11, /* Clock 11 */
  162 + QE_CLK12, /* Clock 12 */
  163 + QE_CLK13, /* Clock 13 */
  164 + QE_CLK14, /* Clock 14 */
  165 + QE_CLK15, /* Clock 15 */
  166 + QE_CLK16, /* Clock 16 */
  167 + QE_CLK17, /* Clock 17 */
  168 + QE_CLK18, /* Clock 18 */
  169 + QE_CLK19, /* Clock 19 */
  170 + QE_CLK20, /* Clock 20 */
  171 + QE_CLK21, /* Clock 21 */
  172 + QE_CLK22, /* Clock 22 */
  173 + QE_CLK23, /* Clock 23 */
  174 + QE_CLK24, /* Clock 24 */
  175 + QE_CLK_DUMMY
  176 +} qe_clock_e;
  177 +
  178 +/* QE CMXGCR register
  179 +*/
  180 +#define QE_CMXGCR_MII_ENET_MNG_MASK 0x00007000
  181 +#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12
  182 +
  183 +/* QE CMXUCR registers
  184 + */
  185 +#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F
  186 +
  187 +/* QE BRG configuration register
  188 +*/
  189 +#define QE_BRGC_ENABLE 0x00010000
  190 +#define QE_BRGC_DIVISOR_SHIFT 1
  191 +#define QE_BRGC_DIVISOR_MAX 0xFFF
  192 +#define QE_BRGC_DIV16 1
  193 +
  194 +/* QE SDMA registers
  195 +*/
  196 +#define QE_SDSR_BER1 0x02000000
  197 +#define QE_SDSR_BER2 0x01000000
  198 +
  199 +#define QE_SDMR_GLB_1_MSK 0x80000000
  200 +#define QE_SDMR_ADR_SEL 0x20000000
  201 +#define QE_SDMR_BER1_MSK 0x02000000
  202 +#define QE_SDMR_BER2_MSK 0x01000000
  203 +#define QE_SDMR_EB1_MSK 0x00800000
  204 +#define QE_SDMR_ER1_MSK 0x00080000
  205 +#define QE_SDMR_ER2_MSK 0x00040000
  206 +#define QE_SDMR_CEN_MASK 0x0000E000
  207 +#define QE_SDMR_SBER_1 0x00000200
  208 +#define QE_SDMR_SBER_2 0x00000200
  209 +#define QE_SDMR_EB1_PR_MASK 0x000000C0
  210 +#define QE_SDMR_ER1_PR 0x00000008
  211 +
  212 +#define QE_SDMR_CEN_SHIFT 13
  213 +#define QE_SDMR_EB1_PR_SHIFT 6
  214 +
  215 +#define QE_SDTM_MSNUM_SHIFT 24
  216 +
  217 +#define QE_SDEBCR_BA_MASK 0x01FFFFFF
  218 +
  219 +/* Communication Processor */
  220 +#define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */
  221 +#define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */
  222 +#define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */
  223 +
  224 +/* I-RAM */
  225 +#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */
  226 +#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */
  227 +#define QE_IRAM_READY 0x80000000
  228 +
  229 +/* Structure that defines QE firmware binary files.
  230 + *
  231 + * See doc/README.qe_firmware for a description of these fields.
  232 + */
  233 +struct qe_firmware {
  234 + struct qe_header {
  235 + u32 length; /* Length of the entire structure, in bytes */
  236 + u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */
  237 + u8 version; /* Version of this layout. First ver is '1' */
  238 + } header;
  239 + u8 id[62]; /* Null-terminated identifier string */
  240 + u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
  241 + u8 count; /* Number of microcode[] structures */
  242 + struct {
  243 + u16 model; /* The SOC model */
  244 + u8 major; /* The SOC revision major */
  245 + u8 minor; /* The SOC revision minor */
  246 + } __attribute__ ((packed)) soc;
  247 + u8 padding[4]; /* Reserved, for alignment */
  248 + u64 extended_modes; /* Extended modes */
  249 + u32 vtraps[8]; /* Virtual trap addresses */
  250 + u8 reserved[4]; /* Reserved, for future expansion */
  251 + struct qe_microcode {
  252 + u8 id[32]; /* Null-terminated identifier */
  253 + u32 traps[16]; /* Trap addresses, 0 == ignore */
  254 + u32 eccr; /* The value for the ECCR register */
  255 + u32 iram_offset;/* Offset into I-RAM for the code */
  256 + u32 count; /* Number of 32-bit words of the code */
  257 + u32 code_offset;/* Offset of the actual microcode */
  258 + u8 major; /* The microcode version major */
  259 + u8 minor; /* The microcode version minor */
  260 + u8 revision; /* The microcode version revision */
  261 + u8 padding; /* Reserved, for alignment */
  262 + u8 reserved[4]; /* Reserved, for future expansion */
  263 + } __attribute__ ((packed)) microcode[1];
  264 + /* All microcode binaries should be located here */
  265 + /* CRC32 should be located here, after the microcode binaries */
  266 +} __attribute__ ((packed));
  267 +
  268 +struct qe_firmware_info {
  269 + char id[64]; /* Firmware name */
  270 + u32 vtraps[8]; /* Virtual trap addresses */
  271 + u64 extended_modes; /* Extended modes */
  272 +};
  273 +
  274 +void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign);
  275 +void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data);
  276 +uint qe_muram_alloc(uint size, uint align);
  277 +void *qe_muram_addr(uint offset);
  278 +int qe_get_snum(void);
  279 +void qe_put_snum(u8 snum);
  280 +void qe_init(uint qe_base);
  281 +void qe_reset(void);
  282 +void qe_assign_page(uint snum, uint para_ram_base);
  283 +int qe_set_brg(uint brg, uint rate);
  284 +int qe_set_mii_clk_src(int ucc_num);
  285 +int qe_upload_firmware(const struct qe_firmware *firmware);
  286 +struct qe_firmware_info *qe_get_firmware_info(void);
  287 +void ft_qe_setup(void *blob);
  288 +void qe_init(uint qe_base);
  289 +void qe_reset(void);
  290 +
  291 +#ifdef CONFIG_U_QE
  292 +void u_qe_init(void);
  293 +int u_qe_upload_firmware(const struct qe_firmware *firmware);
  294 +void u_qe_resume(void);
  295 +int u_qe_firmware_resume(const struct qe_firmware *firmware,
  296 + qe_map_t *qe_immrr);
  297 +#endif
  298 +
  299 +#endif /* __QE_H__ */