Eric Lee / smarc-uboot

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Commit 248278d7f789c8f885197a22285639c635f5a34b

Authored by Patrice Chotard
1 parent 28c064e66b
Exists in smarc_8mq_lf_v2020.04 and in 9 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

clk: stm32mp1: Add SPI1 clock entry 

Add missing SPI1 clock needed by SPI1 instance.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

Showing 1 changed file with 7 additions and 0 deletions Side-by-side Diff

drivers/clk/clk_stm32mp1.c
Diff comments   View file @ 248278d
... ... @@ -90,6 +90,7 @@
90 90 #define RCC_PLL4CSGR 0x8A4
91 91 #define RCC_I2C12CKSELR 0x8C0
92 92 #define RCC_I2C35CKSELR 0x8C4
  93 +#define RCC_SPI2S1CKSELR 0x8D8
93 94 #define RCC_UART6CKSELR 0x8E4
94 95 #define RCC_UART24CKSELR 0x8E8
95 96 #define RCC_UART35CKSELR 0x8EC
... ... @@ -298,6 +299,7 @@
298 299 _STGEN_SEL,
299 300 _DSI_SEL,
300 301 _ADC12_SEL,
  302 + _SPI1_SEL,
301 303 _PARENT_SEL_NB,
302 304 _UNKNOWN_SEL = 0xff,
303 305 };
... ... @@ -519,6 +521,7 @@
519 521 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
520 522 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
521 523  
  524 + STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 8, SPI1_K, _SPI1_SEL),
522 525 STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
523 526  
524 527 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
... ... @@ -589,6 +592,8 @@
589 592 static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
590 593 static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
591 594 static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
  595 +static const u8 spi_parents[] = {_PLL4_P, _PLL3_Q, _I2S_CKIN, _CK_PER,
  596 + _PLL3_R};
592 597  
593 598 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
594 599 STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
... ... @@ -613,6 +618,7 @@
613 618 STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
614 619 STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
615 620 STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x1, adc_parents),
  621 + STM32MP1_CLK_PARENT(_SPI1_SEL, RCC_SPI2S1CKSELR, 0, 0x7, spi_parents),
616 622 };
617 623  
618 624 #ifdef STM32MP1_CLOCK_TREE_INIT
... ... @@ -727,6 +733,7 @@
727 733 [_STGEN_SEL] = "STGEN",
728 734 [_DSI_SEL] = "DSI",
729 735 [_ADC12_SEL] = "ADC12",
  736 + [_SPI1_SEL] = "SPI1",
730 737 };
731 738  
732 739 static const struct stm32mp1_clk_data stm32mp1_data = {