Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 254887a57e93a818a10d95451a8ec29cb30c21f4

Authored by Shengzhou Liu
Committed by York Sun
1 parent 35c471e509
Exists in master and in 49 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

powerpc/t2081qds: Add T2081 QDS board support 

T2081 QDS is a high-performance computing evaluation, development and
test platform supporting the T2081 QorIQ Power Architecture processor.

T2081QDS board Overview
-----------------------
- T2081 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
- 2MB shared L2 and 512KB L3 CoreNet platform cache (CPC)
- CoreNet fabric supporting coherent and noncoherent transactions with
  prioritization and bandwidth allocation
- 32-/64-bit DDR3/DDR3LP SDRAM memory controller with ECC and interleaving
- Ethernet interfaces:
  - Two on-board 10M/100M/1G bps RGMII ports
  - Two 10Gbps XFI with on-board SFP+ cage
  - 1Gbps/2.5Gbps SGMII Riser card
  - 10Gbps XAUI Riser card
- Accelerator:
  - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
- SerDes:
  - 8 lanes up to 10.3125GHz
  - Supports SGMII, HiGig, XFI, XAUI and Aurora debug,
- IFC:
  - 512MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA
- eSPI:
  - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
- USB:
  - Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB)
- PCIe:
  - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
- eSDHC:
  - Supports various SD/SDHC/SDXC/eMMC devices with adapter cards and
    voltage translators
- I2C:
  - Four I2C controllers.
- UART:
  - Dual 4-pins UART serial ports

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

Showing 28 changed files with 2461 additions and 2219 deletions Side-by-side Diff

board/freescale/t2080qds/Makefile
View file @ 254887a
1   -#
2   -# Copyright 2013 Freescale Semiconductor, Inc.
3   -#
4   -# SPDX-License-Identifier: GPL-2.0+
5   -#
6   -
7   -obj-$(CONFIG_T2080QDS) += t2080qds.o
8   -obj-$(CONFIG_T2080QDS) += eth_t2080qds.o
9   -obj-$(CONFIG_PCI) += pci.o
10   -obj-y += ddr.o
11   -obj-y += law.o
12   -obj-y += tlb.o
board/freescale/t2080qds/ddr.c
View file @ 254887a
1   -/*
2   - * Copyright 2013 Freescale Semiconductor, Inc.
3   - *
4   - * This program is free software; you can redistribute it and/or
5   - * modify it under the terms of the GNU General Public License
6   - * Version 2 or later as published by the Free Software Foundation.
7   - */
8   -
9   -#include <common.h>
10   -#include <i2c.h>
11   -#include <hwconfig.h>
12   -#include <asm/mmu.h>
13   -#include <fsl_ddr_sdram.h>
14   -#include <fsl_ddr_dimm_params.h>
15   -#include <asm/fsl_law.h>
16   -#include "ddr.h"
17   -
18   -DECLARE_GLOBAL_DATA_PTR;
19   -
20   -void fsl_ddr_board_options(memctl_options_t *popts,
21   - dimm_params_t *pdimm,
22   - unsigned int ctrl_num)
23   -{
24   - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
25   - ulong ddr_freq;
26   -
27   - if (ctrl_num > 1) {
28   - printf("Not supported controller number %d\n", ctrl_num);
29   - return;
30   - }
31   - if (!pdimm->n_ranks)
32   - return;
33   -
34   - /*
35   - * we use identical timing for all slots. If needed, change the code
36   - * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
37   - */
38   - if (popts->registered_dimm_en)
39   - pbsp = rdimms[0];
40   - else
41   - pbsp = udimms[0];
42   -
43   - /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
44   - * freqency and n_banks specified in board_specific_parameters table.
45   - */
46   - ddr_freq = get_ddr_freq(0) / 1000000;
47   - while (pbsp->datarate_mhz_high) {
48   - if (pbsp->n_ranks == pdimm->n_ranks &&
49   - (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
50   - if (ddr_freq <= pbsp->datarate_mhz_high) {
51   - popts->clk_adjust = pbsp->clk_adjust;
52   - popts->wrlvl_start = pbsp->wrlvl_start;
53   - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
54   - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
55   - goto found;
56   - }
57   - pbsp_highest = pbsp;
58   - }
59   - pbsp++;
60   - }
61   -
62   - if (pbsp_highest) {
63   - printf("Error: board specific timing not found");
64   - printf("for data rate %lu MT/s\n", ddr_freq);
65   - printf("Trying to use the highest speed (%u) parameters\n",
66   - pbsp_highest->datarate_mhz_high);
67   - popts->clk_adjust = pbsp_highest->clk_adjust;
68   - popts->wrlvl_start = pbsp_highest->wrlvl_start;
69   - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
70   - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
71   - } else {
72   - panic("DIMM is not supported by this board");
73   - }
74   -found:
75   - debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
76   - "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
77   - "wrlvl_ctrl_3 0x%x\n",
78   - pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
79   - pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
80   - pbsp->wrlvl_ctl_3);
81   -
82   - /*
83   - * Factors to consider for half-strength driver enable:
84   - * - number of DIMMs installed
85   - */
86   - popts->half_strength_driver_enable = 0;
87   - /*
88   - * Write leveling override
89   - */
90   - popts->wrlvl_override = 1;
91   - popts->wrlvl_sample = 0xf;
92   -
93   - /*
94   - * Rtt and Rtt_WR override
95   - */
96   - popts->rtt_override = 0;
97   -
98   - /* Enable ZQ calibration */
99   - popts->zq_en = 1;
100   -
101   - /* DHC_EN =1, ODT = 75 Ohm */
102   - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
103   - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
104   -}
105   -
106   -phys_size_t initdram(int board_type)
107   -{
108   - phys_size_t dram_size;
109   -
110   - puts("Initializing....using SPD\n");
111   -
112   - dram_size = fsl_ddr_sdram();
113   -
114   - dram_size = setup_ddr_tlbs(dram_size / 0x100000);
115   - dram_size *= 0x100000;
116   -
117   - puts(" DDR: ");
118   - return dram_size;
119   -}
board/freescale/t2080qds/ddr.h
View file @ 254887a
1   -/*
2   - * Copyright 2013 Freescale Semiconductor, Inc.
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -#ifndef __DDR_H__
8   -#define __DDR_H__
9   -struct board_specific_parameters {
10   - u32 n_ranks;
11   - u32 datarate_mhz_high;
12   - u32 rank_gb;
13   - u32 clk_adjust;
14   - u32 wrlvl_start;
15   - u32 wrlvl_ctl_2;
16   - u32 wrlvl_ctl_3;
17   -};
18   -
19   -/*
20   - * These tables contain all valid speeds we want to override with board
21   - * specific parameters. datarate_mhz_high values need to be in ascending order
22   - * for each n_ranks group.
23   - */
24   -
25   -static const struct board_specific_parameters udimm0[] = {
26   - /*
27   - * memory controller 0
28   - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
29   - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
30   - */
31   - {2, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
32   - {2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
33   - {2, 1600, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b},
34   - {2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
35   - {2, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c},
36   - {2, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b},
37   - {1, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
38   - {1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
39   - {1, 1600, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b},
40   - {1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
41   - {1, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c},
42   - {1, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b},
43   - {}
44   -};
45   -
46   -static const struct board_specific_parameters rdimm0[] = {
47   - /*
48   - * memory controller 0
49   - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
50   - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
51   - */
52   - /* TODO: need tuning these parameters if RDIMM is used */
53   - {4, 1350, 0, 5, 9, 0x08070605, 0x06070806},
54   - {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906},
55   - {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
56   - {2, 1350, 0, 5, 9, 0x08070605, 0x06070806},
57   - {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
58   - {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
59   - {1, 1350, 0, 5, 9, 0x08070605, 0x06070806},
60   - {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
61   - {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07},
62   - {}
63   -};
64   -
65   -static const struct board_specific_parameters *udimms[] = {
66   - udimm0,
67   -};
68   -
69   -static const struct board_specific_parameters *rdimms[] = {
70   - rdimm0,
71   -};
72   -#endif
board/freescale/t2080qds/eth_t2080qds.c
View file @ 254887a
1   -/*
2   - * Copyright 2013 Freescale Semiconductor, Inc.
3   - *
4   - * Shengzhou Liu <Shengzhou.Liu@freescale.com>
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -#include <common.h>
10   -#include <command.h>
11   -#include <netdev.h>
12   -#include <asm/mmu.h>
13   -#include <asm/processor.h>
14   -#include <asm/immap_85xx.h>
15   -#include <asm/fsl_law.h>
16   -#include <asm/fsl_serdes.h>
17   -#include <asm/fsl_portals.h>
18   -#include <asm/fsl_liodn.h>
19   -#include <malloc.h>
20   -#include <fm_eth.h>
21   -#include <fsl_mdio.h>
22   -#include <miiphy.h>
23   -#include <phy.h>
24   -#include <asm/fsl_dtsec.h>
25   -#include <asm/fsl_serdes.h>
26   -#include "../common/qixis.h"
27   -#include "../common/fman.h"
28   -#include "t2080qds_qixis.h"
29   -
30   -#define EMI_NONE 0xFFFFFFFF
31   -#define EMI1_RGMII1 0
32   -#define EMI1_RGMII2 1
33   -#define EMI1_SLOT1 2
34   -#define EMI1_SLOT2 6
35   -#define EMI1_SLOT3 3
36   -#define EMI1_SLOT4 4
37   -#define EMI1_SLOT5 5
38   -#define EMI2 7
39   -
40   -static int mdio_mux[NUM_FM_PORTS];
41   -
42   -static const char * const mdio_names[] = {
43   - "T2080QDS_MDIO_RGMII1",
44   - "T2080QDS_MDIO_RGMII2",
45   - "T2080QDS_MDIO_SLOT1",
46   - "T2080QDS_MDIO_SLOT3",
47   - "T2080QDS_MDIO_SLOT4",
48   - "T2080QDS_MDIO_SLOT5",
49   - "T2080QDS_MDIO_SLOT2",
50   - "T2080QDS_MDIO_10GC",
51   -};
52   -
53   -/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
54   -static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
55   -
56   -static const char *T2080qds_mdio_name_for_muxval(u8 muxval)
57   -{
58   - return mdio_names[muxval];
59   -}
60   -
61   -struct mii_dev *mii_dev_for_muxval(u8 muxval)
62   -{
63   - struct mii_dev *bus;
64   - const char *name = T2080qds_mdio_name_for_muxval(muxval);
65   -
66   - if (!name) {
67   - printf("No bus for muxval %x\n", muxval);
68   - return NULL;
69   - }
70   -
71   - bus = miiphy_get_dev_by_name(name);
72   -
73   - if (!bus) {
74   - printf("No bus by name %s\n", name);
75   - return NULL;
76   - }
77   -
78   - return bus;
79   -}
80   -
81   -struct T2080qds_mdio {
82   - u8 muxval;
83   - struct mii_dev *realbus;
84   -};
85   -
86   -static void T2080qds_mux_mdio(u8 muxval)
87   -{
88   - u8 brdcfg4;
89   - if (muxval < 7) {
90   - brdcfg4 = QIXIS_READ(brdcfg[4]);
91   - brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
92   - brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
93   - QIXIS_WRITE(brdcfg[4], brdcfg4);
94   - }
95   -}
96   -
97   -static int T2080qds_mdio_read(struct mii_dev *bus, int addr, int devad,
98   - int regnum)
99   -{
100   - struct T2080qds_mdio *priv = bus->priv;
101   -
102   - T2080qds_mux_mdio(priv->muxval);
103   -
104   - return priv->realbus->read(priv->realbus, addr, devad, regnum);
105   -}
106   -
107   -static int T2080qds_mdio_write(struct mii_dev *bus, int addr, int devad,
108   - int regnum, u16 value)
109   -{
110   - struct T2080qds_mdio *priv = bus->priv;
111   -
112   - T2080qds_mux_mdio(priv->muxval);
113   -
114   - return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
115   -}
116   -
117   -static int T2080qds_mdio_reset(struct mii_dev *bus)
118   -{
119   - struct T2080qds_mdio *priv = bus->priv;
120   -
121   - return priv->realbus->reset(priv->realbus);
122   -}
123   -
124   -static int T2080qds_mdio_init(char *realbusname, u8 muxval)
125   -{
126   - struct T2080qds_mdio *pmdio;
127   - struct mii_dev *bus = mdio_alloc();
128   -
129   - if (!bus) {
130   - printf("Failed to allocate T2080QDS MDIO bus\n");
131   - return -1;
132   - }
133   -
134   - pmdio = malloc(sizeof(*pmdio));
135   - if (!pmdio) {
136   - printf("Failed to allocate T2080QDS private data\n");
137   - free(bus);
138   - return -1;
139   - }
140   -
141   - bus->read = T2080qds_mdio_read;
142   - bus->write = T2080qds_mdio_write;
143   - bus->reset = T2080qds_mdio_reset;
144   - sprintf(bus->name, T2080qds_mdio_name_for_muxval(muxval));
145   -
146   - pmdio->realbus = miiphy_get_dev_by_name(realbusname);
147   -
148   - if (!pmdio->realbus) {
149   - printf("No bus with name %s\n", realbusname);
150   - free(bus);
151   - free(pmdio);
152   - return -1;
153   - }
154   -
155   - pmdio->muxval = muxval;
156   - bus->priv = pmdio;
157   -
158   - return mdio_register(bus);
159   -}
160   -
161   -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
162   - enum fm_port port, int offset)
163   -{
164   - int phy;
165   - char alias[20];
166   - struct fixed_link f_link;
167   - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
168   - u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
169   - FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
170   -
171   - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
172   -
173   - if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
174   - phy = fm_info_get_phy_address(port);
175   - switch (port) {
176   - case FM1_DTSEC1:
177   - case FM1_DTSEC2:
178   - case FM1_DTSEC9:
179   - case FM1_DTSEC10:
180   - sprintf(alias, "phy_sgmii_s3_%x", phy);
181   - fdt_set_phy_handle(fdt, compat, addr, alias);
182   - fdt_status_okay_by_alias(fdt, "emi1_slot3");
183   - break;
184   - case FM1_DTSEC5:
185   - case FM1_DTSEC6:
186   - if (mdio_mux[port] == EMI1_SLOT1) {
187   - sprintf(alias, "phy_sgmii_s1_%x", phy);
188   - fdt_set_phy_handle(fdt, compat, addr, alias);
189   - fdt_status_okay_by_alias(fdt, "emi1_slot1");
190   - } else if (mdio_mux[port] == EMI1_SLOT2) {
191   - sprintf(alias, "phy_sgmii_s2_%x", phy);
192   - fdt_set_phy_handle(fdt, compat, addr, alias);
193   - fdt_status_okay_by_alias(fdt, "emi1_slot2");
194   - }
195   - break;
196   - default:
197   - break;
198   - }
199   -
200   - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
201   - switch (srds_s1) {
202   - case 0x66: /* XFI interface */
203   - case 0x6b:
204   - case 0x6c:
205   - case 0x6d:
206   - case 0x71:
207   - f_link.phy_id = port;
208   - f_link.duplex = 1;
209   - f_link.link_speed = 10000;
210   - f_link.pause = 0;
211   - f_link.asym_pause = 0;
212   - /* no PHY for XFI */
213   - fdt_delprop(fdt, offset, "phy-handle");
214   - fdt_setprop(fdt, offset, "fixed-link", &f_link,
215   - sizeof(f_link));
216   - break;
217   - default:
218   - break;
219   - }
220   - }
221   -}
222   -
223   -void fdt_fixup_board_enet(void *fdt)
224   -{
225   - return;
226   -}
227   -
228   -/*
229   - * This function reads RCW to check if Serdes1{E,F,G,H} is configured
230   - * as slot 1/2/3 and update the lane_to_slot[] array accordingly
231   - */
232   -static void initialize_lane_to_slot(void)
233   -{
234   - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
235   - u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
236   - FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
237   -
238   - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
239   -
240   - switch (srds_s1) {
241   - case 0x51:
242   - case 0x5f:
243   - case 0x65:
244   - case 0x6b:
245   - case 0x71:
246   - lane_to_slot[5] = 2;
247   - lane_to_slot[6] = 2;
248   - lane_to_slot[7] = 2;
249   - break;
250   - case 0xa6:
251   - case 0x8e:
252   - case 0x8f:
253   - case 0x82:
254   - case 0x83:
255   - case 0xd3:
256   - case 0xd9:
257   - case 0xcb:
258   - lane_to_slot[6] = 2;
259   - lane_to_slot[7] = 2;
260   - break;
261   - case 0xda:
262   - lane_to_slot[4] = 3;
263   - lane_to_slot[5] = 3;
264   - lane_to_slot[6] = 3;
265   - lane_to_slot[7] = 3;
266   - break;
267   - default:
268   - break;
269   - }
270   -}
271   -
272   -int board_eth_init(bd_t *bis)
273   -{
274   -#if defined(CONFIG_FMAN_ENET)
275   - int i, idx, lane, slot, interface;
276   - struct memac_mdio_info dtsec_mdio_info;
277   - struct memac_mdio_info tgec_mdio_info;
278   - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
279   - u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
280   - u32 srds_s1;
281   -
282   - srds_s1 = in_be32(&gur->rcwsr[4]) &
283   - FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
284   - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
285   -
286   - initialize_lane_to_slot();
287   -
288   - /* Initialize the mdio_mux array so we can recognize empty elements */
289   - for (i = 0; i < NUM_FM_PORTS; i++)
290   - mdio_mux[i] = EMI_NONE;
291   -
292   - dtsec_mdio_info.regs =
293   - (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
294   -
295   - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
296   -
297   - /* Register the 1G MDIO bus */
298   - fm_memac_mdio_init(bis, &dtsec_mdio_info);
299   -
300   - tgec_mdio_info.regs =
301   - (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
302   - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
303   -
304   - /* Register the 10G MDIO bus */
305   - fm_memac_mdio_init(bis, &tgec_mdio_info);
306   -
307   - /* Register the muxing front-ends to the MDIO buses */
308   - T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
309   - T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
310   - T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
311   - T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
312   - T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
313   - T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
314   - T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
315   - T2080qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
316   -
317   - /* Set the two on-board RGMII PHY address */
318   - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
319   - if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
320   - FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII)
321   - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
322   - else
323   - fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
324   -
325   - switch (srds_s1) {
326   - case 0x1c:
327   - case 0x95:
328   - case 0xa2:
329   - case 0x94:
330   - /* SGMII in Slot3 */
331   - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
332   - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
333   - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
334   - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
335   - /* SGMII in Slot2 */
336   - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
337   - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
338   - break;
339   - case 0x51:
340   - case 0x5f:
341   - case 0x65:
342   - /* XAUI/HiGig in Slot3 */
343   - fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
344   - /* SGMII in Slot2 */
345   - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
346   - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
347   - break;
348   - case 0x66:
349   - /*
350   - * XFI does not need a PHY to work, but to avoid U-boot use
351   - * default PHY address which is zero to a MAC when it found
352   - * a MAC has no PHY address, we give a PHY address to XFI
353   - * MAC, and should not use a real XAUI PHY address, since
354   - * MDIO can access it successfully, and then MDIO thinks
355   - * the XAUI card is used for the XFI MAC, which will cause
356   - * error.
357   - */
358   - fm_info_set_phy_address(FM1_10GEC1, 4);
359   - fm_info_set_phy_address(FM1_10GEC2, 5);
360   - fm_info_set_phy_address(FM1_10GEC3, 6);
361   - fm_info_set_phy_address(FM1_10GEC4, 7);
362   - break;
363   - case 0x6b:
364   - fm_info_set_phy_address(FM1_10GEC1, 4);
365   - fm_info_set_phy_address(FM1_10GEC2, 5);
366   - fm_info_set_phy_address(FM1_10GEC3, 6);
367   - fm_info_set_phy_address(FM1_10GEC4, 7);
368   - /* SGMII in Slot2 */
369   - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
370   - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
371   - break;
372   - case 0x6c:
373   - case 0x6d:
374   - fm_info_set_phy_address(FM1_10GEC1, 4);
375   - fm_info_set_phy_address(FM1_10GEC2, 5);
376   - /* SGMII in Slot3 */
377   - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
378   - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
379   - break;
380   - case 0x71:
381   - /* SGMII in Slot3 */
382   - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
383   - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
384   - /* SGMII in Slot2 */
385   - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
386   - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
387   - break;
388   - case 0xa6:
389   - case 0x8e:
390   - case 0x8f:
391   - case 0x82:
392   - case 0x83:
393   - /* SGMII in Slot3 */
394   - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
395   - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
396   - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
397   - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
398   - /* SGMII in Slot2 */
399   - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
400   - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
401   - break;
402   - case 0xa4:
403   - case 0x96:
404   - case 0x8a:
405   - /* SGMII in Slot3 */
406   - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
407   - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
408   - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
409   - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
410   - break;
411   - case 0xd9:
412   - case 0xd3:
413   - case 0xcb:
414   - /* SGMII in Slot3 */
415   - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
416   - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
417   - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
418   - /* SGMII in Slot2 */
419   - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
420   - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
421   - break;
422   - default:
423   - break;
424   - }
425   -
426   - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
427   - idx = i - FM1_DTSEC1;
428   - interface = fm_info_get_enet_if(i);
429   - switch (interface) {
430   - case PHY_INTERFACE_MODE_SGMII:
431   - lane = serdes_get_first_lane(FSL_SRDS_1,
432   - SGMII_FM1_DTSEC1 + idx);
433   - if (lane < 0)
434   - break;
435   - slot = lane_to_slot[lane];
436   - debug("FM1@DTSEC%u expects SGMII in slot %u\n",
437   - idx + 1, slot);
438   - if (QIXIS_READ(present2) & (1 << (slot - 1)))
439   - fm_disable_port(i);
440   -
441   - switch (slot) {
442   - case 1:
443   - mdio_mux[i] = EMI1_SLOT1;
444   - fm_info_set_mdio(i, mii_dev_for_muxval(
445   - mdio_mux[i]));
446   - break;
447   - case 2:
448   - mdio_mux[i] = EMI1_SLOT2;
449   - fm_info_set_mdio(i, mii_dev_for_muxval(
450   - mdio_mux[i]));
451   - break;
452   - case 3:
453   - mdio_mux[i] = EMI1_SLOT3;
454   - fm_info_set_mdio(i, mii_dev_for_muxval(
455   - mdio_mux[i]));
456   - break;
457   - }
458   - break;
459   - case PHY_INTERFACE_MODE_RGMII:
460   - if (i == FM1_DTSEC3)
461   - mdio_mux[i] = EMI1_RGMII1;
462   - else if (i == FM1_DTSEC4 || FM1_DTSEC10)
463   - mdio_mux[i] = EMI1_RGMII2;
464   - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
465   - break;
466   - default:
467   - break;
468   - }
469   - }
470   -
471   - for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
472   - idx = i - FM1_10GEC1;
473   - switch (fm_info_get_enet_if(i)) {
474   - case PHY_INTERFACE_MODE_XGMII:
475   - if (srds_s1 == 0x51) {
476   - lane = serdes_get_first_lane(FSL_SRDS_1,
477   - XAUI_FM1_MAC9 + idx);
478   - } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) {
479   - lane = serdes_get_first_lane(FSL_SRDS_1,
480   - HIGIG_FM1_MAC9 + idx);
481   - } else {
482   - if (i == FM1_10GEC1 || i == FM1_10GEC2)
483   - lane = serdes_get_first_lane(FSL_SRDS_1,
484   - XFI_FM1_MAC9 + idx);
485   - else
486   - lane = serdes_get_first_lane(FSL_SRDS_1,
487   - XFI_FM1_MAC1 + idx);
488   - }
489   -
490   - if (lane < 0)
491   - break;
492   - mdio_mux[i] = EMI2;
493   - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
494   -
495   - if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||
496   - (srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
497   - (srds_s1 == 0x71)) {
498   - /* As XFI is in cage intead of a slot, so
499   - * ensure doesn't disable the corresponding port
500   - */
501   - break;
502   - }
503   -
504   - slot = lane_to_slot[lane];
505   - if (QIXIS_READ(present2) & (1 << (slot - 1)))
506   - fm_disable_port(i);
507   - break;
508   - default:
509   - break;
510   - }
511   - }
512   -
513   - cpu_eth_init(bis);
514   -#endif /* CONFIG_FMAN_ENET */
515   -
516   - return pci_eth_init(bis);
517   -}
board/freescale/t2080qds/law.c
View file @ 254887a
1   -/*
2   - * Copyright 2008-2012 Freescale Semiconductor, Inc.
3   - *
4   - * (C) Copyright 2000
5   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6   - *
7   - * SPDX-License-Identifier: GPL-2.0+
8   - */
9   -
10   -#include <common.h>
11   -#include <asm/fsl_law.h>
12   -#include <asm/mmu.h>
13   -
14   -struct law_entry law_table[] = {
15   - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
16   -#ifdef CONFIG_SYS_BMAN_MEM_PHYS
17   - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
18   -#endif
19   -#ifdef CONFIG_SYS_QMAN_MEM_PHYS
20   - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
21   -#endif
22   -#ifdef QIXIS_BASE_PHYS
23   - SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
24   -#endif
25   -#ifdef CONFIG_SYS_DCSRBAR_PHYS
26   - /* Limit DCSR to 32M to access NPC Trace Buffer */
27   - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
28   -#endif
29   -#ifdef CONFIG_SYS_NAND_BASE_PHYS
30   - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
31   -#endif
32   -};
33   -
34   -int num_law_entries = ARRAY_SIZE(law_table);
board/freescale/t2080qds/pci.c
View file @ 254887a
1   -/*
2   - * Copyright 2007-2013 Freescale Semiconductor, Inc.
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -#include <common.h>
8   -#include <command.h>
9   -#include <pci.h>
10   -#include <asm/fsl_pci.h>
11   -#include <libfdt.h>
12   -#include <fdt_support.h>
13   -#include <asm/fsl_serdes.h>
14   -
15   -void pci_init_board(void)
16   -{
17   - fsl_pcie_init_board(0);
18   -}
19   -
20   -void pci_of_setup(void *blob, bd_t *bd)
21   -{
22   - FT_FSL_PCI_SETUP;
23   -}
board/freescale/t2080qds/t2080_pbi.cfg
View file @ 254887a
1   -#
2   -# Copyright 2013 Freescale Semiconductor, Inc.
3   -#
4   -# SPDX-License-Identifier: GPL-2.0+
5   -#
6   -# Refer doc/README.pblimage for more details about how-to configure
7   -# and create PBL boot image
8   -#
9   -
10   -#PBI commands
11   -#Initialize CPC1
12   -09010000 00200400
13   -09138000 00000000
14   -091380c0 00000100
15   -#512KB SRAM
16   -09010100 00000000
17   -09010104 fff80009
18   -09010f00 08000000
19   -#enable CPC1
20   -09010000 80000000
21   -#Configure LAW for CPC1
22   -09000d00 00000000
23   -09000d04 fff80000
24   -09000d08 81000012
25   -#Initialize eSPI controller, default configuration is slow for eSPI to
26   -#load data, this configuration comes from u-boot eSPI driver.
27   -09110000 80000403
28   -09110020 2d170008
29   -09110024 00100008
30   -09110028 00100008
31   -0911002c 00100008
32   -#Errata for slowing down the MDC clock to make it <= 2.5 MHZ
33   -094fc030 00008148
34   -094fd030 00008148
35   -#Configure alternate space
36   -09000010 00000000
37   -09000014 ff000000
38   -09000018 81000000
39   -#Flush PBL data
40   -09138000 00000000
41   -091380c0 00000000
board/freescale/t2080qds/t2080_rcw.cfg
View file @ 254887a
1   -#PBL preamble and RCW header
2   -aa55aa55 010e0100
3   -#SerDes Protocol: 0x66_0x16
4   -#Core/DDR: 1533Mhz/2133MT/s
5   -12100017 15000000 00000000 00000000
6   -66160002 00008400 e8104000 c1000000
7   -00000000 00000000 00000000 000307fc
8   -00000000 00000000 00000000 00000004
board/freescale/t2080qds/t2080qds.c
View file @ 254887a
1   -/*
2   - * Copyright 2009-2013 Freescale Semiconductor, Inc.
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -#include <common.h>
8   -#include <command.h>
9   -#include <i2c.h>
10   -#include <netdev.h>
11   -#include <linux/compiler.h>
12   -#include <asm/mmu.h>
13   -#include <asm/processor.h>
14   -#include <asm/immap_85xx.h>
15   -#include <asm/fsl_law.h>
16   -#include <asm/fsl_serdes.h>
17   -#include <asm/fsl_portals.h>
18   -#include <asm/fsl_liodn.h>
19   -#include <fm_eth.h>
20   -
21   -#include "../common/qixis.h"
22   -#include "../common/vsc3316_3308.h"
23   -#include "t2080qds.h"
24   -#include "t2080qds_qixis.h"
25   -
26   -DECLARE_GLOBAL_DATA_PTR;
27   -
28   -int checkboard(void)
29   -{
30   - char buf[64];
31   - u8 sw;
32   - struct cpu_type *cpu = gd->arch.cpu;
33   - static const char *freq[4] = {
34   - "100.00MHZ(from 8T49N222A)", "125.00MHz",
35   - "156.25MHZ", "100.00MHz"
36   - };
37   -
38   - printf("Board: %sQDS, ", cpu->name);
39   - sw = QIXIS_READ(arch);
40   - printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
41   - printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
42   -
43   -#ifdef CONFIG_SDCARD
44   - puts("SD/MMC\n");
45   -#elif CONFIG_SPIFLASH
46   - puts("SPI\n");
47   -#else
48   - sw = QIXIS_READ(brdcfg[0]);
49   - sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
50   -
51   - if (sw < 0x8)
52   - printf("vBank%d\n", sw);
53   - else if (sw == 0x8)
54   - puts("Promjet\n");
55   - else if (sw == 0x9)
56   - puts("NAND\n");
57   - else
58   - printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
59   -#endif
60   -
61   - printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
62   - qixis_read_tag(buf), (int)qixis_read_minor());
63   - /* the timestamp string contains "\n" at the end */
64   - printf(" on %s", qixis_read_time(buf));
65   -
66   - puts("SERDES Reference Clocks:\n");
67   - sw = QIXIS_READ(brdcfg[2]);
68   - printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
69   - freq[(sw >> 4) & 0x3]);
70   - printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
71   - freq[sw & 0x3]);
72   -
73   - return 0;
74   -}
75   -
76   -int select_i2c_ch_pca9547(u8 ch)
77   -{
78   - int ret;
79   -
80   - ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
81   - if (ret) {
82   - puts("PCA: failed to select proper channel\n");
83   - return ret;
84   - }
85   -
86   - return 0;
87   -}
88   -
89   -int brd_mux_lane_to_slot(void)
90   -{
91   - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
92   - u32 srds_prtcl_s1, srds_prtcl_s2;
93   -
94   - srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
95   - FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
96   - srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
97   - srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
98   - FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
99   - srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
100   -
101   - switch (srds_prtcl_s1) {
102   - case 0:
103   - /* SerDes1 is not enabled */
104   - break;
105   - case 0x1c:
106   - case 0xa2:
107   - /* SD1(A:D) => SLOT3 SGMII
108   - * SD1(G:H) => SLOT1 SGMII
109   - */
110   - QIXIS_WRITE(brdcfg[12], 0x1a);
111   - break;
112   - case 0x94:
113   - case 0x95:
114   - /* SD1(A:B) => SLOT3 SGMII@1.25bps
115   - * SD1(C:D) => SFP Module, SGMII@3.125bps
116   - * SD1(E:H) => SLOT1 SGMII@1.25bps
117   - */
118   - case 0x96:
119   - /* SD1(A:B) => SLOT3 SGMII@1.25bps
120   - * SD1(C) => SFP Module, SGMII@3.125bps
121   - * SD1(D) => SFP Module, SGMII@1.25bps
122   - * SD1(E:H) => SLOT1 PCIe4 x4
123   - */
124   - QIXIS_WRITE(brdcfg[12], 0x3a);
125   - break;
126   - case 0x51:
127   - /* SD1(A:D) => SLOT3 XAUI
128   - * SD1(E) => SLOT1 PCIe4
129   - * SD1(F:H) => SLOT2 SGMII
130   - */
131   - QIXIS_WRITE(brdcfg[12], 0x15);
132   - break;
133   - case 0x66:
134   - case 0x67:
135   - /* SD1(A:D) => XFI cage
136   - * SD1(E:H) => SLOT1 PCIe4
137   - */
138   - QIXIS_WRITE(brdcfg[12], 0xfe);
139   - break;
140   - case 0x6b:
141   - /* SD1(A:D) => XFI cage
142   - * SD1(E) => SLOT1 PCIe4
143   - * SD1(F:H) => SLOT2 SGMII
144   - */
145   - QIXIS_WRITE(brdcfg[12], 0xf1);
146   - break;
147   - case 0x6c:
148   - case 0x6d:
149   - /* SD1(A:B) => XFI cage
150   - * SD1(C:D) => SLOT3 SGMII
151   - * SD1(E:H) => SLOT1 PCIe4
152   - */
153   - QIXIS_WRITE(brdcfg[12], 0xda);
154   - break;
155   - case 0x6e:
156   - /* SD1(A:B) => SFP Module, XFI
157   - * SD1(C:D) => SLOT3 SGMII
158   - * SD1(E:F) => SLOT1 PCIe4 x2
159   - * SD1(G:H) => SLOT2 SGMII
160   - */
161   - QIXIS_WRITE(brdcfg[12], 0xd9);
162   - break;
163   - case 0xda:
164   - /* SD1(A:H) => SLOT3 PCIe3 x8
165   - */
166   - QIXIS_WRITE(brdcfg[12], 0x0);
167   - break;
168   - case 0xc8:
169   - /* SD1(A) => SLOT3 PCIe3 x1
170   - * SD1(B) => SFP Module, SGMII@1.25bps
171   - * SD1(C:D) => SFP Module, SGMII@3.125bps
172   - * SD1(E:F) => SLOT1 PCIe4 x2
173   - * SD1(G:H) => SLOT2 SGMII
174   - */
175   - QIXIS_WRITE(brdcfg[12], 0x79);
176   - break;
177   - case 0xab:
178   - /* SD1(A:D) => SLOT3 PCIe3 x4
179   - * SD1(E:H) => SLOT1 PCIe4 x4
180   - */
181   - QIXIS_WRITE(brdcfg[12], 0x1a);
182   - break;
183   - default:
184   - printf("WARNING: unsupported for SerDes1 Protocol %d\n",
185   - srds_prtcl_s1);
186   - return -1;
187   - }
188   -
189   - switch (srds_prtcl_s2) {
190   - case 0:
191   - /* SerDes2 is not enabled */
192   - break;
193   - case 0x01:
194   - case 0x02:
195   - /* SD2(A:H) => SLOT4 PCIe1 */
196   - QIXIS_WRITE(brdcfg[13], 0x10);
197   - break;
198   - case 0x15:
199   - case 0x16:
200   - /*
201   - * SD2(A:D) => SLOT4 PCIe1
202   - * SD2(E:F) => SLOT5 PCIe2
203   - * SD2(G:H) => SATA1,SATA2
204   - */
205   - QIXIS_WRITE(brdcfg[13], 0xb0);
206   - break;
207   - case 0x18:
208   - /*
209   - * SD2(A:D) => SLOT4 PCIe1
210   - * SD2(E:F) => SLOT5 Aurora
211   - * SD2(G:H) => SATA1,SATA2
212   - */
213   - QIXIS_WRITE(brdcfg[13], 0x78);
214   - break;
215   - case 0x1f:
216   - /*
217   - * SD2(A:D) => SLOT4 PCIe1
218   - * SD2(E:H) => SLOT5 PCIe2
219   - */
220   - QIXIS_WRITE(brdcfg[13], 0xa0);
221   - break;
222   - case 0x29:
223   - case 0x2d:
224   - case 0x2e:
225   - /*
226   - * SD2(A:D) => SLOT4 SRIO2
227   - * SD2(E:H) => SLOT5 SRIO1
228   - */
229   - QIXIS_WRITE(brdcfg[13], 0xa0);
230   - break;
231   - case 0x36:
232   - /*
233   - * SD2(A:D) => SLOT4 SRIO2
234   - * SD2(E:F) => Aurora
235   - * SD2(G:H) => SATA1,SATA2
236   - */
237   - QIXIS_WRITE(brdcfg[13], 0x78);
238   - break;
239   - default:
240   - printf("WARNING: unsupported for SerDes2 Protocol %d\n",
241   - srds_prtcl_s2);
242   - return -1;
243   - }
244   - return 0;
245   -}
246   -
247   -int board_early_init_r(void)
248   -{
249   - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
250   - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
251   -
252   - /*
253   - * Remap Boot flash + PROMJET region to caching-inhibited
254   - * so that flash can be erased properly.
255   - */
256   -
257   - /* Flush d-cache and invalidate i-cache of any FLASH data */
258   - flush_dcache();
259   - invalidate_icache();
260   -
261   - /* invalidate existing TLB entry for flash + promjet */
262   - disable_tlb(flash_esel);
263   -
264   - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
265   - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
266   - 0, flash_esel, BOOKE_PAGESZ_256M, 1);
267   -
268   - set_liodns();
269   -#ifdef CONFIG_SYS_DPAA_QBMAN
270   - setup_portals();
271   -#endif
272   -
273   - /* Disable remote I2C connection to qixis fpga */
274   - QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
275   -
276   - brd_mux_lane_to_slot();
277   - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
278   -
279   - return 0;
280   -}
281   -
282   -unsigned long get_board_sys_clk(void)
283   -{
284   - u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
285   -#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
286   - /* use accurate clock measurement */
287   - int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
288   - int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
289   - u32 val;
290   -
291   - val = freq * base;
292   - if (val) {
293   - debug("SYS Clock measurement is: %d\n", val);
294   - return val;
295   - } else {
296   - printf("Warning: SYS clock measurement is invalid, ");
297   - printf("using value from brdcfg1.\n");
298   - }
299   -#endif
300   -
301   - switch (sysclk_conf & 0x0F) {
302   - case QIXIS_SYSCLK_83:
303   - return 83333333;
304   - case QIXIS_SYSCLK_100:
305   - return 100000000;
306   - case QIXIS_SYSCLK_125:
307   - return 125000000;
308   - case QIXIS_SYSCLK_133:
309   - return 133333333;
310   - case QIXIS_SYSCLK_150:
311   - return 150000000;
312   - case QIXIS_SYSCLK_160:
313   - return 160000000;
314   - case QIXIS_SYSCLK_166:
315   - return 166666666;
316   - }
317   - return 66666666;
318   -}
319   -
320   -unsigned long get_board_ddr_clk(void)
321   -{
322   - u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
323   -#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
324   - /* use accurate clock measurement */
325   - int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
326   - int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
327   - u32 val;
328   -
329   - val = freq * base;
330   - if (val) {
331   - debug("DDR Clock measurement is: %d\n", val);
332   - return val;
333   - } else {
334   - printf("Warning: DDR clock measurement is invalid, ");
335   - printf("using value from brdcfg1.\n");
336   - }
337   -#endif
338   -
339   - switch ((ddrclk_conf & 0x30) >> 4) {
340   - case QIXIS_DDRCLK_100:
341   - return 100000000;
342   - case QIXIS_DDRCLK_125:
343   - return 125000000;
344   - case QIXIS_DDRCLK_133:
345   - return 133333333;
346   - }
347   - return 66666666;
348   -}
349   -
350   -int misc_init_r(void)
351   -{
352   - return 0;
353   -}
354   -
355   -void ft_board_setup(void *blob, bd_t *bd)
356   -{
357   - phys_addr_t base;
358   - phys_size_t size;
359   -
360   - ft_cpu_setup(blob, bd);
361   -
362   - base = getenv_bootm_low();
363   - size = getenv_bootm_size();
364   -
365   - fdt_fixup_memory(blob, (u64)base, (u64)size);
366   -
367   -#ifdef CONFIG_PCI
368   - pci_of_setup(blob, bd);
369   -#endif
370   -
371   - fdt_fixup_liodn(blob);
372   - fdt_fixup_dr_usb(blob, bd);
373   -
374   -#ifdef CONFIG_SYS_DPAA_FMAN
375   - fdt_fixup_fman_ethernet(blob);
376   - fdt_fixup_board_enet(blob);
377   -#endif
378   -}
board/freescale/t2080qds/t2080qds.h
View file @ 254887a
1   -/*
2   - * Copyright 2011-2013 Freescale Semiconductor, Inc.
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -#ifndef __CORENET_DS_H__
8   -#define __CORENET_DS_H__
9   -
10   -void fdt_fixup_board_enet(void *blob);
11   -void pci_of_setup(void *blob, bd_t *bd);
12   -
13   -#endif
board/freescale/t2080qds/t2080qds_qixis.h
View file @ 254887a
1   -/*
2   - * Copyright 2013 Freescale Semiconductor, Inc.
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -#ifndef __T2080QDS_QIXIS_H__
8   -#define __T2080QDS_QIXIS_H__
9   -
10   -/* Definitions of QIXIS Registers for T2080QDS */
11   -
12   -#define QIXIS_SRDS1CLK_122 0x5a
13   -#define QIXIS_SRDS1CLK_125 0x5e
14   -
15   -
16   -/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
17   -#define BRDCFG4_EMISEL_MASK 0xE0
18   -#define BRDCFG4_EMISEL_SHIFT 5
19   -
20   -/* SYSCLK */
21   -#define QIXIS_SYSCLK_66 0x0
22   -#define QIXIS_SYSCLK_83 0x1
23   -#define QIXIS_SYSCLK_100 0x2
24   -#define QIXIS_SYSCLK_125 0x3
25   -#define QIXIS_SYSCLK_133 0x4
26   -#define QIXIS_SYSCLK_150 0x5
27   -#define QIXIS_SYSCLK_160 0x6
28   -#define QIXIS_SYSCLK_166 0x7
29   -
30   -/* DDRCLK */
31   -#define QIXIS_DDRCLK_66 0x0
32   -#define QIXIS_DDRCLK_100 0x1
33   -#define QIXIS_DDRCLK_125 0x2
34   -#define QIXIS_DDRCLK_133 0x3
35   -
36   -#define BRDCFG5_IRE 0x20 /* i2c Remote i2c1 enable */
37   -
38   -#define BRDCFG12_SD3EN_MASK 0x20
39   -#define BRDCFG12_SD3MX_MASK 0x08
40   -#define BRDCFG12_SD3MX_SLOT5 0x08
41   -#define BRDCFG12_SD3MX_SLOT6 0x00
42   -#define BRDCFG12_SD4EN_MASK 0x04
43   -#define BRDCFG12_SD4MX_MASK 0x03
44   -#define BRDCFG12_SD4MX_SLOT7 0x02
45   -#define BRDCFG12_SD4MX_SLOT8 0x01
46   -#define BRDCFG12_SD4MX_AURO_SATA 0x00
47   -#endif
board/freescale/t2080qds/tlb.c
View file @ 254887a
1   -/*
2   - * Copyright 2008-2013 Freescale Semiconductor, Inc.
3   - *
4   - * (C) Copyright 2000
5   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6   - *
7   - * SPDX-License-Identifier: GPL-2.0+
8   - */
9   -
10   -#include <common.h>
11   -#include <asm/mmu.h>
12   -
13   -struct fsl_e_tlb_entry tlb_table[] = {
14   - /* TLB 0 - for temp stack in cache */
15   - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
16   - CONFIG_SYS_INIT_RAM_ADDR_PHYS,
17   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
18   - 0, 0, BOOKE_PAGESZ_4K, 0),
19   - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
20   - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
21   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
22   - 0, 0, BOOKE_PAGESZ_4K, 0),
23   - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
24   - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
25   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
26   - 0, 0, BOOKE_PAGESZ_4K, 0),
27   - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
28   - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
29   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
30   - 0, 0, BOOKE_PAGESZ_4K, 0),
31   -
32   - /* TLB 1 */
33   - /* *I*** - Covers boot page */
34   -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
35   - /*
36   - * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
37   - * SRAM is at 0xfff00000, it covered the 0xfffff000.
38   - */
39   - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
40   - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
41   - 0, 0, BOOKE_PAGESZ_1M, 1),
42   -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
43   - /*
44   - * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
45   - * space is at 0xfff00000, it covered the 0xfffff000.
46   - */
47   - SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
48   - CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
49   - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
50   - 0, 0, BOOKE_PAGESZ_1M, 1),
51   -#else
52   - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
53   - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
54   - 0, 0, BOOKE_PAGESZ_4K, 1),
55   -#endif
56   -
57   - /* *I*G* - CCSRBAR */
58   - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
59   - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
60   - 0, 1, BOOKE_PAGESZ_16M, 1),
61   -
62   - /* *I*G* - Flash, localbus */
63   - /* This will be changed to *I*G* after relocation to RAM. */
64   - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
65   - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
66   - 0, 2, BOOKE_PAGESZ_256M, 1),
67   -
68   - /* *I*G* - PCIe 1, 0x80000000 */
69   - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
70   - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
71   - 0, 3, BOOKE_PAGESZ_512M, 1),
72   -
73   - /* *I*G* - PCIe 2, 0xa0000000 */
74   - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
75   - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
76   - 0, 4, BOOKE_PAGESZ_256M, 1),
77   -
78   - /* *I*G* - PCIe 3, 0xb0000000 */
79   - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
80   - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
81   - 0, 5, BOOKE_PAGESZ_256M, 1),
82   -
83   -
84   - /* *I*G* - PCIe 4, 0xc0000000 */
85   - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS,
86   - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
87   - 0, 6, BOOKE_PAGESZ_256M, 1),
88   -
89   - /* *I*G* - PCI I/O */
90   - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
91   - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
92   - 0, 7, BOOKE_PAGESZ_256K, 1),
93   -
94   - /* Bman/Qman */
95   -#ifdef CONFIG_SYS_BMAN_MEM_PHYS
96   - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
97   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
98   - 0, 9, BOOKE_PAGESZ_16M, 1),
99   - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
100   - CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
101   - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
102   - 0, 10, BOOKE_PAGESZ_16M, 1),
103   -#endif
104   -#ifdef CONFIG_SYS_QMAN_MEM_PHYS
105   - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
106   - MAS3_SX|MAS3_SW|MAS3_SR, 0,
107   - 0, 11, BOOKE_PAGESZ_16M, 1),
108   - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
109   - CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
110   - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
111   - 0, 12, BOOKE_PAGESZ_16M, 1),
112   -#endif
113   -#ifdef CONFIG_SYS_DCSRBAR_PHYS
114   - SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
115   - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
116   - 0, 13, BOOKE_PAGESZ_32M, 1),
117   -#endif
118   -#ifdef CONFIG_SYS_NAND_BASE
119   - /*
120   - * *I*G - NAND
121   - * entry 14 and 15 has been used hard coded, they will be disabled
122   - * in cpu_init_f, so we use entry 16 for nand.
123   - */
124   - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
125   - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
126   - 0, 16, BOOKE_PAGESZ_64K, 1),
127   -#endif
128   -#ifdef QIXIS_BASE_PHYS
129   - SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
130   - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
131   - 0, 17, BOOKE_PAGESZ_4K, 1),
132   -#endif
133   -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
134   - /*
135   - * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
136   - * fetching ucode and ENV from master
137   - */
138   - SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
139   - CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
140   - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
141   - 0, 18, BOOKE_PAGESZ_1M, 1),
142   -#endif
143   -
144   -};
145   -
146   -int num_tlb_entries = ARRAY_SIZE(tlb_table);
board/freescale/t208xqds/Makefile
Diff comments   View file @ 254887a
  1 +#
  2 +# Copyright 2013 Freescale Semiconductor, Inc.
  3 +#
  4 +# SPDX-License-Identifier: GPL-2.0+
  5 +#
  6 +
  7 +obj-$(CONFIG_T2080QDS) += t208xqds.o
  8 +obj-$(CONFIG_T2080QDS) += eth_t208xqds.o
  9 +obj-$(CONFIG_T2081QDS) += t208xqds.o
  10 +obj-$(CONFIG_T2081QDS) += eth_t208xqds.o
  11 +obj-$(CONFIG_PCI) += pci.o
  12 +obj-y += ddr.o
  13 +obj-y += law.o
  14 +obj-y += tlb.o
board/freescale/t208xqds/ddr.c
Diff comments   View file @ 254887a
  1 +/*
  2 + * Copyright 2013 Freescale Semiconductor, Inc.
  3 + *
  4 + * This program is free software; you can redistribute it and/or
  5 + * modify it under the terms of the GNU General Public License
  6 + * Version 2 or later as published by the Free Software Foundation.
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <i2c.h>
  11 +#include <hwconfig.h>
  12 +#include <asm/mmu.h>
  13 +#include <fsl_ddr_sdram.h>
  14 +#include <fsl_ddr_dimm_params.h>
  15 +#include <asm/fsl_law.h>
  16 +#include "ddr.h"
  17 +
  18 +DECLARE_GLOBAL_DATA_PTR;
  19 +
  20 +void fsl_ddr_board_options(memctl_options_t *popts,
  21 + dimm_params_t *pdimm,
  22 + unsigned int ctrl_num)
  23 +{
  24 + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  25 + ulong ddr_freq;
  26 +
  27 + if (ctrl_num > 1) {
  28 + printf("Not supported controller number %d\n", ctrl_num);
  29 + return;
  30 + }
  31 + if (!pdimm->n_ranks)
  32 + return;
  33 +
  34 + /*
  35 + * we use identical timing for all slots. If needed, change the code
  36 + * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
  37 + */
  38 + if (popts->registered_dimm_en)
  39 + pbsp = rdimms[0];
  40 + else
  41 + pbsp = udimms[0];
  42 +
  43 + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
  44 + * freqency and n_banks specified in board_specific_parameters table.
  45 + */
  46 + ddr_freq = get_ddr_freq(0) / 1000000;
  47 + while (pbsp->datarate_mhz_high) {
  48 + if (pbsp->n_ranks == pdimm->n_ranks &&
  49 + (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
  50 + if (ddr_freq <= pbsp->datarate_mhz_high) {
  51 + popts->clk_adjust = pbsp->clk_adjust;
  52 + popts->wrlvl_start = pbsp->wrlvl_start;
  53 + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  54 + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  55 + goto found;
  56 + }
  57 + pbsp_highest = pbsp;
  58 + }
  59 + pbsp++;
  60 + }
  61 +
  62 + if (pbsp_highest) {
  63 + printf("Error: board specific timing not found");
  64 + printf("for data rate %lu MT/s\n", ddr_freq);
  65 + printf("Trying to use the highest speed (%u) parameters\n",
  66 + pbsp_highest->datarate_mhz_high);
  67 + popts->clk_adjust = pbsp_highest->clk_adjust;
  68 + popts->wrlvl_start = pbsp_highest->wrlvl_start;
  69 + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  70 + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  71 + } else {
  72 + panic("DIMM is not supported by this board");
  73 + }
  74 +found:
  75 + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
  76 + "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
  77 + "wrlvl_ctrl_3 0x%x\n",
  78 + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
  79 + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
  80 + pbsp->wrlvl_ctl_3);
  81 +
  82 + /*
  83 + * Factors to consider for half-strength driver enable:
  84 + * - number of DIMMs installed
  85 + */
  86 + popts->half_strength_driver_enable = 0;
  87 + /*
  88 + * Write leveling override
  89 + */
  90 + popts->wrlvl_override = 1;
  91 + popts->wrlvl_sample = 0xf;
  92 +
  93 + /*
  94 + * Rtt and Rtt_WR override
  95 + */
  96 + popts->rtt_override = 0;
  97 +
  98 + /* Enable ZQ calibration */
  99 + popts->zq_en = 1;
  100 +
  101 + /* DHC_EN =1, ODT = 75 Ohm */
  102 + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
  103 + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
  104 +}
  105 +
  106 +phys_size_t initdram(int board_type)
  107 +{
  108 + phys_size_t dram_size;
  109 +
  110 + puts("Initializing....using SPD\n");
  111 +
  112 + dram_size = fsl_ddr_sdram();
  113 +
  114 + dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  115 + dram_size *= 0x100000;
  116 +
  117 + puts(" DDR: ");
  118 + return dram_size;
  119 +}
board/freescale/t208xqds/ddr.h
Diff comments   View file @ 254887a
  1 +/*
  2 + * Copyright 2013 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef __DDR_H__
  8 +#define __DDR_H__
  9 +struct board_specific_parameters {
  10 + u32 n_ranks;
  11 + u32 datarate_mhz_high;
  12 + u32 rank_gb;
  13 + u32 clk_adjust;
  14 + u32 wrlvl_start;
  15 + u32 wrlvl_ctl_2;
  16 + u32 wrlvl_ctl_3;
  17 +};
  18 +
  19 +/*
  20 + * These tables contain all valid speeds we want to override with board
  21 + * specific parameters. datarate_mhz_high values need to be in ascending order
  22 + * for each n_ranks group.
  23 + */
  24 +
  25 +static const struct board_specific_parameters udimm0[] = {
  26 + /*
  27 + * memory controller 0
  28 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
  29 + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
  30 + */
  31 + {2, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
  32 + {2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
  33 + {2, 1600, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b},
  34 + {2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
  35 + {2, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c},
  36 + {2, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b},
  37 + {1, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
  38 + {1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
  39 + {1, 1600, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b},
  40 + {1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
  41 + {1, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c},
  42 + {1, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b},
  43 + {}
  44 +};
  45 +
  46 +static const struct board_specific_parameters rdimm0[] = {
  47 + /*
  48 + * memory controller 0
  49 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
  50 + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
  51 + */
  52 + /* TODO: need tuning these parameters if RDIMM is used */
  53 + {4, 1350, 0, 5, 9, 0x08070605, 0x06070806},
  54 + {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906},
  55 + {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
  56 + {2, 1350, 0, 5, 9, 0x08070605, 0x06070806},
  57 + {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
  58 + {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
  59 + {1, 1350, 0, 5, 9, 0x08070605, 0x06070806},
  60 + {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
  61 + {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07},
  62 + {}
  63 +};
  64 +
  65 +static const struct board_specific_parameters *udimms[] = {
  66 + udimm0,
  67 +};
  68 +
  69 +static const struct board_specific_parameters *rdimms[] = {
  70 + rdimm0,
  71 +};
  72 +#endif
board/freescale/t208xqds/eth_t208xqds.c
Diff comments   View file @ 254887a
  1 +/*
  2 + * Copyright 2013 Freescale Semiconductor, Inc.
  3 + *
  4 + * Shengzhou Liu <Shengzhou.Liu@freescale.com>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <command.h>
  11 +#include <netdev.h>
  12 +#include <asm/mmu.h>
  13 +#include <asm/processor.h>
  14 +#include <asm/immap_85xx.h>
  15 +#include <asm/fsl_law.h>
  16 +#include <asm/fsl_serdes.h>
  17 +#include <asm/fsl_portals.h>
  18 +#include <asm/fsl_liodn.h>
  19 +#include <malloc.h>
  20 +#include <fm_eth.h>
  21 +#include <fsl_mdio.h>
  22 +#include <miiphy.h>
  23 +#include <phy.h>
  24 +#include <asm/fsl_dtsec.h>
  25 +#include <asm/fsl_serdes.h>
  26 +#include "../common/qixis.h"
  27 +#include "../common/fman.h"
  28 +#include "t208xqds_qixis.h"
  29 +
  30 +#define EMI_NONE 0xFFFFFFFF
  31 +#define EMI1_RGMII1 0
  32 +#define EMI1_RGMII2 1
  33 +#define EMI1_SLOT1 2
  34 +#if defined(CONFIG_T2080QDS)
  35 +#define EMI1_SLOT2 6
  36 +#define EMI1_SLOT3 3
  37 +#define EMI1_SLOT4 4
  38 +#define EMI1_SLOT5 5
  39 +#elif defined(CONFIG_T2081QDS)
  40 +#define EMI1_SLOT2 3
  41 +#define EMI1_SLOT3 4
  42 +#define EMI1_SLOT5 5
  43 +#define EMI1_SLOT6 6
  44 +#define EMI1_SLOT7 7
  45 +#endif
  46 +#define EMI2 8
  47 +
  48 +static int mdio_mux[NUM_FM_PORTS];
  49 +
  50 +static const char * const mdio_names[] = {
  51 +#if defined(CONFIG_T2080QDS)
  52 + "T2080QDS_MDIO_RGMII1",
  53 + "T2080QDS_MDIO_RGMII2",
  54 + "T2080QDS_MDIO_SLOT1",
  55 + "T2080QDS_MDIO_SLOT3",
  56 + "T2080QDS_MDIO_SLOT4",
  57 + "T2080QDS_MDIO_SLOT5",
  58 + "T2080QDS_MDIO_SLOT2",
  59 + "T2080QDS_MDIO_10GC",
  60 +#elif defined(CONFIG_T2081QDS)
  61 + "T2081QDS_MDIO_RGMII1",
  62 + "T2081QDS_MDIO_RGMII2",
  63 + "T2081QDS_MDIO_SLOT1",
  64 + "T2081QDS_MDIO_SLOT2",
  65 + "T2081QDS_MDIO_SLOT3",
  66 + "T2081QDS_MDIO_SLOT5",
  67 + "T2081QDS_MDIO_SLOT6",
  68 + "T2081QDS_MDIO_SLOT7",
  69 + "T2081QDS_MDIO_10GC",
  70 +#endif
  71 +};
  72 +
  73 +/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
  74 +#if defined(CONFIG_T2080QDS)
  75 +static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
  76 +#elif defined(CONFIG_T2081QDS)
  77 +static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1};
  78 +#endif
  79 +
  80 +static const char *t208xqds_mdio_name_for_muxval(u8 muxval)
  81 +{
  82 + return mdio_names[muxval];
  83 +}
  84 +
  85 +struct mii_dev *mii_dev_for_muxval(u8 muxval)
  86 +{
  87 + struct mii_dev *bus;
  88 + const char *name = t208xqds_mdio_name_for_muxval(muxval);
  89 +
  90 + if (!name) {
  91 + printf("No bus for muxval %x\n", muxval);
  92 + return NULL;
  93 + }
  94 +
  95 + bus = miiphy_get_dev_by_name(name);
  96 +
  97 + if (!bus) {
  98 + printf("No bus by name %s\n", name);
  99 + return NULL;
  100 + }
  101 +
  102 + return bus;
  103 +}
  104 +
  105 +struct t208xqds_mdio {
  106 + u8 muxval;
  107 + struct mii_dev *realbus;
  108 +};
  109 +
  110 +static void t208xqds_mux_mdio(u8 muxval)
  111 +{
  112 + u8 brdcfg4;
  113 + if (muxval < 8) {
  114 + brdcfg4 = QIXIS_READ(brdcfg[4]);
  115 + brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
  116 + brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
  117 + QIXIS_WRITE(brdcfg[4], brdcfg4);
  118 + }
  119 +}
  120 +
  121 +static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad,
  122 + int regnum)
  123 +{
  124 + struct t208xqds_mdio *priv = bus->priv;
  125 +
  126 + t208xqds_mux_mdio(priv->muxval);
  127 +
  128 + return priv->realbus->read(priv->realbus, addr, devad, regnum);
  129 +}
  130 +
  131 +static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad,
  132 + int regnum, u16 value)
  133 +{
  134 + struct t208xqds_mdio *priv = bus->priv;
  135 +
  136 + t208xqds_mux_mdio(priv->muxval);
  137 +
  138 + return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
  139 +}
  140 +
  141 +static int t208xqds_mdio_reset(struct mii_dev *bus)
  142 +{
  143 + struct t208xqds_mdio *priv = bus->priv;
  144 +
  145 + return priv->realbus->reset(priv->realbus);
  146 +}
  147 +
  148 +static int t208xqds_mdio_init(char *realbusname, u8 muxval)
  149 +{
  150 + struct t208xqds_mdio *pmdio;
  151 + struct mii_dev *bus = mdio_alloc();
  152 +
  153 + if (!bus) {
  154 + printf("Failed to allocate t208xqds MDIO bus\n");
  155 + return -1;
  156 + }
  157 +
  158 + pmdio = malloc(sizeof(*pmdio));
  159 + if (!pmdio) {
  160 + printf("Failed to allocate t208xqds private data\n");
  161 + free(bus);
  162 + return -1;
  163 + }
  164 +
  165 + bus->read = t208xqds_mdio_read;
  166 + bus->write = t208xqds_mdio_write;
  167 + bus->reset = t208xqds_mdio_reset;
  168 + sprintf(bus->name, t208xqds_mdio_name_for_muxval(muxval));
  169 +
  170 + pmdio->realbus = miiphy_get_dev_by_name(realbusname);
  171 +
  172 + if (!pmdio->realbus) {
  173 + printf("No bus with name %s\n", realbusname);
  174 + free(bus);
  175 + free(pmdio);
  176 + return -1;
  177 + }
  178 +
  179 + pmdio->muxval = muxval;
  180 + bus->priv = pmdio;
  181 + return mdio_register(bus);
  182 +}
  183 +
  184 +void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
  185 + enum fm_port port, int offset)
  186 +{
  187 + int phy;
  188 + char alias[20];
  189 + struct fixed_link f_link;
  190 + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  191 + u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
  192 + FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  193 +
  194 + srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  195 +
  196 + if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
  197 + phy = fm_info_get_phy_address(port);
  198 + switch (port) {
  199 +#if defined(CONFIG_T2080QDS)
  200 + case FM1_DTSEC1:
  201 + case FM1_DTSEC2:
  202 + case FM1_DTSEC9:
  203 + case FM1_DTSEC10:
  204 + if (mdio_mux[port] == EMI1_SLOT2) {
  205 + sprintf(alias, "phy_sgmii_s2_%x", phy);
  206 + fdt_set_phy_handle(fdt, compat, addr, alias);
  207 + fdt_status_okay_by_alias(fdt, "emi1_slot2");
  208 + } else if (mdio_mux[port] == EMI1_SLOT3) {
  209 + sprintf(alias, "phy_sgmii_s3_%x", phy);
  210 + fdt_set_phy_handle(fdt, compat, addr, alias);
  211 + fdt_status_okay_by_alias(fdt, "emi1_slot3");
  212 + }
  213 + break;
  214 + case FM1_DTSEC5:
  215 + case FM1_DTSEC6:
  216 + if (mdio_mux[port] == EMI1_SLOT1) {
  217 + sprintf(alias, "phy_sgmii_s1_%x", phy);
  218 + fdt_set_phy_handle(fdt, compat, addr, alias);
  219 + fdt_status_okay_by_alias(fdt, "emi1_slot1");
  220 + } else if (mdio_mux[port] == EMI1_SLOT2) {
  221 + sprintf(alias, "phy_sgmii_s2_%x", phy);
  222 + fdt_set_phy_handle(fdt, compat, addr, alias);
  223 + fdt_status_okay_by_alias(fdt, "emi1_slot2");
  224 + }
  225 + break;
  226 +#elif defined(CONFIG_T2081QDS)
  227 + case FM1_DTSEC1:
  228 + case FM1_DTSEC2:
  229 + case FM1_DTSEC5:
  230 + case FM1_DTSEC6:
  231 + case FM1_DTSEC9:
  232 + case FM1_DTSEC10:
  233 + if (mdio_mux[port] == EMI1_SLOT2) {
  234 + sprintf(alias, "phy_sgmii_s2_%x", phy);
  235 + fdt_set_phy_handle(fdt, compat, addr, alias);
  236 + fdt_status_okay_by_alias(fdt, "emi1_slot2");
  237 + } else if (mdio_mux[port] == EMI1_SLOT3) {
  238 + sprintf(alias, "phy_sgmii_s3_%x", phy);
  239 + fdt_set_phy_handle(fdt, compat, addr, alias);
  240 + fdt_status_okay_by_alias(fdt, "emi1_slot3");
  241 + } else if (mdio_mux[port] == EMI1_SLOT5) {
  242 + sprintf(alias, "phy_sgmii_s5_%x", phy);
  243 + fdt_set_phy_handle(fdt, compat, addr, alias);
  244 + fdt_status_okay_by_alias(fdt, "emi1_slot5");
  245 + } else if (mdio_mux[port] == EMI1_SLOT6) {
  246 + sprintf(alias, "phy_sgmii_s6_%x", phy);
  247 + fdt_set_phy_handle(fdt, compat, addr, alias);
  248 + fdt_status_okay_by_alias(fdt, "emi1_slot6");
  249 + } else if (mdio_mux[port] == EMI1_SLOT7) {
  250 + sprintf(alias, "phy_sgmii_s7_%x", phy);
  251 + fdt_set_phy_handle(fdt, compat, addr, alias);
  252 + fdt_status_okay_by_alias(fdt, "emi1_slot7");
  253 + }
  254 + break;
  255 +#endif
  256 + default:
  257 + break;
  258 + }
  259 +
  260 + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
  261 + switch (srds_s1) {
  262 + case 0x66: /* XFI interface */
  263 + case 0x6b:
  264 + case 0x6c:
  265 + case 0x6d:
  266 + case 0x71:
  267 + f_link.phy_id = port;
  268 + f_link.duplex = 1;
  269 + f_link.link_speed = 10000;
  270 + f_link.pause = 0;
  271 + f_link.asym_pause = 0;
  272 + /* no PHY for XFI */
  273 + fdt_delprop(fdt, offset, "phy-handle");
  274 + fdt_setprop(fdt, offset, "fixed-link", &f_link,
  275 + sizeof(f_link));
  276 + break;
  277 + default:
  278 + break;
  279 + }
  280 + }
  281 +}
  282 +
  283 +void fdt_fixup_board_enet(void *fdt)
  284 +{
  285 + return;
  286 +}
  287 +
  288 +/*
  289 + * This function reads RCW to check if Serdes1{A:H} is configured
  290 + * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly
  291 + */
  292 +static void initialize_lane_to_slot(void)
  293 +{
  294 + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  295 + u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
  296 + FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  297 +
  298 + srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  299 +
  300 + switch (srds_s1) {
  301 +#if defined(CONFIG_T2080QDS)
  302 + case 0x51:
  303 + case 0x5f:
  304 + case 0x65:
  305 + case 0x6b:
  306 + case 0x71:
  307 + lane_to_slot[5] = 2;
  308 + lane_to_slot[6] = 2;
  309 + lane_to_slot[7] = 2;
  310 + break;
  311 + case 0xa6:
  312 + case 0x8e:
  313 + case 0x8f:
  314 + case 0x82:
  315 + case 0x83:
  316 + case 0xd3:
  317 + case 0xd9:
  318 + case 0xcb:
  319 + lane_to_slot[6] = 2;
  320 + lane_to_slot[7] = 2;
  321 + break;
  322 + case 0xda:
  323 + lane_to_slot[4] = 3;
  324 + lane_to_slot[5] = 3;
  325 + lane_to_slot[6] = 3;
  326 + lane_to_slot[7] = 3;
  327 + break;
  328 +#elif defined(CONFIG_T2081QDS)
  329 + case 0x6b:
  330 + lane_to_slot[4] = 1;
  331 + lane_to_slot[5] = 3;
  332 + lane_to_slot[6] = 3;
  333 + lane_to_slot[7] = 3;
  334 + break;
  335 + case 0xca:
  336 + case 0xcb:
  337 + lane_to_slot[1] = 7;
  338 + lane_to_slot[2] = 6;
  339 + lane_to_slot[3] = 5;
  340 + lane_to_slot[5] = 3;
  341 + lane_to_slot[6] = 3;
  342 + lane_to_slot[7] = 3;
  343 + break;
  344 + case 0xf2:
  345 + lane_to_slot[1] = 7;
  346 + lane_to_slot[2] = 7;
  347 + lane_to_slot[3] = 7;
  348 + lane_to_slot[5] = 4;
  349 + lane_to_slot[6] = 3;
  350 + lane_to_slot[7] = 7;
  351 + break;
  352 +#endif
  353 + default:
  354 + break;
  355 + }
  356 +}
  357 +
  358 +int board_eth_init(bd_t *bis)
  359 +{
  360 +#if defined(CONFIG_FMAN_ENET)
  361 + int i, idx, lane, slot, interface;
  362 + struct memac_mdio_info dtsec_mdio_info;
  363 + struct memac_mdio_info tgec_mdio_info;
  364 + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  365 + u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
  366 + u32 srds_s1;
  367 +
  368 + srds_s1 = in_be32(&gur->rcwsr[4]) &
  369 + FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  370 + srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  371 +
  372 + initialize_lane_to_slot();
  373 +
  374 + /* Initialize the mdio_mux array so we can recognize empty elements */
  375 + for (i = 0; i < NUM_FM_PORTS; i++)
  376 + mdio_mux[i] = EMI_NONE;
  377 +
  378 + dtsec_mdio_info.regs =
  379 + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
  380 +
  381 + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  382 +
  383 + /* Register the 1G MDIO bus */
  384 + fm_memac_mdio_init(bis, &dtsec_mdio_info);
  385 +
  386 + tgec_mdio_info.regs =
  387 + (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
  388 + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
  389 +
  390 + /* Register the 10G MDIO bus */
  391 + fm_memac_mdio_init(bis, &tgec_mdio_info);
  392 +
  393 + /* Register the muxing front-ends to the MDIO buses */
  394 + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
  395 + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
  396 + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
  397 + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
  398 + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
  399 +#if defined(CONFIG_T2080QDS)
  400 + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
  401 +#endif
  402 + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
  403 +#if defined(CONFIG_T2081QDS)
  404 + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
  405 + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
  406 +#endif
  407 + t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
  408 +
  409 + /* Set the two on-board RGMII PHY address */
  410 + fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
  411 + if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
  412 + FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII)
  413 + fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
  414 + else
  415 + fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
  416 +
  417 + switch (srds_s1) {
  418 + case 0x1c:
  419 + case 0x95:
  420 + case 0xa2:
  421 + case 0x94:
  422 + /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot2 */
  423 + fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
  424 + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
  425 + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
  426 + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
  427 + /* T2080QDS: SGMII in Slot2; T2081QDS: SGMII in Slot1 */
  428 + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
  429 + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
  430 + break;
  431 + case 0x51:
  432 + case 0x5f:
  433 + case 0x65:
  434 + /* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */
  435 + fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
  436 + /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */
  437 + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
  438 + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
  439 + break;
  440 + case 0x66:
  441 + /*
  442 + * XFI does not need a PHY to work, but to avoid U-boot use
  443 + * default PHY address which is zero to a MAC when it found
  444 + * a MAC has no PHY address, we give a PHY address to XFI
  445 + * MAC, and should not use a real XAUI PHY address, since
  446 + * MDIO can access it successfully, and then MDIO thinks
  447 + * the XAUI card is used for the XFI MAC, which will cause
  448 + * error.
  449 + */
  450 + fm_info_set_phy_address(FM1_10GEC1, 4);
  451 + fm_info_set_phy_address(FM1_10GEC2, 5);
  452 + fm_info_set_phy_address(FM1_10GEC3, 6);
  453 + fm_info_set_phy_address(FM1_10GEC4, 7);
  454 + break;
  455 + case 0x6b:
  456 + fm_info_set_phy_address(FM1_10GEC1, 4);
  457 + fm_info_set_phy_address(FM1_10GEC2, 5);
  458 + fm_info_set_phy_address(FM1_10GEC3, 6);
  459 + fm_info_set_phy_address(FM1_10GEC4, 7);
  460 + /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */
  461 + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
  462 + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
  463 + break;
  464 + case 0x6c:
  465 + case 0x6d:
  466 + fm_info_set_phy_address(FM1_10GEC1, 4);
  467 + fm_info_set_phy_address(FM1_10GEC2, 5);
  468 + /* T2080QDS: SGMII in Slot3; T2081QDS: in Slot2 */
  469 + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
  470 + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
  471 + break;
  472 + case 0x71:
  473 + /* SGMII in Slot3 */
  474 + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
  475 + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
  476 + /* SGMII in Slot2 */
  477 + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
  478 + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
  479 + break;
  480 + case 0xa6:
  481 + case 0x8e:
  482 + case 0x8f:
  483 + case 0x82:
  484 + case 0x83:
  485 + /* SGMII in Slot3 */
  486 + fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
  487 + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
  488 + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
  489 + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
  490 + /* SGMII in Slot2 */
  491 + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
  492 + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
  493 + break;
  494 + case 0xa4:
  495 + case 0x96:
  496 + case 0x8a:
  497 + /* SGMII in Slot3 */
  498 + fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
  499 + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
  500 + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
  501 + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
  502 + break;
  503 +#if defined(CONFIG_T2080QDS)
  504 + case 0xd9:
  505 + case 0xd3:
  506 + case 0xcb:
  507 + /* SGMII in Slot3 */
  508 + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
  509 + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
  510 + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
  511 + /* SGMII in Slot2 */
  512 + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
  513 + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
  514 + break;
  515 +#elif defined(CONFIG_T2081QDS)
  516 + case 0xca:
  517 + case 0xcb:
  518 + /* SGMII in Slot3 */
  519 + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
  520 + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
  521 + /* SGMII in Slot5 */
  522 + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
  523 + /* SGMII in Slot6 */
  524 + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
  525 + /* SGMII in Slot7 */
  526 + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
  527 + break;
  528 +#endif
  529 + case 0xf2:
  530 + /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */
  531 + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
  532 + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
  533 + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
  534 + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
  535 + break;
  536 + default:
  537 + break;
  538 + }
  539 +
  540 + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  541 + idx = i - FM1_DTSEC1;
  542 + interface = fm_info_get_enet_if(i);
  543 + switch (interface) {
  544 + case PHY_INTERFACE_MODE_SGMII:
  545 + lane = serdes_get_first_lane(FSL_SRDS_1,
  546 + SGMII_FM1_DTSEC1 + idx);
  547 + if (lane < 0)
  548 + break;
  549 + slot = lane_to_slot[lane];
  550 + debug("FM1@DTSEC%u expects SGMII in slot %u\n",
  551 + idx + 1, slot);
  552 + if (QIXIS_READ(present2) & (1 << (slot - 1)))
  553 + fm_disable_port(i);
  554 +
  555 + switch (slot) {
  556 + case 1:
  557 + mdio_mux[i] = EMI1_SLOT1;
  558 + fm_info_set_mdio(i, mii_dev_for_muxval(
  559 + mdio_mux[i]));
  560 + break;
  561 + case 2:
  562 + mdio_mux[i] = EMI1_SLOT2;
  563 + fm_info_set_mdio(i, mii_dev_for_muxval(
  564 + mdio_mux[i]));
  565 + break;
  566 + case 3:
  567 + mdio_mux[i] = EMI1_SLOT3;
  568 + fm_info_set_mdio(i, mii_dev_for_muxval(
  569 + mdio_mux[i]));
  570 + break;
  571 +#if defined(CONFIG_T2081QDS)
  572 + case 5:
  573 + mdio_mux[i] = EMI1_SLOT5;
  574 + fm_info_set_mdio(i, mii_dev_for_muxval(
  575 + mdio_mux[i]));
  576 + break;
  577 + case 6:
  578 + mdio_mux[i] = EMI1_SLOT6;
  579 + fm_info_set_mdio(i, mii_dev_for_muxval(
  580 + mdio_mux[i]));
  581 + break;
  582 + case 7:
  583 + mdio_mux[i] = EMI1_SLOT7;
  584 + fm_info_set_mdio(i, mii_dev_for_muxval(
  585 + mdio_mux[i]));
  586 + break;
  587 +#endif
  588 + }
  589 + break;
  590 + case PHY_INTERFACE_MODE_RGMII:
  591 + if (i == FM1_DTSEC3)
  592 + mdio_mux[i] = EMI1_RGMII1;
  593 + else if (i == FM1_DTSEC4 || FM1_DTSEC10)
  594 + mdio_mux[i] = EMI1_RGMII2;
  595 + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  596 + break;
  597 + default:
  598 + break;
  599 + }
  600 + }
  601 +
  602 + for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
  603 + idx = i - FM1_10GEC1;
  604 + switch (fm_info_get_enet_if(i)) {
  605 + case PHY_INTERFACE_MODE_XGMII:
  606 + if (srds_s1 == 0x51) {
  607 + lane = serdes_get_first_lane(FSL_SRDS_1,
  608 + XAUI_FM1_MAC9 + idx);
  609 + } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) {
  610 + lane = serdes_get_first_lane(FSL_SRDS_1,
  611 + HIGIG_FM1_MAC9 + idx);
  612 + } else {
  613 + if (i == FM1_10GEC1 || i == FM1_10GEC2)
  614 + lane = serdes_get_first_lane(FSL_SRDS_1,
  615 + XFI_FM1_MAC9 + idx);
  616 + else
  617 + lane = serdes_get_first_lane(FSL_SRDS_1,
  618 + XFI_FM1_MAC1 + idx);
  619 + }
  620 +
  621 + if (lane < 0)
  622 + break;
  623 + mdio_mux[i] = EMI2;
  624 + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  625 +
  626 + if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||
  627 + (srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
  628 + (srds_s1 == 0x71)) {
  629 + /* As XFI is in cage intead of a slot, so
  630 + * ensure doesn't disable the corresponding port
  631 + */
  632 + break;
  633 + }
  634 +
  635 + slot = lane_to_slot[lane];
  636 + if (QIXIS_READ(present2) & (1 << (slot - 1)))
  637 + fm_disable_port(i);
  638 + break;
  639 + default:
  640 + break;
  641 + }
  642 + }
  643 +
  644 + cpu_eth_init(bis);
  645 +#endif /* CONFIG_FMAN_ENET */
  646 +
  647 + return pci_eth_init(bis);
  648 +}
board/freescale/t208xqds/law.c
Diff comments   View file @ 254887a
  1 +/*
  2 + * Copyright 2008-2012 Freescale Semiconductor, Inc.
  3 + *
  4 + * (C) Copyright 2000
  5 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  6 + *
  7 + * SPDX-License-Identifier: GPL-2.0+
  8 + */
  9 +
  10 +#include <common.h>
  11 +#include <asm/fsl_law.h>
  12 +#include <asm/mmu.h>
  13 +
  14 +struct law_entry law_table[] = {
  15 + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
  16 +#ifdef CONFIG_SYS_BMAN_MEM_PHYS
  17 + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
  18 +#endif
  19 +#ifdef CONFIG_SYS_QMAN_MEM_PHYS
  20 + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
  21 +#endif
  22 +#ifdef QIXIS_BASE_PHYS
  23 + SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
  24 +#endif
  25 +#ifdef CONFIG_SYS_DCSRBAR_PHYS
  26 + /* Limit DCSR to 32M to access NPC Trace Buffer */
  27 + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
  28 +#endif
  29 +#ifdef CONFIG_SYS_NAND_BASE_PHYS
  30 + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
  31 +#endif
  32 +};
  33 +
  34 +int num_law_entries = ARRAY_SIZE(law_table);
board/freescale/t208xqds/pci.c
Diff comments   View file @ 254887a
  1 +/*
  2 + * Copyright 2007-2013 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <command.h>
  9 +#include <pci.h>
  10 +#include <asm/fsl_pci.h>
  11 +#include <libfdt.h>
  12 +#include <fdt_support.h>
  13 +#include <asm/fsl_serdes.h>
  14 +
  15 +void pci_init_board(void)
  16 +{
  17 + fsl_pcie_init_board(0);
  18 +}
  19 +
  20 +void pci_of_setup(void *blob, bd_t *bd)
  21 +{
  22 + FT_FSL_PCI_SETUP;
  23 +}
board/freescale/t208xqds/t2080_rcw.cfg
Diff comments   View file @ 254887a
  1 +#PBL preamble and RCW header
  2 +aa55aa55 010e0100
  3 +#SerDes Protocol: 0x66_0x16
  4 +#Core/DDR: 1533Mhz/2133MT/s
  5 +12100017 15000000 00000000 00000000
  6 +66160002 00008400 e8104000 c1000000
  7 +00000000 00000000 00000000 000307fc
  8 +00000000 00000000 00000000 00000004
board/freescale/t208xqds/t2081_rcw.cfg
Diff comments   View file @ 254887a
  1 +#PBL preamble and RCW header
  2 +aa55aa55 010e0100
  3 +#Default SerDes Protocol: 0x6C
  4 +#Core/DDR: 1533Mhz/2133MT/s
  5 +12100017 15000000 00000000 00000000
  6 +6c000002 00008000 e8104000 c1000000
  7 +00000000 00000000 00000000 000307fc
  8 +00000000 00000000 00000000 00000004
board/freescale/t208xqds/t208x_pbi.cfg
Diff comments   View file @ 254887a
  1 +#
  2 +# Copyright 2013 Freescale Semiconductor, Inc.
  3 +#
  4 +# SPDX-License-Identifier: GPL-2.0+
  5 +#
  6 +# Refer doc/README.pblimage for more details about how-to configure
  7 +# and create PBL boot image
  8 +#
  9 +
  10 +#PBI commands
  11 +#Initialize CPC1
  12 +09010000 00200400
  13 +09138000 00000000
  14 +091380c0 00000100
  15 +#512KB SRAM
  16 +09010100 00000000
  17 +09010104 fff80009
  18 +09010f00 08000000
  19 +#enable CPC1
  20 +09010000 80000000
  21 +#Configure LAW for CPC1
  22 +09000d00 00000000
  23 +09000d04 fff80000
  24 +09000d08 81000012
  25 +#Initialize eSPI controller, default configuration is slow for eSPI to
  26 +#load data, this configuration comes from u-boot eSPI driver.
  27 +09110000 80000403
  28 +09110020 2d170008
  29 +09110024 00100008
  30 +09110028 00100008
  31 +0911002c 00100008
  32 +#Errata for slowing down the MDC clock to make it <= 2.5 MHZ
  33 +094fc030 00008148
  34 +094fd030 00008148
  35 +#Configure alternate space
  36 +09000010 00000000
  37 +09000014 ff000000
  38 +09000018 81000000
  39 +#Flush PBL data
  40 +09138000 00000000
  41 +091380c0 00000000
board/freescale/t208xqds/t208xqds.c
Diff comments   View file @ 254887a
  1 +/*
  2 + * Copyright 2009-2013 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <command.h>
  9 +#include <i2c.h>
  10 +#include <netdev.h>
  11 +#include <linux/compiler.h>
  12 +#include <asm/mmu.h>
  13 +#include <asm/processor.h>
  14 +#include <asm/immap_85xx.h>
  15 +#include <asm/fsl_law.h>
  16 +#include <asm/fsl_serdes.h>
  17 +#include <asm/fsl_portals.h>
  18 +#include <asm/fsl_liodn.h>
  19 +#include <fm_eth.h>
  20 +
  21 +#include "../common/qixis.h"
  22 +#include "../common/vsc3316_3308.h"
  23 +#include "t208xqds.h"
  24 +#include "t208xqds_qixis.h"
  25 +
  26 +DECLARE_GLOBAL_DATA_PTR;
  27 +
  28 +int checkboard(void)
  29 +{
  30 + char buf[64];
  31 + u8 sw;
  32 + struct cpu_type *cpu = gd->arch.cpu;
  33 + static const char *freq[4] = {
  34 + "100.00MHZ(from 8T49N222A)", "125.00MHz",
  35 + "156.25MHZ", "100.00MHz"
  36 + };
  37 +
  38 + printf("Board: %sQDS, ", cpu->name);
  39 + sw = QIXIS_READ(arch);
  40 + printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
  41 + printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  42 +
  43 +#ifdef CONFIG_SDCARD
  44 + puts("SD/MMC\n");
  45 +#elif CONFIG_SPIFLASH
  46 + puts("SPI\n");
  47 +#else
  48 + sw = QIXIS_READ(brdcfg[0]);
  49 + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  50 +
  51 + if (sw < 0x8)
  52 + printf("vBank%d\n", sw);
  53 + else if (sw == 0x8)
  54 + puts("Promjet\n");
  55 + else if (sw == 0x9)
  56 + puts("NAND\n");
  57 + else
  58 + printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  59 +#endif
  60 +
  61 + printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
  62 + qixis_read_tag(buf), (int)qixis_read_minor());
  63 + /* the timestamp string contains "\n" at the end */
  64 + printf(" on %s", qixis_read_time(buf));
  65 +
  66 + puts("SERDES Reference Clocks:\n");
  67 + sw = QIXIS_READ(brdcfg[2]);
  68 + printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
  69 + freq[(sw >> 4) & 0x3]);
  70 + printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
  71 + freq[sw & 0x3]);
  72 +
  73 + return 0;
  74 +}
  75 +
  76 +int select_i2c_ch_pca9547(u8 ch)
  77 +{
  78 + int ret;
  79 +
  80 + ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  81 + if (ret) {
  82 + puts("PCA: failed to select proper channel\n");
  83 + return ret;
  84 + }
  85 +
  86 + return 0;
  87 +}
  88 +
  89 +int brd_mux_lane_to_slot(void)
  90 +{
  91 + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  92 + u32 srds_prtcl_s1;
  93 +
  94 + srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
  95 + FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  96 + srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  97 +#if defined(CONFIG_T2080QDS)
  98 + u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
  99 + FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  100 + srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
  101 +#endif
  102 +
  103 + switch (srds_prtcl_s1) {
  104 + case 0:
  105 + /* SerDes1 is not enabled */
  106 + break;
  107 +#if defined(CONFIG_T2080QDS)
  108 + case 0x1c:
  109 + case 0xa2:
  110 + /* SD1(A:D) => SLOT3 SGMII
  111 + * SD1(G:H) => SLOT1 SGMII
  112 + */
  113 + QIXIS_WRITE(brdcfg[12], 0x1a);
  114 + break;
  115 + case 0x94:
  116 + case 0x95:
  117 + /* SD1(A:B) => SLOT3 SGMII@1.25bps
  118 + * SD1(C:D) => SFP Module, SGMII@3.125bps
  119 + * SD1(E:H) => SLOT1 SGMII@1.25bps
  120 + */
  121 + case 0x96:
  122 + /* SD1(A:B) => SLOT3 SGMII@1.25bps
  123 + * SD1(C) => SFP Module, SGMII@3.125bps
  124 + * SD1(D) => SFP Module, SGMII@1.25bps
  125 + * SD1(E:H) => SLOT1 PCIe4 x4
  126 + */
  127 + QIXIS_WRITE(brdcfg[12], 0x3a);
  128 + break;
  129 + case 0x51:
  130 + /* SD1(A:D) => SLOT3 XAUI
  131 + * SD1(E) => SLOT1 PCIe4
  132 + * SD1(F:H) => SLOT2 SGMII
  133 + */
  134 + QIXIS_WRITE(brdcfg[12], 0x15);
  135 + break;
  136 + case 0x66:
  137 + case 0x67:
  138 + /* SD1(A:D) => XFI cage
  139 + * SD1(E:H) => SLOT1 PCIe4
  140 + */
  141 + QIXIS_WRITE(brdcfg[12], 0xfe);
  142 + break;
  143 + case 0x6b:
  144 + /* SD1(A:D) => XFI cage
  145 + * SD1(E) => SLOT1 PCIe4
  146 + * SD1(F:H) => SLOT2 SGMII
  147 + */
  148 + QIXIS_WRITE(brdcfg[12], 0xf1);
  149 + break;
  150 + case 0x6c:
  151 + case 0x6d:
  152 + /* SD1(A:B) => XFI cage
  153 + * SD1(C:D) => SLOT3 SGMII
  154 + * SD1(E:H) => SLOT1 PCIe4
  155 + */
  156 + QIXIS_WRITE(brdcfg[12], 0xda);
  157 + break;
  158 + case 0x6e:
  159 + /* SD1(A:B) => SFP Module, XFI
  160 + * SD1(C:D) => SLOT3 SGMII
  161 + * SD1(E:F) => SLOT1 PCIe4 x2
  162 + * SD1(G:H) => SLOT2 SGMII
  163 + */
  164 + QIXIS_WRITE(brdcfg[12], 0xd9);
  165 + break;
  166 + case 0xda:
  167 + /* SD1(A:H) => SLOT3 PCIe3 x8
  168 + */
  169 + QIXIS_WRITE(brdcfg[12], 0x0);
  170 + break;
  171 + case 0xc8:
  172 + /* SD1(A) => SLOT3 PCIe3 x1
  173 + * SD1(B) => SFP Module, SGMII@1.25bps
  174 + * SD1(C:D) => SFP Module, SGMII@3.125bps
  175 + * SD1(E:F) => SLOT1 PCIe4 x2
  176 + * SD1(G:H) => SLOT2 SGMII
  177 + */
  178 + QIXIS_WRITE(brdcfg[12], 0x79);
  179 + break;
  180 + case 0xab:
  181 + /* SD1(A:D) => SLOT3 PCIe3 x4
  182 + * SD1(E:H) => SLOT1 PCIe4 x4
  183 + */
  184 + QIXIS_WRITE(brdcfg[12], 0x1a);
  185 + break;
  186 +#elif defined(CONFIG_T2081QDS)
  187 + case 0x51:
  188 + /* SD1(A:D) => SLOT2 XAUI
  189 + * SD1(E) => SLOT1 PCIe4 x1
  190 + * SD1(F:H) => SLOT3 SGMII
  191 + */
  192 + QIXIS_WRITE(brdcfg[12], 0x98);
  193 + QIXIS_WRITE(brdcfg[13], 0x70);
  194 + break;
  195 + case 0x6b:
  196 + /* SD1(A:D) => XFI SFP Module
  197 + * SD1(E) => SLOT1 PCIe4 x1
  198 + * SD1(F:H) => SLOT3 SGMII
  199 + */
  200 + QIXIS_WRITE(brdcfg[12], 0x80);
  201 + QIXIS_WRITE(brdcfg[13], 0x70);
  202 + break;
  203 + case 0x6c:
  204 + /* SD1(A:B) => XFI SFP Module
  205 + * SD1(C:D) => SLOT2 SGMII
  206 + * SD1(E:H) => SLOT1 PCIe4 x4
  207 + */
  208 + QIXIS_WRITE(brdcfg[12], 0xe8);
  209 + QIXIS_WRITE(brdcfg[13], 0x0);
  210 + break;
  211 + case 0x6d:
  212 + /* SD1(A:B) => XFI SFP Module
  213 + * SD1(C:D) => SLOT2 SGMII
  214 + * SD1(E:H) => SLOT1 PCIe4 x4
  215 + */
  216 + QIXIS_WRITE(brdcfg[12], 0xe8);
  217 + QIXIS_WRITE(brdcfg[13], 0x0);
  218 + break;
  219 + case 0xaa:
  220 + case 0xab:
  221 + /* SD1(A:D) => SLOT2 PCIe3 x4
  222 + * SD1(F:H) => SLOT1 SGMI4 x4
  223 + */
  224 + QIXIS_WRITE(brdcfg[12], 0xf8);
  225 + QIXIS_WRITE(brdcfg[13], 0x0);
  226 + break;
  227 + case 0xca:
  228 + case 0xcb:
  229 + /* SD1(A) => SLOT2 PCIe3 x1
  230 + * SD1(B) => SLOT7 SGMII
  231 + * SD1(C) => SLOT6 SGMII
  232 + * SD1(D) => SLOT5 SGMII
  233 + * SD1(E) => SLOT1 PCIe4 x1
  234 + * SD1(F:H) => SLOT3 SGMII
  235 + */
  236 + QIXIS_WRITE(brdcfg[12], 0x80);
  237 + QIXIS_WRITE(brdcfg[13], 0x70);
  238 + break;
  239 + case 0xde:
  240 + case 0xdf:
  241 + /* SD1(A:D) => SLOT2 PCIe3 x4
  242 + * SD1(E) => SLOT1 PCIe4 x1
  243 + * SD1(F) => SLOT4 PCIe1 x1
  244 + * SD1(G) => SLOT3 PCIe2 x1
  245 + * SD1(H) => SLOT7 SGMII
  246 + */
  247 + QIXIS_WRITE(brdcfg[12], 0x98);
  248 + QIXIS_WRITE(brdcfg[13], 0x25);
  249 + break;
  250 + case 0xf2:
  251 + /* SD1(A) => SLOT2 PCIe3 x1
  252 + * SD1(B:D) => SLOT7 SGMII
  253 + * SD1(E) => SLOT1 PCIe4 x1
  254 + * SD1(F) => SLOT4 PCIe1 x1
  255 + * SD1(G) => SLOT3 PCIe2 x1
  256 + * SD1(H) => SLOT7 SGMII
  257 + */
  258 + QIXIS_WRITE(brdcfg[12], 0x81);
  259 + QIXIS_WRITE(brdcfg[13], 0xa5);
  260 + break;
  261 +#endif
  262 + default:
  263 + printf("WARNING: unsupported for SerDes1 Protocol %d\n",
  264 + srds_prtcl_s1);
  265 + return -1;
  266 + }
  267 +
  268 +#ifdef CONFIG_T2080QDS
  269 + switch (srds_prtcl_s2) {
  270 + case 0:
  271 + /* SerDes2 is not enabled */
  272 + break;
  273 + case 0x01:
  274 + case 0x02:
  275 + /* SD2(A:H) => SLOT4 PCIe1 */
  276 + QIXIS_WRITE(brdcfg[13], 0x10);
  277 + break;
  278 + case 0x15:
  279 + case 0x16:
  280 + /*
  281 + * SD2(A:D) => SLOT4 PCIe1
  282 + * SD2(E:F) => SLOT5 PCIe2
  283 + * SD2(G:H) => SATA1,SATA2
  284 + */
  285 + QIXIS_WRITE(brdcfg[13], 0xb0);
  286 + break;
  287 + case 0x18:
  288 + /*
  289 + * SD2(A:D) => SLOT4 PCIe1
  290 + * SD2(E:F) => SLOT5 Aurora
  291 + * SD2(G:H) => SATA1,SATA2
  292 + */
  293 + QIXIS_WRITE(brdcfg[13], 0x78);
  294 + break;
  295 + case 0x1f:
  296 + /*
  297 + * SD2(A:D) => SLOT4 PCIe1
  298 + * SD2(E:H) => SLOT5 PCIe2
  299 + */
  300 + QIXIS_WRITE(brdcfg[13], 0xa0);
  301 + break;
  302 + case 0x29:
  303 + case 0x2d:
  304 + case 0x2e:
  305 + /*
  306 + * SD2(A:D) => SLOT4 SRIO2
  307 + * SD2(E:H) => SLOT5 SRIO1
  308 + */
  309 + QIXIS_WRITE(brdcfg[13], 0xa0);
  310 + break;
  311 + case 0x36:
  312 + /*
  313 + * SD2(A:D) => SLOT4 SRIO2
  314 + * SD2(E:F) => Aurora
  315 + * SD2(G:H) => SATA1,SATA2
  316 + */
  317 + QIXIS_WRITE(brdcfg[13], 0x78);
  318 + break;
  319 + default:
  320 + printf("WARNING: unsupported for SerDes2 Protocol %d\n",
  321 + srds_prtcl_s2);
  322 + return -1;
  323 + }
  324 +#endif
  325 + return 0;
  326 +}
  327 +
  328 +int board_early_init_r(void)
  329 +{
  330 + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  331 + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  332 +
  333 + /*
  334 + * Remap Boot flash + PROMJET region to caching-inhibited
  335 + * so that flash can be erased properly.
  336 + */
  337 +
  338 + /* Flush d-cache and invalidate i-cache of any FLASH data */
  339 + flush_dcache();
  340 + invalidate_icache();
  341 +
  342 + /* invalidate existing TLB entry for flash + promjet */
  343 + disable_tlb(flash_esel);
  344 +
  345 + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  346 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  347 + 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  348 +
  349 + set_liodns();
  350 +#ifdef CONFIG_SYS_DPAA_QBMAN
  351 + setup_portals();
  352 +#endif
  353 +
  354 + /* Disable remote I2C connection to qixis fpga */
  355 + QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
  356 +
  357 + brd_mux_lane_to_slot();
  358 + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  359 +
  360 + return 0;
  361 +}
  362 +
  363 +unsigned long get_board_sys_clk(void)
  364 +{
  365 + u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  366 +#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
  367 + /* use accurate clock measurement */
  368 + int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
  369 + int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
  370 + u32 val;
  371 +
  372 + val = freq * base;
  373 + if (val) {
  374 + debug("SYS Clock measurement is: %d\n", val);
  375 + return val;
  376 + } else {
  377 + printf("Warning: SYS clock measurement is invalid, ");
  378 + printf("using value from brdcfg1.\n");
  379 + }
  380 +#endif
  381 +
  382 + switch (sysclk_conf & 0x0F) {
  383 + case QIXIS_SYSCLK_83:
  384 + return 83333333;
  385 + case QIXIS_SYSCLK_100:
  386 + return 100000000;
  387 + case QIXIS_SYSCLK_125:
  388 + return 125000000;
  389 + case QIXIS_SYSCLK_133:
  390 + return 133333333;
  391 + case QIXIS_SYSCLK_150:
  392 + return 150000000;
  393 + case QIXIS_SYSCLK_160:
  394 + return 160000000;
  395 + case QIXIS_SYSCLK_166:
  396 + return 166666666;
  397 + }
  398 + return 66666666;
  399 +}
  400 +
  401 +unsigned long get_board_ddr_clk(void)
  402 +{
  403 + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  404 +#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
  405 + /* use accurate clock measurement */
  406 + int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
  407 + int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
  408 + u32 val;
  409 +
  410 + val = freq * base;
  411 + if (val) {
  412 + debug("DDR Clock measurement is: %d\n", val);
  413 + return val;
  414 + } else {
  415 + printf("Warning: DDR clock measurement is invalid, ");
  416 + printf("using value from brdcfg1.\n");
  417 + }
  418 +#endif
  419 +
  420 + switch ((ddrclk_conf & 0x30) >> 4) {
  421 + case QIXIS_DDRCLK_100:
  422 + return 100000000;
  423 + case QIXIS_DDRCLK_125:
  424 + return 125000000;
  425 + case QIXIS_DDRCLK_133:
  426 + return 133333333;
  427 + }
  428 + return 66666666;
  429 +}
  430 +
  431 +int misc_init_r(void)
  432 +{
  433 + return 0;
  434 +}
  435 +
  436 +void ft_board_setup(void *blob, bd_t *bd)
  437 +{
  438 + phys_addr_t base;
  439 + phys_size_t size;
  440 +
  441 + ft_cpu_setup(blob, bd);
  442 +
  443 + base = getenv_bootm_low();
  444 + size = getenv_bootm_size();
  445 +
  446 + fdt_fixup_memory(blob, (u64)base, (u64)size);
  447 +
  448 +#ifdef CONFIG_PCI
  449 + pci_of_setup(blob, bd);
  450 +#endif
  451 +
  452 + fdt_fixup_liodn(blob);
  453 + fdt_fixup_dr_usb(blob, bd);
  454 +
  455 +#ifdef CONFIG_SYS_DPAA_FMAN
  456 + fdt_fixup_fman_ethernet(blob);
  457 + fdt_fixup_board_enet(blob);
  458 +#endif
  459 +}
board/freescale/t208xqds/t208xqds.h
Diff comments   View file @ 254887a
  1 +/*
  2 + * Copyright 2011-2013 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef __CORENET_DS_H__
  8 +#define __CORENET_DS_H__
  9 +
  10 +void fdt_fixup_board_enet(void *blob);
  11 +void pci_of_setup(void *blob, bd_t *bd);
  12 +
  13 +#endif
board/freescale/t208xqds/t208xqds_qixis.h
Diff comments   View file @ 254887a
  1 +/*
  2 + * Copyright 2013 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef __T208xQDS_QIXIS_H__
  8 +#define __T208xQDS_QIXIS_H__
  9 +
  10 +/* Definitions of QIXIS Registers for T208xQDS */
  11 +
  12 +#define QIXIS_SRDS1CLK_122 0x5a
  13 +#define QIXIS_SRDS1CLK_125 0x5e
  14 +
  15 +
  16 +/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
  17 +#define BRDCFG4_EMISEL_MASK 0xE0
  18 +#define BRDCFG4_EMISEL_SHIFT 5
  19 +
  20 +/* SYSCLK */
  21 +#define QIXIS_SYSCLK_66 0x0
  22 +#define QIXIS_SYSCLK_83 0x1
  23 +#define QIXIS_SYSCLK_100 0x2
  24 +#define QIXIS_SYSCLK_125 0x3
  25 +#define QIXIS_SYSCLK_133 0x4
  26 +#define QIXIS_SYSCLK_150 0x5
  27 +#define QIXIS_SYSCLK_160 0x6
  28 +#define QIXIS_SYSCLK_166 0x7
  29 +
  30 +/* DDRCLK */
  31 +#define QIXIS_DDRCLK_66 0x0
  32 +#define QIXIS_DDRCLK_100 0x1
  33 +#define QIXIS_DDRCLK_125 0x2
  34 +#define QIXIS_DDRCLK_133 0x3
  35 +
  36 +#define BRDCFG5_IRE 0x20 /* i2c Remote i2c1 enable */
  37 +
  38 +#define BRDCFG9_SFP_TX_EN 0x10
  39 +
  40 +#define BRDCFG12_SD3EN_MASK 0x20
  41 +#define BRDCFG12_SD3MX_MASK 0x08
  42 +#define BRDCFG12_SD3MX_SLOT5 0x08
  43 +#define BRDCFG12_SD3MX_SLOT6 0x00
  44 +#define BRDCFG12_SD4EN_MASK 0x04
  45 +#define BRDCFG12_SD4MX_MASK 0x03
  46 +#define BRDCFG12_SD4MX_SLOT7 0x02
  47 +#define BRDCFG12_SD4MX_SLOT8 0x01
  48 +#define BRDCFG12_SD4MX_AURO_SATA 0x00
  49 +#endif
board/freescale/t208xqds/tlb.c
Diff comments   View file @ 254887a
  1 +/*
  2 + * Copyright 2008-2013 Freescale Semiconductor, Inc.
  3 + *
  4 + * (C) Copyright 2000
  5 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  6 + *
  7 + * SPDX-License-Identifier: GPL-2.0+
  8 + */
  9 +
  10 +#include <common.h>
  11 +#include <asm/mmu.h>
  12 +
  13 +struct fsl_e_tlb_entry tlb_table[] = {
  14 + /* TLB 0 - for temp stack in cache */
  15 + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
  16 + CONFIG_SYS_INIT_RAM_ADDR_PHYS,
  17 + MAS3_SX|MAS3_SW|MAS3_SR, 0,
  18 + 0, 0, BOOKE_PAGESZ_4K, 0),
  19 + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  20 + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
  21 + MAS3_SX|MAS3_SW|MAS3_SR, 0,
  22 + 0, 0, BOOKE_PAGESZ_4K, 0),
  23 + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  24 + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
  25 + MAS3_SX|MAS3_SW|MAS3_SR, 0,
  26 + 0, 0, BOOKE_PAGESZ_4K, 0),
  27 + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  28 + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  29 + MAS3_SX|MAS3_SW|MAS3_SR, 0,
  30 + 0, 0, BOOKE_PAGESZ_4K, 0),
  31 +
  32 + /* TLB 1 */
  33 + /* *I*** - Covers boot page */
  34 +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
  35 + /*
  36 + * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
  37 + * SRAM is at 0xfff00000, it covered the 0xfffff000.
  38 + */
  39 + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
  40 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  41 + 0, 0, BOOKE_PAGESZ_1M, 1),
  42 +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  43 + /*
  44 + * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
  45 + * space is at 0xfff00000, it covered the 0xfffff000.
  46 + */
  47 + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
  48 + CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
  49 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
  50 + 0, 0, BOOKE_PAGESZ_1M, 1),
  51 +#else
  52 + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  53 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  54 + 0, 0, BOOKE_PAGESZ_4K, 1),
  55 +#endif
  56 +
  57 + /* *I*G* - CCSRBAR */
  58 + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  59 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  60 + 0, 1, BOOKE_PAGESZ_16M, 1),
  61 +
  62 + /* *I*G* - Flash, localbus */
  63 + /* This will be changed to *I*G* after relocation to RAM. */
  64 + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  65 + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  66 + 0, 2, BOOKE_PAGESZ_256M, 1),
  67 +
  68 + /* *I*G* - PCIe 1, 0x80000000 */
  69 + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  70 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  71 + 0, 3, BOOKE_PAGESZ_512M, 1),
  72 +
  73 + /* *I*G* - PCIe 2, 0xa0000000 */
  74 + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
  75 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  76 + 0, 4, BOOKE_PAGESZ_256M, 1),
  77 +
  78 + /* *I*G* - PCIe 3, 0xb0000000 */
  79 + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
  80 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  81 + 0, 5, BOOKE_PAGESZ_256M, 1),
  82 +
  83 +
  84 + /* *I*G* - PCIe 4, 0xc0000000 */
  85 + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS,
  86 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  87 + 0, 6, BOOKE_PAGESZ_256M, 1),
  88 +
  89 + /* *I*G* - PCI I/O */
  90 + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  91 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  92 + 0, 7, BOOKE_PAGESZ_256K, 1),
  93 +
  94 + /* Bman/Qman */
  95 +#ifdef CONFIG_SYS_BMAN_MEM_PHYS
  96 + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
  97 + MAS3_SX|MAS3_SW|MAS3_SR, 0,
  98 + 0, 9, BOOKE_PAGESZ_16M, 1),
  99 + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
  100 + CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
  101 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  102 + 0, 10, BOOKE_PAGESZ_16M, 1),
  103 +#endif
  104 +#ifdef CONFIG_SYS_QMAN_MEM_PHYS
  105 + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
  106 + MAS3_SX|MAS3_SW|MAS3_SR, 0,
  107 + 0, 11, BOOKE_PAGESZ_16M, 1),
  108 + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
  109 + CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
  110 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  111 + 0, 12, BOOKE_PAGESZ_16M, 1),
  112 +#endif
  113 +#ifdef CONFIG_SYS_DCSRBAR_PHYS
  114 + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
  115 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  116 + 0, 13, BOOKE_PAGESZ_32M, 1),
  117 +#endif
  118 +#ifdef CONFIG_SYS_NAND_BASE
  119 + /*
  120 + * *I*G - NAND
  121 + * entry 14 and 15 has been used hard coded, they will be disabled
  122 + * in cpu_init_f, so we use entry 16 for nand.
  123 + */
  124 + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
  125 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  126 + 0, 16, BOOKE_PAGESZ_64K, 1),
  127 +#endif
  128 +#ifdef QIXIS_BASE_PHYS
  129 + SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
  130 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  131 + 0, 17, BOOKE_PAGESZ_4K, 1),
  132 +#endif
  133 +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  134 + /*
  135 + * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
  136 + * fetching ucode and ENV from master
  137 + */
  138 + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
  139 + CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
  140 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
  141 + 0, 18, BOOKE_PAGESZ_1M, 1),
  142 +#endif
  143 +
  144 +};
  145 +
  146 +int num_tlb_entries = ARRAY_SIZE(tlb_table);
... ... @@ -972,11 +972,16 @@
972 972 Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com>
973 973 Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com>
974 974 Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T1042RDB_PI:PPC_T1042 Poonam Aggrwal <poonam.aggrwal@freescale.com>
975   -Active powerpc mpc85xx - freescale t2080qds T2080QDS T2080QDS:PPC_T2080 -
976   -Active powerpc mpc85xx - freescale t2080qds T2080QDS_NAND T2080QDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
977   -Active powerpc mpc85xx - freescale t2080qds T2080QDS_SDCARD T2080QDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
978   -Active powerpc mpc85xx - freescale t2080qds T2080QDS_SPIFLASH T2080QDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
979   -Active powerpc mpc85xx - freescale t2080qds T2080QDS_SRIO_PCIE_BOOT T2080QDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
  975 +Active powerpc mpc85xx - freescale t208xqds T2080QDS T208xQDS:PPC_T2080
  976 +Active powerpc mpc85xx - freescale t208xqds T2080QDS_SDCARD T208xQDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000
  977 +Active powerpc mpc85xx - freescale t208xqds T2080QDS_SPIFLASH T208xQDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000
  978 +Active powerpc mpc85xx - freescale t208xqds T2080QDS_NAND T208xQDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000
  979 +Active powerpc mpc85xx - freescale t208xqds T2080QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000
  980 +Active powerpc mpc85xx - freescale t208xqds T2081QDS T208xQDS:PPC_T2081
  981 +Active powerpc mpc85xx - freescale t208xqds T2081QDS_SDCARD T208xQDS:PPC_T2081,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000
  982 +Active powerpc mpc85xx - freescale t208xqds T2081QDS_SPIFLASH T208xQDS:PPC_T2081,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000
  983 +Active powerpc mpc85xx - freescale t208xqds T2081QDS_NAND T208xQDS:PPC_T2081,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000
  984 +Active powerpc mpc85xx - freescale t208xqds T2081QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000
980 985 Active powerpc mpc85xx - freescale t4qds T4160QDS T4240QDS:PPC_T4160 -
981 986 Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
982 987 Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
include/configs/T2080QDS.h
View file @ 254887a
1   -/*
2   - * Copyright 2011-2013 Freescale Semiconductor, Inc.
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -/*
8   - * T2080 QDS board configuration file
9   - */
10   -
11   -#ifndef __T2080QDS_H
12   -#define __T2080QDS_H
13   -
14   -#define CONFIG_T2080QDS
15   -#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
16   -#define CONFIG_MMC
17   -#define CONFIG_SPI_FLASH
18   -#define CONFIG_USB_EHCI
19   -#define CONFIG_FSL_SATA_V2
20   -#define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
21   -#define CONFIG_SRIO1 /* SRIO port 1 */
22   -#define CONFIG_SRIO2 /* SRIO port 2 */
23   -
24   -/* High Level Configuration Options */
25   -#define CONFIG_PHYS_64BIT
26   -#define CONFIG_BOOKE
27   -#define CONFIG_E500 /* BOOKE e500 family */
28   -#define CONFIG_E500MC /* BOOKE e500mc family */
29   -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
30   -#define CONFIG_MP /* support multiple processors */
31   -#define CONFIG_ENABLE_36BIT_PHYS
32   -
33   -#ifdef CONFIG_PHYS_64BIT
34   -#define CONFIG_ADDR_MAP 1
35   -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
36   -#endif
37   -
38   -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
39   -#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
40   -#define CONFIG_FSL_IFC /* Enable IFC Support */
41   -#define CONFIG_FSL_LAW /* Use common FSL init code */
42   -#define CONFIG_ENV_OVERWRITE
43   -
44   -#ifdef CONFIG_RAMBOOT_PBL
45   -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
46   -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
47   -#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t2080qds/t2080_pbi.cfg
48   -#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t2080qds/t2080_rcw.cfg
49   -#endif
50   -
51   -#define CONFIG_SRIO_PCIE_BOOT_MASTER
52   -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
53   -/* Set 1M boot space */
54   -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
55   -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
56   - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
57   -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
58   -#define CONFIG_SYS_NO_FLASH
59   -#endif
60   -
61   -#ifndef CONFIG_SYS_TEXT_BASE
62   -#define CONFIG_SYS_TEXT_BASE 0xeff40000
63   -#endif
64   -
65   -#ifndef CONFIG_RESET_VECTOR_ADDRESS
66   -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
67   -#endif
68   -
69   -/*
70   - * These can be toggled for performance analysis, otherwise use default.
71   - */
72   -#define CONFIG_SYS_CACHE_STASHING
73   -#define CONFIG_BTB /* toggle branch predition */
74   -#define CONFIG_DDR_ECC
75   -#ifdef CONFIG_DDR_ECC
76   -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
77   -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
78   -#endif
79   -
80   -#ifdef CONFIG_SYS_NO_FLASH
81   -#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
82   -#define CONFIG_ENV_IS_NOWHERE
83   -#endif
84   -#else
85   -#define CONFIG_FLASH_CFI_DRIVER
86   -#define CONFIG_SYS_FLASH_CFI
87   -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
88   -#endif
89   -
90   -#if defined(CONFIG_SPIFLASH)
91   -#define CONFIG_SYS_EXTRA_ENV_RELOC
92   -#define CONFIG_ENV_IS_IN_SPI_FLASH
93   -#define CONFIG_ENV_SPI_BUS 0
94   -#define CONFIG_ENV_SPI_CS 0
95   -#define CONFIG_ENV_SPI_MAX_HZ 10000000
96   -#define CONFIG_ENV_SPI_MODE 0
97   -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
98   -#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
99   -#define CONFIG_ENV_SECT_SIZE 0x10000
100   -#elif defined(CONFIG_SDCARD)
101   -#define CONFIG_SYS_EXTRA_ENV_RELOC
102   -#define CONFIG_ENV_IS_IN_MMC
103   -#define CONFIG_SYS_MMC_ENV_DEV 0
104   -#define CONFIG_ENV_SIZE 0x2000
105   -#define CONFIG_ENV_OFFSET (512 * 1658)
106   -#elif defined(CONFIG_NAND)
107   -#define CONFIG_SYS_EXTRA_ENV_RELOC
108   -#define CONFIG_ENV_IS_IN_NAND
109   -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
110   -#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
111   -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
112   -#define CONFIG_ENV_IS_IN_REMOTE
113   -#define CONFIG_ENV_ADDR 0xffe20000
114   -#define CONFIG_ENV_SIZE 0x2000
115   -#elif defined(CONFIG_ENV_IS_NOWHERE)
116   -#define CONFIG_ENV_SIZE 0x2000
117   -#else
118   -#define CONFIG_ENV_IS_IN_FLASH
119   -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
120   -#define CONFIG_ENV_SIZE 0x2000
121   -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
122   -#endif
123   -
124   -#ifndef __ASSEMBLY__
125   -unsigned long get_board_sys_clk(void);
126   -unsigned long get_board_ddr_clk(void);
127   -#endif
128   -
129   -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
130   -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
131   -
132   -/*
133   - * Config the L3 Cache as L3 SRAM
134   - */
135   -#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
136   -
137   -#define CONFIG_SYS_DCSRBAR 0xf0000000
138   -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
139   -
140   -/* EEPROM */
141   -#define CONFIG_ID_EEPROM
142   -#define CONFIG_SYS_I2C_EEPROM_NXID
143   -#define CONFIG_SYS_EEPROM_BUS_NUM 0
144   -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
145   -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
146   -
147   -/*
148   - * DDR Setup
149   - */
150   -#define CONFIG_VERY_BIG_RAM
151   -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
152   -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
153   -#define CONFIG_DIMM_SLOTS_PER_CTLR 1
154   -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
155   -#define CONFIG_DDR_SPD
156   -#define CONFIG_SYS_FSL_DDR3
157   -#undef CONFIG_FSL_DDR_INTERACTIVE
158   -#define CONFIG_SYS_SPD_BUS_NUM 0
159   -#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
160   -#define SPD_EEPROM_ADDRESS1 0x51
161   -#define SPD_EEPROM_ADDRESS2 0x52
162   -#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
163   -#define CTRL_INTLV_PREFERED cacheline
164   -
165   -/*
166   - * IFC Definitions
167   - */
168   -#define CONFIG_SYS_FLASH_BASE 0xe0000000
169   -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
170   -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
171   -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
172   - + 0x8000000) | \
173   - CSPR_PORT_SIZE_16 | \
174   - CSPR_MSEL_NOR | \
175   - CSPR_V)
176   -#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
177   -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
178   - CSPR_PORT_SIZE_16 | \
179   - CSPR_MSEL_NOR | \
180   - CSPR_V)
181   -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
182   -/* NOR Flash Timing Params */
183   -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
184   -
185   -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
186   - FTIM0_NOR_TEADC(0x5) | \
187   - FTIM0_NOR_TEAHC(0x5))
188   -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
189   - FTIM1_NOR_TRAD_NOR(0x1A) |\
190   - FTIM1_NOR_TSEQRAD_NOR(0x13))
191   -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
192   - FTIM2_NOR_TCH(0x4) | \
193   - FTIM2_NOR_TWPH(0x0E) | \
194   - FTIM2_NOR_TWP(0x1c))
195   -#define CONFIG_SYS_NOR_FTIM3 0x0
196   -
197   -#define CONFIG_SYS_FLASH_QUIET_TEST
198   -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
199   -
200   -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
201   -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
202   -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
203   -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
204   -
205   -#define CONFIG_SYS_FLASH_EMPTY_INFO
206   -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
207   - + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
208   -
209   -#define CONFIG_FSL_QIXIS /* use common QIXIS code */
210   -#define QIXIS_BASE 0xffdf0000
211   -#define QIXIS_LBMAP_SWITCH 6
212   -#define QIXIS_LBMAP_MASK 0x0f
213   -#define QIXIS_LBMAP_SHIFT 0
214   -#define QIXIS_LBMAP_DFLTBANK 0x00
215   -#define QIXIS_LBMAP_ALTBANK 0x04
216   -#define QIXIS_RST_CTL_RESET 0x83
217   -#define QIXIS_RST_FORCE_MEM 0x1
218   -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
219   -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
220   -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
221   -#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
222   -
223   -#define CONFIG_SYS_CSPR3_EXT (0xf)
224   -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
225   - | CSPR_PORT_SIZE_8 \
226   - | CSPR_MSEL_GPCM \
227   - | CSPR_V)
228   -#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
229   -#define CONFIG_SYS_CSOR3 0x0
230   -/* QIXIS Timing parameters for IFC CS3 */
231   -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
232   - FTIM0_GPCM_TEADC(0x0e) | \
233   - FTIM0_GPCM_TEAHC(0x0e))
234   -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
235   - FTIM1_GPCM_TRAD(0x3f))
236   -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
237   - FTIM2_GPCM_TCH(0x0) | \
238   - FTIM2_GPCM_TWP(0x1f))
239   -#define CONFIG_SYS_CS3_FTIM3 0x0
240   -
241   -/* NAND Flash on IFC */
242   -#define CONFIG_NAND_FSL_IFC
243   -#define CONFIG_SYS_NAND_BASE 0xff800000
244   -#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
245   -
246   -#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
247   -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
248   - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
249   - | CSPR_MSEL_NAND /* MSEL = NAND */ \
250   - | CSPR_V)
251   -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
252   -
253   -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
254   - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
255   - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
256   - | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
257   - | CSOR_NAND_PGS_2K /* Page Size = 2K */\
258   - | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
259   - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
260   -
261   -#define CONFIG_SYS_NAND_ONFI_DETECTION
262   -
263   -/* ONFI NAND Flash mode0 Timing Params */
264   -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
265   - FTIM0_NAND_TWP(0x18) | \
266   - FTIM0_NAND_TWCHT(0x07) | \
267   - FTIM0_NAND_TWH(0x0a))
268   -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
269   - FTIM1_NAND_TWBE(0x39) | \
270   - FTIM1_NAND_TRR(0x0e) | \
271   - FTIM1_NAND_TRP(0x18))
272   -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
273   - FTIM2_NAND_TREH(0x0a) | \
274   - FTIM2_NAND_TWHRE(0x1e))
275   -#define CONFIG_SYS_NAND_FTIM3 0x0
276   -
277   -#define CONFIG_SYS_NAND_DDR_LAW 11
278   -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
279   -#define CONFIG_SYS_MAX_NAND_DEVICE 1
280   -#define CONFIG_MTD_NAND_VERIFY_WRITE
281   -#define CONFIG_CMD_NAND
282   -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
283   -
284   -#if defined(CONFIG_NAND)
285   -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
286   -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
287   -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
288   -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
289   -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
290   -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
291   -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
292   -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
293   -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
294   -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
295   -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
296   -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
297   -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
298   -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
299   -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
300   -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
301   -#else
302   -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
303   -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
304   -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
305   -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
306   -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
307   -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
308   -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
309   -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
310   -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
311   -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
312   -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
313   -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
314   -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
315   -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
316   -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
317   -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
318   -#endif
319   -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
320   -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
321   -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
322   -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
323   -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
324   -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
325   -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
326   -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
327   -
328   -#if defined(CONFIG_RAMBOOT_PBL)
329   -#define CONFIG_SYS_RAMBOOT
330   -#endif
331   -
332   -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
333   -#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
334   -#define CONFIG_MISC_INIT_R
335   -#define CONFIG_HWCONFIG
336   -
337   -/* define to use L1 as initial stack */
338   -#define CONFIG_L1_INIT_RAM
339   -#define CONFIG_SYS_INIT_RAM_LOCK
340   -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
341   -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
342   -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
343   -/* The assembler doesn't like typecast */
344   -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
345   - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
346   - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
347   -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
348   -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
349   - GENERATED_GBL_DATA_SIZE)
350   -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
351   -#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
352   -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
353   -
354   -/*
355   - * Serial Port
356   - */
357   -#define CONFIG_CONS_INDEX 1
358   -#define CONFIG_SYS_NS16550
359   -#define CONFIG_SYS_NS16550_SERIAL
360   -#define CONFIG_SYS_NS16550_REG_SIZE 1
361   -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
362   -#define CONFIG_SYS_BAUDRATE_TABLE \
363   - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
364   -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
365   -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
366   -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
367   -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
368   -
369   -/* Use the HUSH parser */
370   -#define CONFIG_SYS_HUSH_PARSER
371   -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
372   -
373   -/* pass open firmware flat tree */
374   -#define CONFIG_OF_LIBFDT
375   -#define CONFIG_OF_BOARD_SETUP
376   -#define CONFIG_OF_STDOUT_VIA_ALIAS
377   -
378   -/* new uImage format support */
379   -#define CONFIG_FIT
380   -#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
381   -
382   -/*
383   - * I2C
384   - */
385   -#define CONFIG_SYS_I2C
386   -#define CONFIG_SYS_I2C_FSL
387   -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
388   -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
389   -#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
390   -#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
391   -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
392   -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
393   -#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
394   -#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
395   -#define CONFIG_SYS_FSL_I2C_SPEED 100000
396   -#define CONFIG_SYS_FSL_I2C2_SPEED 100000
397   -#define CONFIG_SYS_FSL_I2C3_SPEED 100000
398   -#define CONFIG_SYS_FSL_I2C4_SPEED 100000
399   -#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
400   -#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
401   -#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
402   -#define I2C_MUX_CH_DEFAULT 0x8
403   -
404   -
405   -/*
406   - * RapidIO
407   - */
408   -#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
409   -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
410   -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
411   -#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
412   -#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
413   -#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
414   -/*
415   - * for slave u-boot IMAGE instored in master memory space,
416   - * PHYS must be aligned based on the SIZE
417   - */
418   -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
419   -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
420   -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
421   -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
422   -/*
423   - * for slave UCODE and ENV instored in master memory space,
424   - * PHYS must be aligned based on the SIZE
425   - */
426   -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
427   -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
428   -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
429   -
430   -/* slave core release by master*/
431   -#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
432   -#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
433   -
434   -/*
435   - * SRIO_PCIE_BOOT - SLAVE
436   - */
437   -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
438   -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
439   -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
440   - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
441   -#endif
442   -
443   -/*
444   - * eSPI - Enhanced SPI
445   - */
446   -#ifdef CONFIG_SPI_FLASH
447   -#define CONFIG_FSL_ESPI
448   -#define CONFIG_SPI_FLASH_SST
449   -#define CONFIG_SPI_FLASH_STMICRO
450   -#define CONFIG_SPI_FLASH_SPANSION
451   -#define CONFIG_CMD_SF
452   -#define CONFIG_SF_DEFAULT_SPEED 10000000
453   -#define CONFIG_SF_DEFAULT_MODE 0
454   -#endif
455   -
456   -/*
457   - * General PCI
458   - * Memory space is mapped 1-1, but I/O space must start from 0.
459   - */
460   -#define CONFIG_PCI /* Enable PCI/PCIE */
461   -#define CONFIG_PCIE1 /* PCIE controler 1 */
462   -#define CONFIG_PCIE2 /* PCIE controler 2 */
463   -#define CONFIG_PCIE3 /* PCIE controler 3 */
464   -#define CONFIG_PCIE4 /* PCIE controler 4 */
465   -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
466   -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
467   -/* controller 1, direct to uli, tgtid 3, Base address 20000 */
468   -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
469   -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
470   -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
471   -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
472   -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
473   -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
474   -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
475   -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
476   -
477   -/* controller 2, Slot 2, tgtid 2, Base address 201000 */
478   -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
479   -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
480   -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
481   -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
482   -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
483   -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
484   -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
485   -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
486   -
487   -/* controller 3, Slot 1, tgtid 1, Base address 202000 */
488   -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
489   -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
490   -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
491   -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
492   -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
493   -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
494   -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
495   -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
496   -
497   -/* controller 4, Base address 203000 */
498   -#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
499   -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
500   -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
501   -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
502   -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
503   -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
504   -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
505   -
506   -#ifdef CONFIG_PCI
507   -#define CONFIG_PCI_INDIRECT_BRIDGE
508   -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */
509   -#define CONFIG_NET_MULTI
510   -#define CONFIG_E1000
511   -#define CONFIG_PCI_PNP /* do pci plug-and-play */
512   -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
513   -#define CONFIG_DOS_PARTITION
514   -#endif
515   -
516   -/* Qman/Bman */
517   -#ifndef CONFIG_NOBQFMAN
518   -#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
519   -#define CONFIG_SYS_BMAN_NUM_PORTALS 18
520   -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
521   -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
522   -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
523   -#define CONFIG_SYS_QMAN_NUM_PORTALS 18
524   -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
525   -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
526   -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
527   -
528   -#define CONFIG_SYS_DPAA_FMAN
529   -#define CONFIG_SYS_DPAA_PME
530   -#define CONFIG_SYS_PMAN
531   -#define CONFIG_SYS_DPAA_DCE
532   -#define CONFIG_SYS_DPAA_RMAN /* RMan */
533   -#define CONFIG_SYS_INTERLAKEN
534   -
535   -/* Default address of microcode for the Linux Fman driver */
536   -#if defined(CONFIG_SPIFLASH)
537   -/*
538   - * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
539   - * env, so we got 0x110000.
540   - */
541   -#define CONFIG_SYS_QE_FW_IN_SPIFLASH
542   -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
543   -#elif defined(CONFIG_SDCARD)
544   -/*
545   - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
546   - * about 825KB (1650 blocks), Env is stored after the image, and the env size is
547   - * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
548   - */
549   -#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
550   -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680)
551   -#elif defined(CONFIG_NAND)
552   -#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
553   -#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
554   -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
555   -/*
556   - * Slave has no ucode locally, it can fetch this from remote. When implementing
557   - * in two corenet boards, slave's ucode could be stored in master's memory
558   - * space, the address can be mapped from slave TLB->slave LAW->
559   - * slave SRIO or PCIE outbound window->master inbound window->
560   - * master LAW->the ucode address in master's memory space.
561   - */
562   -#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
563   -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
564   -#else
565   -#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
566   -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
567   -#endif
568   -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
569   -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
570   -#endif /* CONFIG_NOBQFMAN */
571   -
572   -#ifdef CONFIG_SYS_DPAA_FMAN
573   -#define CONFIG_FMAN_ENET
574   -#define CONFIG_PHYLIB_10G
575   -#define CONFIG_PHY_VITESSE
576   -#define CONFIG_PHY_REALTEK
577   -#define CONFIG_PHY_TERANETICS
578   -#define RGMII_PHY1_ADDR 0x1
579   -#define RGMII_PHY2_ADDR 0x2
580   -#define FM1_10GEC1_PHY_ADDR 0x3
581   -#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
582   -#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
583   -#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
584   -#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
585   -#endif
586   -
587   -#ifdef CONFIG_FMAN_ENET
588   -#define CONFIG_MII /* MII PHY management */
589   -#define CONFIG_ETHPRIME "FM1@DTSEC3"
590   -#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
591   -#endif
592   -
593   -/*
594   - * SATA
595   - */
596   -#ifdef CONFIG_FSL_SATA_V2
597   -#define CONFIG_LIBATA
598   -#define CONFIG_FSL_SATA
599   -#define CONFIG_SYS_SATA_MAX_DEVICE 2
600   -#define CONFIG_SATA1
601   -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
602   -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
603   -#define CONFIG_SATA2
604   -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
605   -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
606   -#define CONFIG_LBA48
607   -#define CONFIG_CMD_SATA
608   -#define CONFIG_DOS_PARTITION
609   -#define CONFIG_CMD_EXT2
610   -#endif
611   -
612   -/*
613   - * USB
614   - */
615   -#ifdef CONFIG_USB_EHCI
616   -#define CONFIG_CMD_USB
617   -#define CONFIG_USB_STORAGE
618   -#define CONFIG_USB_EHCI_FSL
619   -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
620   -#define CONFIG_CMD_EXT2
621   -#define CONFIG_HAS_FSL_DR_USB
622   -#endif
623   -
624   -/*
625   - * SDHC
626   - */
627   -#ifdef CONFIG_MMC
628   -#define CONFIG_CMD_MMC
629   -#define CONFIG_FSL_ESDHC
630   -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
631   -#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
632   -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
633   -#define CONFIG_GENERIC_MMC
634   -#define CONFIG_CMD_EXT2
635   -#define CONFIG_CMD_FAT
636   -#define CONFIG_DOS_PARTITION
637   -#endif
638   -
639   -/*
640   - * Environment
641   - */
642   -#define CONFIG_LOADS_ECHO /* echo on for serial download */
643   -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
644   -
645   -/*
646   - * Command line configuration.
647   - */
648   -#include <config_cmd_default.h>
649   -
650   -#define CONFIG_CMD_DHCP
651   -#define CONFIG_CMD_ELF
652   -#define CONFIG_CMD_ERRATA
653   -#define CONFIG_CMD_GREPENV
654   -#define CONFIG_CMD_IRQ
655   -#define CONFIG_CMD_I2C
656   -#define CONFIG_CMD_MII
657   -#define CONFIG_CMD_PING
658   -#define CONFIG_CMD_SETEXPR
659   -#define CONFIG_CMD_REGINFO
660   -#define CONFIG_CMD_BDI
661   -
662   -#ifdef CONFIG_PCI
663   -#define CONFIG_CMD_PCI
664   -#define CONFIG_CMD_NET
665   -#endif
666   -
667   -/*
668   - * Miscellaneous configurable options
669   - */
670   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
671   -#define CONFIG_CMDLINE_EDITING /* Command-line editing */
672   -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
673   -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
674   -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
675   -#ifdef CONFIG_CMD_KGDB
676   -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
677   -#else
678   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
679   -#endif
680   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
681   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
682   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
683   -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/
684   -
685   -/*
686   - * For booting Linux, the board info and command line data
687   - * have to be in the first 64 MB of memory, since this is
688   - * the maximum mapped by the Linux kernel during initialization.
689   - */
690   -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
691   -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
692   -
693   -#ifdef CONFIG_CMD_KGDB
694   -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
695   -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
696   -#endif
697   -
698   -/*
699   - * Environment Configuration
700   - */
701   -#define CONFIG_ROOTPATH "/opt/nfsroot"
702   -#define CONFIG_BOOTFILE "uImage"
703   -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
704   -
705   -/* default location for tftp and bootm */
706   -#define CONFIG_LOADADDR 1000000
707   -#define CONFIG_BAUDRATE 115200
708   -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
709   -#define __USB_PHY_TYPE utmi
710   -
711   -#define CONFIG_EXTRA_ENV_SETTINGS \
712   - "hwconfig=fsl_ddr:" \
713   - "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
714   - "bank_intlv=auto;" \
715   - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
716   - "netdev=eth0\0" \
717   - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
718   - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
719   - "tftpflash=tftpboot $loadaddr $uboot && " \
720   - "protect off $ubootaddr +$filesize && " \
721   - "erase $ubootaddr +$filesize && " \
722   - "cp.b $loadaddr $ubootaddr $filesize && " \
723   - "protect on $ubootaddr +$filesize && " \
724   - "cmp.b $loadaddr $ubootaddr $filesize\0" \
725   - "consoledev=ttyS0\0" \
726   - "ramdiskaddr=2000000\0" \
727   - "ramdiskfile=t2080qds/ramdisk.uboot\0" \
728   - "fdtaddr=c00000\0" \
729   - "fdtfile=t2080qds/t2080qds.dtb\0" \
730   - "bdev=sda3\0" \
731   - "c=ffe\0"
732   -
733   -/*
734   - * For emulation this causes u-boot to jump to the start of the
735   - * proof point app code automatically
736   - */
737   -#define CONFIG_PROOF_POINTS \
738   - "setenv bootargs root=/dev/$bdev rw " \
739   - "console=$consoledev,$baudrate $othbootargs;" \
740   - "cpu 1 release 0x29000000 - - -;" \
741   - "cpu 2 release 0x29000000 - - -;" \
742   - "cpu 3 release 0x29000000 - - -;" \
743   - "cpu 4 release 0x29000000 - - -;" \
744   - "cpu 5 release 0x29000000 - - -;" \
745   - "cpu 6 release 0x29000000 - - -;" \
746   - "cpu 7 release 0x29000000 - - -;" \
747   - "go 0x29000000"
748   -
749   -#define CONFIG_HVBOOT \
750   - "setenv bootargs config-addr=0x60000000; " \
751   - "bootm 0x01000000 - 0x00f00000"
752   -
753   -#define CONFIG_ALU \
754   - "setenv bootargs root=/dev/$bdev rw " \
755   - "console=$consoledev,$baudrate $othbootargs;" \
756   - "cpu 1 release 0x01000000 - - -;" \
757   - "cpu 2 release 0x01000000 - - -;" \
758   - "cpu 3 release 0x01000000 - - -;" \
759   - "cpu 4 release 0x01000000 - - -;" \
760   - "cpu 5 release 0x01000000 - - -;" \
761   - "cpu 6 release 0x01000000 - - -;" \
762   - "cpu 7 release 0x01000000 - - -;" \
763   - "go 0x01000000"
764   -
765   -#define CONFIG_LINUX \
766   - "setenv bootargs root=/dev/ram rw " \
767   - "console=$consoledev,$baudrate $othbootargs;" \
768   - "setenv ramdiskaddr 0x02000000;" \
769   - "setenv fdtaddr 0x00c00000;" \
770   - "setenv loadaddr 0x1000000;" \
771   - "bootm $loadaddr $ramdiskaddr $fdtaddr"
772   -
773   -#define CONFIG_HDBOOT \
774   - "setenv bootargs root=/dev/$bdev rw " \
775   - "console=$consoledev,$baudrate $othbootargs;" \
776   - "tftp $loadaddr $bootfile;" \
777   - "tftp $fdtaddr $fdtfile;" \
778   - "bootm $loadaddr - $fdtaddr"
779   -
780   -#define CONFIG_NFSBOOTCOMMAND \
781   - "setenv bootargs root=/dev/nfs rw " \
782   - "nfsroot=$serverip:$rootpath " \
783   - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
784   - "console=$consoledev,$baudrate $othbootargs;" \
785   - "tftp $loadaddr $bootfile;" \
786   - "tftp $fdtaddr $fdtfile;" \
787   - "bootm $loadaddr - $fdtaddr"
788   -
789   -#define CONFIG_RAMBOOTCOMMAND \
790   - "setenv bootargs root=/dev/ram rw " \
791   - "console=$consoledev,$baudrate $othbootargs;" \
792   - "tftp $ramdiskaddr $ramdiskfile;" \
793   - "tftp $loadaddr $bootfile;" \
794   - "tftp $fdtaddr $fdtfile;" \
795   - "bootm $loadaddr $ramdiskaddr $fdtaddr"
796   -
797   -#define CONFIG_BOOTCOMMAND CONFIG_LINUX
798   -
799   -#ifdef CONFIG_SECURE_BOOT
800   -#include <asm/fsl_secure_boot.h>
801   -#undef CONFIG_CMD_USB
802   -#endif
803   -
804   -#endif /* __T2080QDS_H */
include/configs/T208xQDS.h
Diff comments   View file @ 254887a
  1 +/*
  2 + * Copyright 2011-2013 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +/*
  8 + * T2080/T2081 QDS board configuration file
  9 + */
  10 +
  11 +#ifndef __T208xQDS_H
  12 +#define __T208xQDS_H
  13 +
  14 +#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
  15 +#define CONFIG_MMC
  16 +#define CONFIG_SPI_FLASH
  17 +#define CONFIG_USB_EHCI
  18 +#if defined(CONFIG_PPC_T2080)
  19 +#define CONFIG_T2080QDS
  20 +#define CONFIG_FSL_SATA_V2
  21 +#define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
  22 +#define CONFIG_SRIO1 /* SRIO port 1 */
  23 +#define CONFIG_SRIO2 /* SRIO port 2 */
  24 +#elif defined(CONFIG_PPC_T2081)
  25 +#define CONFIG_T2081QDS
  26 +#endif
  27 +
  28 +/* High Level Configuration Options */
  29 +#define CONFIG_PHYS_64BIT
  30 +#define CONFIG_BOOKE
  31 +#define CONFIG_E500 /* BOOKE e500 family */
  32 +#define CONFIG_E500MC /* BOOKE e500mc family */
  33 +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  34 +#define CONFIG_MP /* support multiple processors */
  35 +#define CONFIG_ENABLE_36BIT_PHYS
  36 +
  37 +#ifdef CONFIG_PHYS_64BIT
  38 +#define CONFIG_ADDR_MAP 1
  39 +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  40 +#endif
  41 +
  42 +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  43 +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
  44 +#define CONFIG_FSL_IFC /* Enable IFC Support */
  45 +#define CONFIG_FSL_LAW /* Use common FSL init code */
  46 +#define CONFIG_ENV_OVERWRITE
  47 +
  48 +#ifdef CONFIG_RAMBOOT_PBL
  49 +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
  50 +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  51 +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t208xqds/t208x_pbi.cfg
  52 +#if defined(CONFIG_PPC_T2080)
  53 +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t208xqds/t2080_rcw.cfg
  54 +#elif defined(CONFIG_PPC_T2081)
  55 +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t208xqds/t2081_rcw.cfg
  56 +#endif
  57 +#endif
  58 +
  59 +#define CONFIG_SRIO_PCIE_BOOT_MASTER
  60 +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  61 +/* Set 1M boot space */
  62 +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  63 +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  64 + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  65 +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  66 +#define CONFIG_SYS_NO_FLASH
  67 +#endif
  68 +
  69 +#ifndef CONFIG_SYS_TEXT_BASE
  70 +#define CONFIG_SYS_TEXT_BASE 0xeff40000
  71 +#endif
  72 +
  73 +#ifndef CONFIG_RESET_VECTOR_ADDRESS
  74 +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  75 +#endif
  76 +
  77 +/*
  78 + * These can be toggled for performance analysis, otherwise use default.
  79 + */
  80 +#define CONFIG_SYS_CACHE_STASHING
  81 +#define CONFIG_BTB /* toggle branch predition */
  82 +#define CONFIG_DDR_ECC
  83 +#ifdef CONFIG_DDR_ECC
  84 +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  85 +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  86 +#endif
  87 +
  88 +#ifdef CONFIG_SYS_NO_FLASH
  89 +#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
  90 +#define CONFIG_ENV_IS_NOWHERE
  91 +#endif
  92 +#else
  93 +#define CONFIG_FLASH_CFI_DRIVER
  94 +#define CONFIG_SYS_FLASH_CFI
  95 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  96 +#endif
  97 +
  98 +#if defined(CONFIG_SPIFLASH)
  99 +#define CONFIG_SYS_EXTRA_ENV_RELOC
  100 +#define CONFIG_ENV_IS_IN_SPI_FLASH
  101 +#define CONFIG_ENV_SPI_BUS 0
  102 +#define CONFIG_ENV_SPI_CS 0
  103 +#define CONFIG_ENV_SPI_MAX_HZ 10000000
  104 +#define CONFIG_ENV_SPI_MODE 0
  105 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
  106 +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
  107 +#define CONFIG_ENV_SECT_SIZE 0x10000
  108 +#elif defined(CONFIG_SDCARD)
  109 +#define CONFIG_SYS_EXTRA_ENV_RELOC
  110 +#define CONFIG_ENV_IS_IN_MMC
  111 +#define CONFIG_SYS_MMC_ENV_DEV 0
  112 +#define CONFIG_ENV_SIZE 0x2000
  113 +#define CONFIG_ENV_OFFSET (512 * 1658)
  114 +#elif defined(CONFIG_NAND)
  115 +#define CONFIG_SYS_EXTRA_ENV_RELOC
  116 +#define CONFIG_ENV_IS_IN_NAND
  117 +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
  118 +#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
  119 +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  120 +#define CONFIG_ENV_IS_IN_REMOTE
  121 +#define CONFIG_ENV_ADDR 0xffe20000
  122 +#define CONFIG_ENV_SIZE 0x2000
  123 +#elif defined(CONFIG_ENV_IS_NOWHERE)
  124 +#define CONFIG_ENV_SIZE 0x2000
  125 +#else
  126 +#define CONFIG_ENV_IS_IN_FLASH
  127 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  128 +#define CONFIG_ENV_SIZE 0x2000
  129 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
  130 +#endif
  131 +
  132 +#ifndef __ASSEMBLY__
  133 +unsigned long get_board_sys_clk(void);
  134 +unsigned long get_board_ddr_clk(void);
  135 +#endif
  136 +
  137 +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
  138 +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
  139 +
  140 +/*
  141 + * Config the L3 Cache as L3 SRAM
  142 + */
  143 +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
  144 +
  145 +#define CONFIG_SYS_DCSRBAR 0xf0000000
  146 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  147 +
  148 +/* EEPROM */
  149 +#define CONFIG_ID_EEPROM
  150 +#define CONFIG_SYS_I2C_EEPROM_NXID
  151 +#define CONFIG_SYS_EEPROM_BUS_NUM 0
  152 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  153 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  154 +
  155 +/*
  156 + * DDR Setup
  157 + */
  158 +#define CONFIG_VERY_BIG_RAM
  159 +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  160 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  161 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1
  162 +#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  163 +#define CONFIG_DDR_SPD
  164 +#define CONFIG_SYS_FSL_DDR3
  165 +#undef CONFIG_FSL_DDR_INTERACTIVE
  166 +#define CONFIG_SYS_SPD_BUS_NUM 0
  167 +#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
  168 +#define SPD_EEPROM_ADDRESS1 0x51
  169 +#define SPD_EEPROM_ADDRESS2 0x52
  170 +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
  171 +#define CTRL_INTLV_PREFERED cacheline
  172 +
  173 +/*
  174 + * IFC Definitions
  175 + */
  176 +#define CONFIG_SYS_FLASH_BASE 0xe0000000
  177 +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  178 +#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
  179 +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  180 + + 0x8000000) | \
  181 + CSPR_PORT_SIZE_16 | \
  182 + CSPR_MSEL_NOR | \
  183 + CSPR_V)
  184 +#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
  185 +#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  186 + CSPR_PORT_SIZE_16 | \
  187 + CSPR_MSEL_NOR | \
  188 + CSPR_V)
  189 +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  190 +/* NOR Flash Timing Params */
  191 +#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
  192 +
  193 +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  194 + FTIM0_NOR_TEADC(0x5) | \
  195 + FTIM0_NOR_TEAHC(0x5))
  196 +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  197 + FTIM1_NOR_TRAD_NOR(0x1A) |\
  198 + FTIM1_NOR_TSEQRAD_NOR(0x13))
  199 +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  200 + FTIM2_NOR_TCH(0x4) | \
  201 + FTIM2_NOR_TWPH(0x0E) | \
  202 + FTIM2_NOR_TWP(0x1c))
  203 +#define CONFIG_SYS_NOR_FTIM3 0x0
  204 +
  205 +#define CONFIG_SYS_FLASH_QUIET_TEST
  206 +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  207 +
  208 +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  209 +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  210 +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  211 +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  212 +
  213 +#define CONFIG_SYS_FLASH_EMPTY_INFO
  214 +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
  215 + + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
  216 +
  217 +#define CONFIG_FSL_QIXIS /* use common QIXIS code */
  218 +#define QIXIS_BASE 0xffdf0000
  219 +#define QIXIS_LBMAP_SWITCH 6
  220 +#define QIXIS_LBMAP_MASK 0x0f
  221 +#define QIXIS_LBMAP_SHIFT 0
  222 +#define QIXIS_LBMAP_DFLTBANK 0x00
  223 +#define QIXIS_LBMAP_ALTBANK 0x04
  224 +#define QIXIS_RST_CTL_RESET 0x83
  225 +#define QIXIS_RST_FORCE_MEM 0x1
  226 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  227 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  228 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  229 +#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
  230 +
  231 +#define CONFIG_SYS_CSPR3_EXT (0xf)
  232 +#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
  233 + | CSPR_PORT_SIZE_8 \
  234 + | CSPR_MSEL_GPCM \
  235 + | CSPR_V)
  236 +#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
  237 +#define CONFIG_SYS_CSOR3 0x0
  238 +/* QIXIS Timing parameters for IFC CS3 */
  239 +#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  240 + FTIM0_GPCM_TEADC(0x0e) | \
  241 + FTIM0_GPCM_TEAHC(0x0e))
  242 +#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
  243 + FTIM1_GPCM_TRAD(0x3f))
  244 +#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  245 + FTIM2_GPCM_TCH(0x0) | \
  246 + FTIM2_GPCM_TWP(0x1f))
  247 +#define CONFIG_SYS_CS3_FTIM3 0x0
  248 +
  249 +/* NAND Flash on IFC */
  250 +#define CONFIG_NAND_FSL_IFC
  251 +#define CONFIG_SYS_NAND_BASE 0xff800000
  252 +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  253 +
  254 +#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  255 +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  256 + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  257 + | CSPR_MSEL_NAND /* MSEL = NAND */ \
  258 + | CSPR_V)
  259 +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  260 +
  261 +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  262 + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  263 + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  264 + | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
  265 + | CSOR_NAND_PGS_2K /* Page Size = 2K */\
  266 + | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
  267 + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  268 +
  269 +#define CONFIG_SYS_NAND_ONFI_DETECTION
  270 +
  271 +/* ONFI NAND Flash mode0 Timing Params */
  272 +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  273 + FTIM0_NAND_TWP(0x18) | \
  274 + FTIM0_NAND_TWCHT(0x07) | \
  275 + FTIM0_NAND_TWH(0x0a))
  276 +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  277 + FTIM1_NAND_TWBE(0x39) | \
  278 + FTIM1_NAND_TRR(0x0e) | \
  279 + FTIM1_NAND_TRP(0x18))
  280 +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  281 + FTIM2_NAND_TREH(0x0a) | \
  282 + FTIM2_NAND_TWHRE(0x1e))
  283 +#define CONFIG_SYS_NAND_FTIM3 0x0
  284 +
  285 +#define CONFIG_SYS_NAND_DDR_LAW 11
  286 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  287 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
  288 +#define CONFIG_MTD_NAND_VERIFY_WRITE
  289 +#define CONFIG_CMD_NAND
  290 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  291 +
  292 +#if defined(CONFIG_NAND)
  293 +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  294 +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  295 +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  296 +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  297 +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  298 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  299 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  300 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  301 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
  302 +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
  303 +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  304 +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  305 +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  306 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  307 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  308 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  309 +#else
  310 +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  311 +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  312 +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  313 +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  314 +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  315 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  316 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  317 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  318 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  319 +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  320 +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  321 +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  322 +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  323 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  324 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  325 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  326 +#endif
  327 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
  328 +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
  329 +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  330 +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  331 +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  332 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  333 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  334 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  335 +
  336 +#if defined(CONFIG_RAMBOOT_PBL)
  337 +#define CONFIG_SYS_RAMBOOT
  338 +#endif
  339 +
  340 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  341 +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
  342 +#define CONFIG_MISC_INIT_R
  343 +#define CONFIG_HWCONFIG
  344 +
  345 +/* define to use L1 as initial stack */
  346 +#define CONFIG_L1_INIT_RAM
  347 +#define CONFIG_SYS_INIT_RAM_LOCK
  348 +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  349 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  350 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
  351 +/* The assembler doesn't like typecast */
  352 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  353 + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  354 + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  355 +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  356 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  357 + GENERATED_GBL_DATA_SIZE)
  358 +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  359 +#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
  360 +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  361 +
  362 +/*
  363 + * Serial Port
  364 + */
  365 +#define CONFIG_CONS_INDEX 1
  366 +#define CONFIG_SYS_NS16550
  367 +#define CONFIG_SYS_NS16550_SERIAL
  368 +#define CONFIG_SYS_NS16550_REG_SIZE 1
  369 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  370 +#define CONFIG_SYS_BAUDRATE_TABLE \
  371 + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  372 +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  373 +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  374 +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  375 +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  376 +
  377 +/* Use the HUSH parser */
  378 +#define CONFIG_SYS_HUSH_PARSER
  379 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  380 +
  381 +/* pass open firmware flat tree */
  382 +#define CONFIG_OF_LIBFDT
  383 +#define CONFIG_OF_BOARD_SETUP
  384 +#define CONFIG_OF_STDOUT_VIA_ALIAS
  385 +
  386 +/* new uImage format support */
  387 +#define CONFIG_FIT
  388 +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
  389 +
  390 +/*
  391 + * I2C
  392 + */
  393 +#define CONFIG_SYS_I2C
  394 +#define CONFIG_SYS_I2C_FSL
  395 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  396 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  397 +#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
  398 +#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
  399 +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  400 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  401 +#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
  402 +#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
  403 +#define CONFIG_SYS_FSL_I2C_SPEED 100000
  404 +#define CONFIG_SYS_FSL_I2C2_SPEED 100000
  405 +#define CONFIG_SYS_FSL_I2C3_SPEED 100000
  406 +#define CONFIG_SYS_FSL_I2C4_SPEED 100000
  407 +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
  408 +#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
  409 +#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
  410 +#define I2C_MUX_CH_DEFAULT 0x8
  411 +
  412 +
  413 +/*
  414 + * RapidIO
  415 + */
  416 +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
  417 +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
  418 +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
  419 +#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
  420 +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
  421 +#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
  422 +/*
  423 + * for slave u-boot IMAGE instored in master memory space,
  424 + * PHYS must be aligned based on the SIZE
  425 + */
  426 +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
  427 +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
  428 +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
  429 +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
  430 +/*
  431 + * for slave UCODE and ENV instored in master memory space,
  432 + * PHYS must be aligned based on the SIZE
  433 + */
  434 +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
  435 +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
  436 +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
  437 +
  438 +/* slave core release by master*/
  439 +#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
  440 +#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
  441 +
  442 +/*
  443 + * SRIO_PCIE_BOOT - SLAVE
  444 + */
  445 +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  446 +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  447 +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  448 + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  449 +#endif
  450 +
  451 +/*
  452 + * eSPI - Enhanced SPI
  453 + */
  454 +#ifdef CONFIG_SPI_FLASH
  455 +#define CONFIG_FSL_ESPI
  456 +#define CONFIG_SPI_FLASH_SST
  457 +#define CONFIG_SPI_FLASH_STMICRO
  458 +#if defined(CONFIG_T2080QDS)
  459 +#define CONFIG_SPI_FLASH_SPANSION
  460 +#elif defined(CONFIG_T2081QDS)
  461 +#define CONFIG_SPI_FLASH_EON
  462 +#endif
  463 +
  464 +#define CONFIG_CMD_SF
  465 +#define CONFIG_SF_DEFAULT_SPEED 10000000
  466 +#define CONFIG_SF_DEFAULT_MODE 0
  467 +#endif
  468 +
  469 +/*
  470 + * General PCI
  471 + * Memory space is mapped 1-1, but I/O space must start from 0.
  472 + */
  473 +#define CONFIG_PCI /* Enable PCI/PCIE */
  474 +#define CONFIG_PCIE1 /* PCIE controler 1 */
  475 +#define CONFIG_PCIE2 /* PCIE controler 2 */
  476 +#define CONFIG_PCIE3 /* PCIE controler 3 */
  477 +#define CONFIG_PCIE4 /* PCIE controler 4 */
  478 +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  479 +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  480 +/* controller 1, direct to uli, tgtid 3, Base address 20000 */
  481 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  482 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  483 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  484 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  485 +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  486 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  487 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  488 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  489 +
  490 +/* controller 2, Slot 2, tgtid 2, Base address 201000 */
  491 +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  492 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  493 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  494 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
  495 +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  496 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  497 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  498 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  499 +
  500 +/* controller 3, Slot 1, tgtid 1, Base address 202000 */
  501 +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
  502 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  503 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
  504 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
  505 +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  506 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  507 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  508 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  509 +
  510 +/* controller 4, Base address 203000 */
  511 +#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
  512 +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
  513 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
  514 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
  515 +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
  516 +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  517 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
  518 +
  519 +#ifdef CONFIG_PCI
  520 +#define CONFIG_PCI_INDIRECT_BRIDGE
  521 +#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
  522 +#define CONFIG_NET_MULTI
  523 +#define CONFIG_E1000
  524 +#define CONFIG_PCI_PNP /* do pci plug-and-play */
  525 +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  526 +#define CONFIG_DOS_PARTITION
  527 +#endif
  528 +
  529 +/* Qman/Bman */
  530 +#ifndef CONFIG_NOBQFMAN
  531 +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
  532 +#define CONFIG_SYS_BMAN_NUM_PORTALS 18
  533 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  534 +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  535 +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  536 +#define CONFIG_SYS_QMAN_NUM_PORTALS 18
  537 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  538 +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  539 +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  540 +
  541 +#define CONFIG_SYS_DPAA_FMAN
  542 +#define CONFIG_SYS_DPAA_PME
  543 +#define CONFIG_SYS_PMAN
  544 +#define CONFIG_SYS_DPAA_DCE
  545 +#define CONFIG_SYS_DPAA_RMAN /* RMan */
  546 +#define CONFIG_SYS_INTERLAKEN
  547 +
  548 +/* Default address of microcode for the Linux Fman driver */
  549 +#if defined(CONFIG_SPIFLASH)
  550 +/*
  551 + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  552 + * env, so we got 0x110000.
  553 + */
  554 +#define CONFIG_SYS_QE_FW_IN_SPIFLASH
  555 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
  556 +#elif defined(CONFIG_SDCARD)
  557 +/*
  558 + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  559 + * about 825KB (1650 blocks), Env is stored after the image, and the env size is
  560 + * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
  561 + */
  562 +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
  563 +#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680)
  564 +#elif defined(CONFIG_NAND)
  565 +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
  566 +#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
  567 +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  568 +/*
  569 + * Slave has no ucode locally, it can fetch this from remote. When implementing
  570 + * in two corenet boards, slave's ucode could be stored in master's memory
  571 + * space, the address can be mapped from slave TLB->slave LAW->
  572 + * slave SRIO or PCIE outbound window->master inbound window->
  573 + * master LAW->the ucode address in master's memory space.
  574 + */
  575 +#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
  576 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
  577 +#else
  578 +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
  579 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
  580 +#endif
  581 +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  582 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  583 +#endif /* CONFIG_NOBQFMAN */
  584 +
  585 +#ifdef CONFIG_SYS_DPAA_FMAN
  586 +#define CONFIG_FMAN_ENET
  587 +#define CONFIG_PHYLIB_10G
  588 +#define CONFIG_PHY_VITESSE
  589 +#define CONFIG_PHY_REALTEK
  590 +#define CONFIG_PHY_TERANETICS
  591 +#define RGMII_PHY1_ADDR 0x1
  592 +#define RGMII_PHY2_ADDR 0x2
  593 +#define FM1_10GEC1_PHY_ADDR 0x3
  594 +#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  595 +#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  596 +#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  597 +#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  598 +#endif
  599 +
  600 +#ifdef CONFIG_FMAN_ENET
  601 +#define CONFIG_MII /* MII PHY management */
  602 +#define CONFIG_ETHPRIME "FM1@DTSEC3"
  603 +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
  604 +#endif
  605 +
  606 +/*
  607 + * SATA
  608 + */
  609 +#ifdef CONFIG_FSL_SATA_V2
  610 +#define CONFIG_LIBATA
  611 +#define CONFIG_FSL_SATA
  612 +#define CONFIG_SYS_SATA_MAX_DEVICE 2
  613 +#define CONFIG_SATA1
  614 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  615 +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  616 +#define CONFIG_SATA2
  617 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  618 +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  619 +#define CONFIG_LBA48
  620 +#define CONFIG_CMD_SATA
  621 +#define CONFIG_DOS_PARTITION
  622 +#define CONFIG_CMD_EXT2
  623 +#endif
  624 +
  625 +/*
  626 + * USB
  627 + */
  628 +#ifdef CONFIG_USB_EHCI
  629 +#define CONFIG_CMD_USB
  630 +#define CONFIG_USB_STORAGE
  631 +#define CONFIG_USB_EHCI_FSL
  632 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  633 +#define CONFIG_CMD_EXT2
  634 +#define CONFIG_HAS_FSL_DR_USB
  635 +#endif
  636 +
  637 +/*
  638 + * SDHC
  639 + */
  640 +#ifdef CONFIG_MMC
  641 +#define CONFIG_CMD_MMC
  642 +#define CONFIG_FSL_ESDHC
  643 +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  644 +#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
  645 +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  646 +#define CONFIG_GENERIC_MMC
  647 +#define CONFIG_CMD_EXT2
  648 +#define CONFIG_CMD_FAT
  649 +#define CONFIG_DOS_PARTITION
  650 +#endif
  651 +
  652 +/*
  653 + * Environment
  654 + */
  655 +#define CONFIG_LOADS_ECHO /* echo on for serial download */
  656 +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  657 +
  658 +/*
  659 + * Command line configuration.
  660 + */
  661 +#include <config_cmd_default.h>
  662 +
  663 +#define CONFIG_CMD_DHCP
  664 +#define CONFIG_CMD_ELF
  665 +#define CONFIG_CMD_ERRATA
  666 +#define CONFIG_CMD_GREPENV
  667 +#define CONFIG_CMD_IRQ
  668 +#define CONFIG_CMD_I2C
  669 +#define CONFIG_CMD_MII
  670 +#define CONFIG_CMD_PING
  671 +#define CONFIG_CMD_SETEXPR
  672 +#define CONFIG_CMD_REGINFO
  673 +#define CONFIG_CMD_BDI
  674 +
  675 +#ifdef CONFIG_PCI
  676 +#define CONFIG_CMD_PCI
  677 +#define CONFIG_CMD_NET
  678 +#endif
  679 +
  680 +/*
  681 + * Miscellaneous configurable options
  682 + */
  683 +#define CONFIG_SYS_LONGHELP /* undef to save memory */
  684 +#define CONFIG_CMDLINE_EDITING /* Command-line editing */
  685 +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
  686 +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  687 +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  688 +#ifdef CONFIG_CMD_KGDB
  689 +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  690 +#else
  691 +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  692 +#endif
  693 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
  694 +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  695 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
  696 +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/
  697 +
  698 +/*
  699 + * For booting Linux, the board info and command line data
  700 + * have to be in the first 64 MB of memory, since this is
  701 + * the maximum mapped by the Linux kernel during initialization.
  702 + */
  703 +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  704 +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  705 +
  706 +#ifdef CONFIG_CMD_KGDB
  707 +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  708 +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  709 +#endif
  710 +
  711 +/*
  712 + * Environment Configuration
  713 + */
  714 +#define CONFIG_ROOTPATH "/opt/nfsroot"
  715 +#define CONFIG_BOOTFILE "uImage"
  716 +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
  717 +
  718 +/* default location for tftp and bootm */
  719 +#define CONFIG_LOADADDR 1000000
  720 +#define CONFIG_BAUDRATE 115200
  721 +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
  722 +#define __USB_PHY_TYPE utmi
  723 +
  724 +#define CONFIG_EXTRA_ENV_SETTINGS \
  725 + "hwconfig=fsl_ddr:" \
  726 + "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
  727 + "bank_intlv=auto;" \
  728 + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  729 + "netdev=eth0\0" \
  730 + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  731 + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  732 + "tftpflash=tftpboot $loadaddr $uboot && " \
  733 + "protect off $ubootaddr +$filesize && " \
  734 + "erase $ubootaddr +$filesize && " \
  735 + "cp.b $loadaddr $ubootaddr $filesize && " \
  736 + "protect on $ubootaddr +$filesize && " \
  737 + "cmp.b $loadaddr $ubootaddr $filesize\0" \
  738 + "consoledev=ttyS0\0" \
  739 + "ramdiskaddr=2000000\0" \
  740 + "ramdiskfile=t2080qds/ramdisk.uboot\0" \
  741 + "fdtaddr=c00000\0" \
  742 + "fdtfile=t2080qds/t2080qds.dtb\0" \
  743 + "bdev=sda3\0" \
  744 + "c=ffe\0"
  745 +
  746 +/*
  747 + * For emulation this causes u-boot to jump to the start of the
  748 + * proof point app code automatically
  749 + */
  750 +#define CONFIG_PROOF_POINTS \
  751 + "setenv bootargs root=/dev/$bdev rw " \
  752 + "console=$consoledev,$baudrate $othbootargs;" \
  753 + "cpu 1 release 0x29000000 - - -;" \
  754 + "cpu 2 release 0x29000000 - - -;" \
  755 + "cpu 3 release 0x29000000 - - -;" \
  756 + "cpu 4 release 0x29000000 - - -;" \
  757 + "cpu 5 release 0x29000000 - - -;" \
  758 + "cpu 6 release 0x29000000 - - -;" \
  759 + "cpu 7 release 0x29000000 - - -;" \
  760 + "go 0x29000000"
  761 +
  762 +#define CONFIG_HVBOOT \
  763 + "setenv bootargs config-addr=0x60000000; " \
  764 + "bootm 0x01000000 - 0x00f00000"
  765 +
  766 +#define CONFIG_ALU \
  767 + "setenv bootargs root=/dev/$bdev rw " \
  768 + "console=$consoledev,$baudrate $othbootargs;" \
  769 + "cpu 1 release 0x01000000 - - -;" \
  770 + "cpu 2 release 0x01000000 - - -;" \
  771 + "cpu 3 release 0x01000000 - - -;" \
  772 + "cpu 4 release 0x01000000 - - -;" \
  773 + "cpu 5 release 0x01000000 - - -;" \
  774 + "cpu 6 release 0x01000000 - - -;" \
  775 + "cpu 7 release 0x01000000 - - -;" \
  776 + "go 0x01000000"
  777 +
  778 +#define CONFIG_LINUX \
  779 + "setenv bootargs root=/dev/ram rw " \
  780 + "console=$consoledev,$baudrate $othbootargs;" \
  781 + "setenv ramdiskaddr 0x02000000;" \
  782 + "setenv fdtaddr 0x00c00000;" \
  783 + "setenv loadaddr 0x1000000;" \
  784 + "bootm $loadaddr $ramdiskaddr $fdtaddr"
  785 +
  786 +#define CONFIG_HDBOOT \
  787 + "setenv bootargs root=/dev/$bdev rw " \
  788 + "console=$consoledev,$baudrate $othbootargs;" \
  789 + "tftp $loadaddr $bootfile;" \
  790 + "tftp $fdtaddr $fdtfile;" \
  791 + "bootm $loadaddr - $fdtaddr"
  792 +
  793 +#define CONFIG_NFSBOOTCOMMAND \
  794 + "setenv bootargs root=/dev/nfs rw " \
  795 + "nfsroot=$serverip:$rootpath " \
  796 + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  797 + "console=$consoledev,$baudrate $othbootargs;" \
  798 + "tftp $loadaddr $bootfile;" \
  799 + "tftp $fdtaddr $fdtfile;" \
  800 + "bootm $loadaddr - $fdtaddr"
  801 +
  802 +#define CONFIG_RAMBOOTCOMMAND \
  803 + "setenv bootargs root=/dev/ram rw " \
  804 + "console=$consoledev,$baudrate $othbootargs;" \
  805 + "tftp $ramdiskaddr $ramdiskfile;" \
  806 + "tftp $loadaddr $bootfile;" \
  807 + "tftp $fdtaddr $fdtfile;" \
  808 + "bootm $loadaddr $ramdiskaddr $fdtaddr"
  809 +
  810 +#define CONFIG_BOOTCOMMAND CONFIG_LINUX
  811 +
  812 +#ifdef CONFIG_SECURE_BOOT
  813 +#include <asm/fsl_secure_boot.h>
  814 +#undef CONFIG_CMD_USB
  815 +#endif
  816 +
  817 +#endif /* __T208xQDS_H */