Eric Lee / smarc-uboot

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Commit 254d68b6011c33af189d006243920c296592fca7

Authored by Masahiro Yamada
Committed by Tom Rini
1 parent b97241b312
Exists in v2017.01-smarct4x and in 48 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

kbuild: move asm-offsets.c from SoC directory to arch/$(ARCH)/lib 

U-Boot has supported two kinds of asm-offsets.h.

One is generic for all architectures and its source is located at
./lib/asm-offsets.c.

The other is SoC specific and its source is under SoC directory.
The problem here is that only boards with SoC directory can use
the asm-offsets infrastructure.
Putting asm-offsets.c right under CPU directory does not work.

Now a new demand is coming. PowerPC folks want to use asm-offsets.
But no PowerPC boards have SoC directory.

It seems inconsistent that some boards add asm-offsets.c to SoC
directoreis and some to CPU directories.
It looks more reasonable to put asm-offsets.c under arch/$(ARCH)/lib.

This commit merges asm-offsets.c under SoC directories into
arch/$(ARCH)/lib/asm-offsets.c.

By the way, I doubt the necessity of some entries in asm-offsets.c.
I am leaving refactoring to the board maintainers.
Please check "TODO" in the comment blocks in
arch/{arm,nds32}/lib/asm-offsets.c.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Yuantian Tang <Yuantian.Tang@freescale.com>

Showing 12 changed files with 356 additions and 434 deletions Side-by-side Diff

... ... @@ -42,13 +42,13 @@
42 42 # 2) Generate asm-offsets.h
43 43 #
44 44  
45   -ifneq ($(wildcard $(srctree)/$(CPUDIR)/$(SOC)/asm-offsets.c),)
  45 +ifneq ($(wildcard $(srctree)/arch/$(ARCH)/lib/asm-offsets.c),)
46 46 offsets-file := include/generated/asm-offsets.h
47 47 endif
48 48  
49 49 always += $(offsets-file)
50 50 targets += $(offsets-file)
51   -targets += $(CPUDIR)/$(SOC)/asm-offsets.s
  51 +targets += arch/$(ARCH)/lib/asm-offsets.s
52 52  
53 53  
54 54 # Default sed regexp - multiline due to syntax constraints
55 55  
... ... @@ -79,10 +79,10 @@
79 79 endef
80 80  
81 81 # We use internal kbuild rules to avoid the "is up to date" message from make
82   -$(CPUDIR)/$(SOC)/asm-offsets.s: $(CPUDIR)/$(SOC)/asm-offsets.c FORCE
  82 +arch/$(ARCH)/lib/asm-offsets.s: arch/$(ARCH)/lib/asm-offsets.c FORCE
83 83 $(Q)mkdir -p $(dir $@)
84 84 $(call if_changed_dep,cc_s_c)
85 85  
86   -$(obj)/$(offsets-file): $(CPUDIR)/$(SOC)/asm-offsets.s
  86 +$(obj)/$(offsets-file): arch/$(ARCH)/lib/asm-offsets.s Kbuild
87 87 $(call cmd,offsets)
arch/arm/cpu/arm1136/mx35/asm-offsets.c
View file @ 254d68b
1   -/*
2   - * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
3   - *
4   - * This program is used to generate definitions needed by
5   - * assembly language modules.
6   - *
7   - * We use the technique used in the OSF Mach kernel code:
8   - * generate asm statements containing #defines,
9   - * compile this file to assembler, and then extract the
10   - * #defines from the assembly-language output.
11   - *
12   - * SPDX-License-Identifier: GPL-2.0+
13   - */
14   -
15   -#include <common.h>
16   -#include <asm/arch/imx-regs.h>
17   -
18   -#include <linux/kbuild.h>
19   -
20   -int main(void)
21   -{
22   - /* Round up to make sure size gives nice stack alignment */
23   - DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr));
24   - DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0));
25   - DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1));
26   - DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2));
27   - DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3));
28   - DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4));
29   - DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr));
30   - DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl));
31   - DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl));
32   - DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr));
33   - DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr));
34   - DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0));
35   - DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1));
36   - DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2));
37   - DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3));
38   -
39   - /* Multi-Layer AHB Crossbar Switch */
40   - DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
41   - DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
42   - DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
43   - DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
44   - DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
45   - DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
46   - DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
47   - DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
48   - DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
49   - DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
50   - DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
51   - DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
52   - DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
53   - DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
54   - DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
55   - DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5));
56   -
57   - /* AHB <-> IP-Bus Interface */
58   - DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
59   - DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
60   - DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7));
61   - DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15));
62   - DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23));
63   - DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31));
64   - DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7));
65   - DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15));
66   - DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23));
67   - DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31));
68   - DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39));
69   -
70   - return 0;
71   -}
arch/arm/cpu/arm926ejs/mb86r0x/asm-offsets.c
View file @ 254d68b
1   -/*
2   - * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
3   - *
4   - * This program is used to generate definitions needed by
5   - * assembly language modules.
6   - *
7   - * We use the technique used in the OSF Mach kernel code:
8   - * generate asm statements containing #defines,
9   - * compile this file to assembler, and then extract the
10   - * #defines from the assembly-language output.
11   - *
12   - * SPDX-License-Identifier: GPL-2.0+
13   - */
14   -
15   -#include <common.h>
16   -#include <asm/arch/mb86r0x.h>
17   -
18   -#include <linux/kbuild.h>
19   -
20   -int main(void)
21   -{
22   - /* ddr2 controller */
23   - DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric));
24   - DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1));
25   - DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2));
26   - DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca));
27   - DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm));
28   - DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1));
29   - DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2));
30   - DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr));
31   - DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf));
32   - DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr));
33   - DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims));
34   - DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros));
35   - DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1));
36   - DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba));
37   - DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs));
38   -
39   - /* clock reset generator */
40   - DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr));
41   - DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha));
42   - DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa));
43   - DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb));
44   - DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb));
45   - DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram));
46   -
47   - /* chip control module */
48   - DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc));
49   -
50   - /* external bus interface */
51   - DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0]));
52   - DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2]));
53   - DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4]));
54   - DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0]));
55   - DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2]));
56   - DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4]));
57   - DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0]));
58   - DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2]));
59   - DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4]));
60   -
61   - return 0;
62   -}
arch/arm/cpu/arm926ejs/mx25/asm-offsets.c
View file @ 254d68b
1   -/*
2   - * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
3   - *
4   - * This program is used to generate definitions needed by
5   - * assembly language modules.
6   - *
7   - * We use the technique used in the OSF Mach kernel code:
8   - * generate asm statements containing #defines,
9   - * compile this file to assembler, and then extract the
10   - * #defines from the assembly-language output.
11   - *
12   - * SPDX-License-Identifier: GPL-2.0+
13   - */
14   -
15   -#include <common.h>
16   -#include <asm/arch/imx-regs.h>
17   -
18   -#include <linux/kbuild.h>
19   -
20   -int main(void)
21   -{
22   - /* Clock Control Module */
23   - DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl));
24   - DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0));
25   - DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1));
26   - DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2));
27   - DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2]));
28   - DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr));
29   -
30   - /* Enhanced SDRAM Controller */
31   - DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0));
32   - DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0));
33   - DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc));
34   -
35   - /* Multi-Layer AHB Crossbar Switch */
36   - DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
37   - DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
38   - DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
39   - DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
40   - DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
41   - DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
42   - DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
43   - DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
44   - DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
45   - DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
46   - DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
47   - DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
48   - DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
49   - DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
50   - DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
51   -
52   - /* AHB <-> IP-Bus Interface */
53   - DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
54   - DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
55   -
56   - return 0;
57   -}
arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
View file @ 254d68b
1   -/*
2   - * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
3   - *
4   - * This program is used to generate definitions needed by
5   - * assembly language modules.
6   - *
7   - * We use the technique used in the OSF Mach kernel code:
8   - * generate asm statements containing #defines,
9   - * compile this file to assembler, and then extract the
10   - * #defines from the assembly-language output.
11   - *
12   - * SPDX-License-Identifier: GPL-2.0+
13   - */
14   -
15   -#include <common.h>
16   -#include <asm/arch/imx-regs.h>
17   -
18   -#include <linux/kbuild.h>
19   -
20   -int main(void)
21   -{
22   - DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0));
23   - DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1));
24   - DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0));
25   - DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1));
26   -
27   - DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr));
28   - DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0));
29   - DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0));
30   - DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0));
31   - DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1));
32   - DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0));
33   - DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1));
34   -
35   - DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0));
36   - DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0));
37   - DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1));
38   - DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
39   - DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
40   -
41   - DEFINE(GPCR, IMX_SYSTEM_CTL_BASE +
42   - offsetof(struct system_control_regs, gpcr));
43   - DEFINE(FMCR, IMX_SYSTEM_CTL_BASE +
44   - offsetof(struct system_control_regs, fmcr));
45   -
46   - return 0;
47   -}
arch/arm/cpu/armv7/mx5/asm-offsets.c
View file @ 254d68b
1   -/*
2   - * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
3   - *
4   - * This program is used to generate definitions needed by
5   - * assembly language modules.
6   - *
7   - * We use the technique used in the OSF Mach kernel code:
8   - * generate asm statements containing #defines,
9   - * compile this file to assembler, and then extract the
10   - * #defines from the assembly-language output.
11   - *
12   - * SPDX-License-Identifier: GPL-2.0+
13   - */
14   -
15   -#include <common.h>
16   -#include <asm/arch/imx-regs.h>
17   -
18   -#include <linux/kbuild.h>
19   -
20   -int main(void)
21   -{
22   -
23   - /* Round up to make sure size gives nice stack alignment */
24   - DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr));
25   - DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr));
26   - DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr));
27   - DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr));
28   - DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr));
29   - DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr));
30   - DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr));
31   - DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1));
32   - DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2));
33   - DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1));
34   - DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr));
35   - DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr));
36   - DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr));
37   - DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr));
38   - DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2));
39   - DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3));
40   - DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4));
41   - DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr));
42   - DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr));
43   - DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr));
44   - DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor));
45   - DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr));
46   - DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr));
47   - DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr));
48   - DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr));
49   - DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr));
50   - DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0));
51   - DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1));
52   - DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2));
53   - DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3));
54   - DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4));
55   - DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5));
56   - DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6));
57   - DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor));
58   -#if defined(CONFIG_MX53)
59   - DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7));
60   -#endif
61   -
62   - /* DPLL */
63   - DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl));
64   - DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config));
65   - DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op));
66   - DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd));
67   - DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn));
68   - DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op));
69   - DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd));
70   - DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn));
71   -
72   - return 0;
73   -}
arch/arm/lib/asm-offsets.c
Diff comments   View file @ 254d68b
  1 +/*
  2 + * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
  3 + *
  4 + * This program is used to generate definitions needed by
  5 + * assembly language modules.
  6 + *
  7 + * We use the technique used in the OSF Mach kernel code:
  8 + * generate asm statements containing #defines,
  9 + * compile this file to assembler, and then extract the
  10 + * #defines from the assembly-language output.
  11 + *
  12 + * SPDX-License-Identifier: GPL-2.0+
  13 + */
  14 +
  15 +#include <common.h>
  16 +#include <linux/kbuild.h>
  17 +
  18 +#if defined(CONFIG_MB86R0x)
  19 +#include <asm/arch/mb86r0x.h>
  20 +#endif
  21 +#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \
  22 + || defined(CONFIG_MX51) || defined(CONFIG_MX53)
  23 +#include <asm/arch/imx-regs.h>
  24 +#endif
  25 +
  26 +int main(void)
  27 +{
  28 + /*
  29 + * TODO : Check if each entry in this file is really necessary.
  30 + * - struct mb86r0x_ddr2
  31 + * - struct mb86r0x_memc
  32 + * - struct esdramc_regs
  33 + * - struct max_regs
  34 + * - struct aips_regs
  35 + * - struct aipi_regs
  36 + * - struct clkctl
  37 + * - struct dpll
  38 + * are used only for generating asm-offsets.h.
  39 + * It means their offset addresses are referenced only from assembly
  40 + * code. Is it better to define the macros directly in headers?
  41 + */
  42 +
  43 +#if defined(CONFIG_MB86R0x)
  44 + /* ddr2 controller */
  45 + DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric));
  46 + DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1));
  47 + DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2));
  48 + DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca));
  49 + DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm));
  50 + DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1));
  51 + DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2));
  52 + DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr));
  53 + DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf));
  54 + DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr));
  55 + DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims));
  56 + DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros));
  57 + DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1));
  58 + DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba));
  59 + DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs));
  60 +
  61 + /* clock reset generator */
  62 + DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr));
  63 + DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha));
  64 + DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa));
  65 + DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb));
  66 + DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb));
  67 + DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram));
  68 +
  69 + /* chip control module */
  70 + DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc));
  71 +
  72 + /* external bus interface */
  73 + DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0]));
  74 + DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2]));
  75 + DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4]));
  76 + DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0]));
  77 + DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2]));
  78 + DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4]));
  79 + DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0]));
  80 + DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2]));
  81 + DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4]));
  82 +#endif
  83 +
  84 +#if defined(CONFIG_MX25)
  85 + /* Clock Control Module */
  86 + DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl));
  87 + DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0));
  88 + DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1));
  89 + DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2));
  90 + DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2]));
  91 + DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr));
  92 +
  93 + /* Enhanced SDRAM Controller */
  94 + DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0));
  95 + DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0));
  96 + DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc));
  97 +
  98 + /* Multi-Layer AHB Crossbar Switch */
  99 + DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
  100 + DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
  101 + DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
  102 + DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
  103 + DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
  104 + DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
  105 + DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
  106 + DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
  107 + DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
  108 + DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
  109 + DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
  110 + DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
  111 + DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
  112 + DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
  113 + DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
  114 +
  115 + /* AHB <-> IP-Bus Interface */
  116 + DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
  117 + DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
  118 +#endif
  119 +
  120 +#if defined(CONFIG_MX27)
  121 + DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0));
  122 + DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1));
  123 + DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0));
  124 + DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1));
  125 +
  126 + DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr));
  127 + DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0));
  128 + DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0));
  129 + DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0));
  130 + DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1));
  131 + DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0));
  132 + DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1));
  133 +
  134 + DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0));
  135 + DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0));
  136 + DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1));
  137 + DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
  138 + DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
  139 +
  140 + DEFINE(GPCR, IMX_SYSTEM_CTL_BASE +
  141 + offsetof(struct system_control_regs, gpcr));
  142 + DEFINE(FMCR, IMX_SYSTEM_CTL_BASE +
  143 + offsetof(struct system_control_regs, fmcr));
  144 +#endif
  145 +
  146 +#if defined(CONFIG_MX35)
  147 + /* Round up to make sure size gives nice stack alignment */
  148 + DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr));
  149 + DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0));
  150 + DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1));
  151 + DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2));
  152 + DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3));
  153 + DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4));
  154 + DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr));
  155 + DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl));
  156 + DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl));
  157 + DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr));
  158 + DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr));
  159 + DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0));
  160 + DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1));
  161 + DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2));
  162 + DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3));
  163 +
  164 + /* Multi-Layer AHB Crossbar Switch */
  165 + DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
  166 + DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
  167 + DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
  168 + DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
  169 + DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
  170 + DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
  171 + DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
  172 + DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
  173 + DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
  174 + DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
  175 + DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
  176 + DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
  177 + DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
  178 + DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
  179 + DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
  180 + DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5));
  181 +
  182 + /* AHB <-> IP-Bus Interface */
  183 + DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
  184 + DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
  185 + DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7));
  186 + DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15));
  187 + DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23));
  188 + DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31));
  189 + DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7));
  190 + DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15));
  191 + DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23));
  192 + DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31));
  193 + DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39));
  194 +#endif
  195 +
  196 +#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
  197 + /* Round up to make sure size gives nice stack alignment */
  198 + DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr));
  199 + DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr));
  200 + DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr));
  201 + DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr));
  202 + DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr));
  203 + DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr));
  204 + DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr));
  205 + DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1));
  206 + DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2));
  207 + DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1));
  208 + DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr));
  209 + DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr));
  210 + DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr));
  211 + DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr));
  212 + DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2));
  213 + DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3));
  214 + DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4));
  215 + DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr));
  216 + DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr));
  217 + DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr));
  218 + DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor));
  219 + DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr));
  220 + DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr));
  221 + DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr));
  222 + DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr));
  223 + DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr));
  224 + DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0));
  225 + DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1));
  226 + DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2));
  227 + DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3));
  228 + DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4));
  229 + DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5));
  230 + DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6));
  231 + DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor));
  232 +#if defined(CONFIG_MX53)
  233 + DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7));
  234 +#endif
  235 +
  236 + /* DPLL */
  237 + DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl));
  238 + DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config));
  239 + DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op));
  240 + DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd));
  241 + DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn));
  242 + DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op));
  243 + DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd));
  244 + DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn));
  245 +#endif
  246 +
  247 + return 0;
  248 +}
arch/nds32/cpu/n1213/ag101/asm-offsets.c
View file @ 254d68b
1   -/*
2   - * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
3   - *
4   - * Generate definitions needed by assembly language modules.
5   - * This code generates raw asm output which is post-processed to extract
6   - * and format the required data.
7   - *
8   - * This program is free software; you can redistribute it and/or modify
9   - * it under the terms of the GNU General Public License version 2 as
10   - * published by the Free Software Foundation.
11   - */
12   -#include <common.h>
13   -
14   -#include <linux/kbuild.h>
15   -
16   -int main(void)
17   -{
18   -#ifdef CONFIG_FTSMC020
19   - OFFSET(FTSMC020_BANK0_CR, ftsmc020, bank[0].cr);
20   - OFFSET(FTSMC020_BANK0_TPR, ftsmc020, bank[0].tpr);
21   -#endif
22   - BLANK();
23   -#ifdef CONFIG_FTAHBC020S
24   - OFFSET(FTAHBC020S_SLAVE_BSR_4, ftahbc02s, s_bsr[4]);
25   - OFFSET(FTAHBC020S_SLAVE_BSR_6, ftahbc02s, s_bsr[6]);
26   - OFFSET(FTAHBC020S_CR, ftahbc02s, cr);
27   -#endif
28   - BLANK();
29   -#ifdef CONFIG_FTPMU010
30   - OFFSET(FTPMU010_PDLLCR0, ftpmu010, PDLLCR0);
31   -#endif
32   - BLANK();
33   -#ifdef CONFIG_FTSDMC021
34   - OFFSET(FTSDMC021_TP1, ftsdmc021, tp1);
35   - OFFSET(FTSDMC021_TP2, ftsdmc021, tp2);
36   - OFFSET(FTSDMC021_CR1, ftsdmc021, cr1);
37   - OFFSET(FTSDMC021_CR2, ftsdmc021, cr2);
38   - OFFSET(FTSDMC021_BANK0_BSR, ftsdmc021, bank0_bsr);
39   - OFFSET(FTSDMC021_BANK1_BSR, ftsdmc021, bank1_bsr);
40   - OFFSET(FTSDMC021_BANK2_BSR, ftsdmc021, bank2_bsr);
41   - OFFSET(FTSDMC021_BANK3_BSR, ftsdmc021, bank3_bsr);
42   -#endif
43   - return 0;
44   -}
arch/nds32/cpu/n1213/ag102/asm-offsets.c
View file @ 254d68b
1   -/*
2   - * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
3   - *
4   - * Generate definitions needed by assembly language modules.
5   - * This code generates raw asm output which is post-processed to extract
6   - * and format the required data.
7   - *
8   - * This program is free software; you can redistribute it and/or modify
9   - * it under the terms of the GNU General Public License version 2 as
10   - * published by the Free Software Foundation.
11   - */
12   -#include <common.h>
13   -
14   -#include <linux/kbuild.h>
15   -
16   -int main(void)
17   -{
18   -#ifdef CONFIG_FTSMC020
19   - OFFSET(FTSMC020_BANK0_CR, ftsmc020, bank[0].cr);
20   - OFFSET(FTSMC020_BANK0_TPR, ftsmc020, bank[0].tpr);
21   -#endif
22   - BLANK();
23   -#ifdef CONFIG_FTAHBC020S
24   - OFFSET(FTAHBC020S_SLAVE_BSR_6, ftahbc02s, s_bsr[6]);
25   - OFFSET(FTAHBC020S_CR, ftahbc02s, cr);
26   -#endif
27   - BLANK();
28   -#ifdef CONFIG_ANDES_PCU
29   - OFFSET(ANDES_PCU_PCS4, andes_pcu, pcs4.parm); /* 0x104 */
30   -#endif
31   - BLANK();
32   -#ifdef CONFIG_DWCDDR21MCTL
33   - OFFSET(DWCDDR21MCTL_CCR, dwcddr21mctl, ccr); /* 0x04 */
34   - OFFSET(DWCDDR21MCTL_DCR, dwcddr21mctl, dcr); /* 0x04 */
35   - OFFSET(DWCDDR21MCTL_IOCR, dwcddr21mctl, iocr); /* 0x08 */
36   - OFFSET(DWCDDR21MCTL_CSR, dwcddr21mctl, csr); /* 0x0c */
37   - OFFSET(DWCDDR21MCTL_DRR, dwcddr21mctl, drr); /* 0x10 */
38   - OFFSET(DWCDDR21MCTL_DLLCR0, dwcddr21mctl, dllcr[0]); /* 0x24 */
39   - OFFSET(DWCDDR21MCTL_DLLCR1, dwcddr21mctl, dllcr[1]); /* 0x28 */
40   - OFFSET(DWCDDR21MCTL_DLLCR2, dwcddr21mctl, dllcr[2]); /* 0x2c */
41   - OFFSET(DWCDDR21MCTL_DLLCR3, dwcddr21mctl, dllcr[3]); /* 0x30 */
42   - OFFSET(DWCDDR21MCTL_DLLCR4, dwcddr21mctl, dllcr[4]); /* 0x34 */
43   - OFFSET(DWCDDR21MCTL_DLLCR5, dwcddr21mctl, dllcr[5]); /* 0x38 */
44   - OFFSET(DWCDDR21MCTL_DLLCR6, dwcddr21mctl, dllcr[6]); /* 0x3c */
45   - OFFSET(DWCDDR21MCTL_DLLCR7, dwcddr21mctl, dllcr[7]); /* 0x40 */
46   - OFFSET(DWCDDR21MCTL_DLLCR8, dwcddr21mctl, dllcr[8]); /* 0x44 */
47   - OFFSET(DWCDDR21MCTL_DLLCR9, dwcddr21mctl, dllcr[9]); /* 0x48 */
48   - OFFSET(DWCDDR21MCTL_RSLR0, dwcddr21mctl, rslr[0]); /* 0x4c */
49   - OFFSET(DWCDDR21MCTL_RDGR0, dwcddr21mctl, rdgr[0]); /* 0x5c */
50   - OFFSET(DWCDDR21MCTL_DTAR, dwcddr21mctl, dtar); /* 0xa4 */
51   - OFFSET(DWCDDR21MCTL_MR, dwcddr21mctl, mr); /* 0x1f0 */
52   -#endif
53   - return 0;
54   -}
arch/nds32/lib/asm-offsets.c
Diff comments   View file @ 254d68b
  1 +/*
  2 + * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
  3 + *
  4 + * Generate definitions needed by assembly language modules.
  5 + * This code generates raw asm output which is post-processed to extract
  6 + * and format the required data.
  7 + *
  8 + * This program is free software; you can redistribute it and/or modify
  9 + * it under the terms of the GNU General Public License version 2 as
  10 + * published by the Free Software Foundation.
  11 + */
  12 +#include <common.h>
  13 +
  14 +#include <linux/kbuild.h>
  15 +
  16 +int main(void)
  17 +{
  18 + /*
  19 + * TODO : Check if each entry in this file is really necessary.
  20 + * - struct ftahbc02s
  21 + * - struct ftsdmc021
  22 + * - struct andes_pcu
  23 + * - struct dwcddr21mctl
  24 + * are used only for generating asm-offsets.h.
  25 + * It means their offset addresses are referenced only from assembly
  26 + * code. Is it better to define the macros directly in headers?
  27 + */
  28 +
  29 +#ifdef CONFIG_FTSMC020
  30 + OFFSET(FTSMC020_BANK0_CR, ftsmc020, bank[0].cr);
  31 + OFFSET(FTSMC020_BANK0_TPR, ftsmc020, bank[0].tpr);
  32 +#endif
  33 + BLANK();
  34 +#ifdef CONFIG_FTAHBC020S
  35 + OFFSET(FTAHBC020S_SLAVE_BSR_4, ftahbc02s, s_bsr[4]);
  36 + OFFSET(FTAHBC020S_SLAVE_BSR_6, ftahbc02s, s_bsr[6]);
  37 + OFFSET(FTAHBC020S_CR, ftahbc02s, cr);
  38 +#endif
  39 + BLANK();
  40 +#ifdef CONFIG_FTPMU010
  41 + OFFSET(FTPMU010_PDLLCR0, ftpmu010, PDLLCR0);
  42 +#endif
  43 + BLANK();
  44 +#ifdef CONFIG_FTSDMC021
  45 + OFFSET(FTSDMC021_TP1, ftsdmc021, tp1);
  46 + OFFSET(FTSDMC021_TP2, ftsdmc021, tp2);
  47 + OFFSET(FTSDMC021_CR1, ftsdmc021, cr1);
  48 + OFFSET(FTSDMC021_CR2, ftsdmc021, cr2);
  49 + OFFSET(FTSDMC021_BANK0_BSR, ftsdmc021, bank0_bsr);
  50 + OFFSET(FTSDMC021_BANK1_BSR, ftsdmc021, bank1_bsr);
  51 + OFFSET(FTSDMC021_BANK2_BSR, ftsdmc021, bank2_bsr);
  52 + OFFSET(FTSDMC021_BANK3_BSR, ftsdmc021, bank3_bsr);
  53 +#endif
  54 + BLANK();
  55 +#ifdef CONFIG_ANDES_PCU
  56 + OFFSET(ANDES_PCU_PCS4, andes_pcu, pcs4.parm); /* 0x104 */
  57 +#endif
  58 + BLANK();
  59 +#ifdef CONFIG_DWCDDR21MCTL
  60 + OFFSET(DWCDDR21MCTL_CCR, dwcddr21mctl, ccr); /* 0x04 */
  61 + OFFSET(DWCDDR21MCTL_DCR, dwcddr21mctl, dcr); /* 0x04 */
  62 + OFFSET(DWCDDR21MCTL_IOCR, dwcddr21mctl, iocr); /* 0x08 */
  63 + OFFSET(DWCDDR21MCTL_CSR, dwcddr21mctl, csr); /* 0x0c */
  64 + OFFSET(DWCDDR21MCTL_DRR, dwcddr21mctl, drr); /* 0x10 */
  65 + OFFSET(DWCDDR21MCTL_DLLCR0, dwcddr21mctl, dllcr[0]); /* 0x24 */
  66 + OFFSET(DWCDDR21MCTL_DLLCR1, dwcddr21mctl, dllcr[1]); /* 0x28 */
  67 + OFFSET(DWCDDR21MCTL_DLLCR2, dwcddr21mctl, dllcr[2]); /* 0x2c */
  68 + OFFSET(DWCDDR21MCTL_DLLCR3, dwcddr21mctl, dllcr[3]); /* 0x30 */
  69 + OFFSET(DWCDDR21MCTL_DLLCR4, dwcddr21mctl, dllcr[4]); /* 0x34 */
  70 + OFFSET(DWCDDR21MCTL_DLLCR5, dwcddr21mctl, dllcr[5]); /* 0x38 */
  71 + OFFSET(DWCDDR21MCTL_DLLCR6, dwcddr21mctl, dllcr[6]); /* 0x3c */
  72 + OFFSET(DWCDDR21MCTL_DLLCR7, dwcddr21mctl, dllcr[7]); /* 0x40 */
  73 + OFFSET(DWCDDR21MCTL_DLLCR8, dwcddr21mctl, dllcr[8]); /* 0x44 */
  74 + OFFSET(DWCDDR21MCTL_DLLCR9, dwcddr21mctl, dllcr[9]); /* 0x48 */
  75 + OFFSET(DWCDDR21MCTL_RSLR0, dwcddr21mctl, rslr[0]); /* 0x4c */
  76 + OFFSET(DWCDDR21MCTL_RDGR0, dwcddr21mctl, rdgr[0]); /* 0x5c */
  77 + OFFSET(DWCDDR21MCTL_DTAR, dwcddr21mctl, dtar); /* 0xa4 */
  78 + OFFSET(DWCDDR21MCTL_MR, dwcddr21mctl, mr); /* 0x1f0 */
  79 +#endif
  80 +
  81 + return 0;
  82 +}
arch/x86/cpu/coreboot/asm-offsets.c
View file @ 254d68b
1   -/*
2   - * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
3   - *
4   - * This program is used to generate definitions needed by
5   - * assembly language modules.
6   - *
7   - * We use the technique used in the OSF Mach kernel code:
8   - * generate asm statements containing #defines,
9   - * compile this file to assembler, and then extract the
10   - * #defines from the assembly-language output.
11   - *
12   - * SPDX-License-Identifier: GPL-2.0+
13   - */
14   -
15   -#include <common.h>
16   -#include <linux/kbuild.h>
17   -
18   -int main(void)
19   -{
20   - DEFINE(GENERATED_GD_RELOC_OFF, offsetof(gd_t, reloc_off));
21   - return 0;
22   -}
arch/x86/lib/asm-offsets.c
Diff comments   View file @ 254d68b
  1 +/*
  2 + * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
  3 + *
  4 + * This program is used to generate definitions needed by
  5 + * assembly language modules.
  6 + *
  7 + * We use the technique used in the OSF Mach kernel code:
  8 + * generate asm statements containing #defines,
  9 + * compile this file to assembler, and then extract the
  10 + * #defines from the assembly-language output.
  11 + *
  12 + * SPDX-License-Identifier: GPL-2.0+
  13 + */
  14 +
  15 +#include <common.h>
  16 +#include <linux/kbuild.h>
  17 +
  18 +int main(void)
  19 +{
  20 + DEFINE(GENERATED_GD_RELOC_OFF, offsetof(gd_t, reloc_off));
  21 + return 0;
  22 +}