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Commit 255ef4d9091fe896ff152629a8cb290ee92c9fde

Authored by Dirk Eibach
Committed by Stefan Roese
1 parent a6569c63b3
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ppc4xx: Add Io64 board support 

Board support for the Guntermann & Drunck Io64.

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>

Showing 11 changed files with 1431 additions and 8 deletions Side-by-side Diff

... ... @@ -150,6 +150,7 @@
150 150 gdppc440etx PPC440EP/GR
151 151 intip PPC460EX
152 152 io PPC405EP
  153 + io64 PPC405EX
153 154 iocon PPC405EP
154 155 neo PPC405EP
155 156  
board/gdsys/405ex/405ex.c
Diff comments   View file @ 255ef4d
  1 +#include <common.h>
  2 +#include <asm/ppc4xx.h>
  3 +#include <asm/ppc405.h>
  4 +#include <asm/processor.h>
  5 +#include <asm/io.h>
  6 +
  7 +#include <gdsys_fpga.h>
  8 +
  9 +#include "405ex.h"
  10 +
  11 +#define REFLECTION_TESTPATTERN 0xdede
  12 +#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
  13 +
  14 +DECLARE_GLOBAL_DATA_PTR;
  15 +
  16 +int get_fpga_state(unsigned dev)
  17 +{
  18 + return gd->fpga_state[dev];
  19 +}
  20 +
  21 +void print_fpga_state(unsigned dev)
  22 +{
  23 + if (gd->fpga_state[dev] & FPGA_STATE_DONE_FAILED)
  24 + puts(" Waiting for FPGA-DONE timed out.\n");
  25 + if (gd->fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
  26 + puts(" FPGA reflection test failed.\n");
  27 +}
  28 +
  29 +int board_early_init_f(void)
  30 +{
  31 + u32 val;
  32 +
  33 + /*--------------------------------------------------------------------+
  34 + | Interrupt controller setup
  35 + +--------------------------------------------------------------------+
  36 + +---------------------------------------------------------------------+
  37 + |Interrupt| Source | Pol. | Sensi.| Crit. |
  38 + +---------+-----------------------------------+-------+-------+-------+
  39 + | IRQ 00 | UART0 | High | Level | Non |
  40 + | IRQ 01 | UART1 | High | Level | Non |
  41 + | IRQ 02 | IIC0 | High | Level | Non |
  42 + | IRQ 03 | TBD | High | Level | Non |
  43 + | IRQ 04 | TBD | High | Level | Non |
  44 + | IRQ 05 | EBM | High | Level | Non |
  45 + | IRQ 06 | BGI | High | Level | Non |
  46 + | IRQ 07 | IIC1 | Rising| Edge | Non |
  47 + | IRQ 08 | SPI | High | Lvl/ed| Non |
  48 + | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non |
  49 + | IRQ 10 | MAL TX EOB | High | Level | Non |
  50 + | IRQ 11 | MAL RX EOB | High | Level | Non |
  51 + | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non |
  52 + | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non |
  53 + | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non |
  54 + | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non |
  55 + | IRQ 16 | PCIE0 AL | high | Level | Non |
  56 + | IRQ 17 | PCIE0 VPD access | rising| Edge | Non |
  57 + | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non |
  58 + | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non |
  59 + | IRQ 20 | PCIE0 TCR | High | Level | Non |
  60 + | IRQ 21 | PCIE0 MSI level0 | High | Level | Non |
  61 + | IRQ 22 | PCIE0 MSI level1 | High | Level | Non |
  62 + | IRQ 23 | Security EIP-94 | High | Level | Non |
  63 + | IRQ 24 | EMAC0 interrupt | High | Level | Non |
  64 + | IRQ 25 | EMAC1 interrupt | High | Level | Non |
  65 + | IRQ 26 | PCIE0 MSI level2 | High | Level | Non |
  66 + | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non |
  67 + | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non |
  68 + | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. |
  69 + | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non |
  70 + | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. |
  71 + |----------------------------------------------------------------------
  72 + | IRQ 32 | MAL Serr | High | Level | Non |
  73 + | IRQ 33 | MAL Txde | High | Level | Non |
  74 + | IRQ 34 | MAL Rxde | High | Level | Non |
  75 + | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non |
  76 + | IRQ 36 | PCIE0 DCR Error | High | Level | Non |
  77 + | IRQ 37 | EBC | High |Lvl Edg| Non |
  78 + | IRQ 38 | NDFC | High | Level | Non |
  79 + | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non |
  80 + | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non |
  81 + | IRQ 41 | PCIE1 AL | high | Level | Non |
  82 + | IRQ 42 | PCIE1 VPD access | rising| edge | Non |
  83 + | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non |
  84 + | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non |
  85 + | IRQ 45 | PCIE1 TCR | High | Level | Non |
  86 + | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non |
  87 + | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
  88 + | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
  89 + | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non |
  90 + | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non |
  91 + | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
  92 + | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non |
  93 + | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non |
  94 + | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non |
  95 + | IRQ 55 | Serial ROM | High | Level | Non |
  96 + | IRQ 56 | GPT Decrement Pulse | High | Level | Non |
  97 + | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non |
  98 + | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non |
  99 + | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non |
  100 + | IRQ 60 | EMAC0 Wake-up | High | Level | Non |
  101 + | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non |
  102 + | IRQ 62 | EMAC1 Wake-up | High | Level | Non |
  103 + |----------------------------------------------------------------------
  104 + | IRQ 64 | PE0 AL | High | Level | Non |
  105 + | IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
  106 + | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
  107 + | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
  108 + | IRQ 68 | PE0 TCR | High | Level | Non |
  109 + | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
  110 + | IRQ 70 | PE0 DCR Error | High | Level | Non |
  111 + | IRQ 71 | Reserved | N/A | N/A | Non |
  112 + | IRQ 72 | PE1 AL | High | Level | Non |
  113 + | IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
  114 + | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
  115 + | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
  116 + | IRQ 76 | PE1 TCR | High | Level | Non |
  117 + | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
  118 + | IRQ 78 | PE1 DCR Error | High | Level | Non |
  119 + | IRQ 79 | Reserved | N/A | N/A | Non |
  120 + | IRQ 80 | PE2 AL | High | Level | Non |
  121 + | IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
  122 + | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
  123 + | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
  124 + | IRQ 84 | PE2 TCR | High | Level | Non |
  125 + | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
  126 + | IRQ 86 | PE2 DCR Error | High | Level | Non |
  127 + | IRQ 87 | Reserved | N/A | N/A | Non |
  128 + | IRQ 88 | External IRQ(5) | Progr | Progr | Non |
  129 + | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
  130 + | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
  131 + | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
  132 + | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
  133 + | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
  134 + | IRQ 94 | Reserved | N/A | N/A | Non |
  135 + | IRQ 95 | Reserved | N/A | N/A | Non |
  136 + |---------------------------------------------------------------------
  137 + +---------+-----------------------------------+-------+-------+------*/
  138 + /*--------------------------------------------------------------------+
  139 + | Initialise UIC registers. Clear all interrupts. Disable all
  140 + | interrupts.
  141 + | Set critical interrupt values. Set interrupt polarities. Set
  142 + | interrupt trigger levels. Make bit 0 High priority. Clear all
  143 + | interrupts again.
  144 + +-------------------------------------------------------------------*/
  145 +
  146 + mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */
  147 + mtdcr(UIC2ER, 0x00000000); /* disable all interrupts */
  148 + mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */
  149 + mtdcr(UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */
  150 + mtdcr(UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */
  151 + mtdcr(UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
  152 + mtdcr(UIC2SR, 0x00000000); /* clear all interrupts */
  153 + mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */
  154 +
  155 + mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts */
  156 + mtdcr(UIC1ER, 0x00000000); /* disable all interrupts */
  157 + mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */
  158 + mtdcr(UIC1PR, 0xfffac785); /* Set Interrupt Polarities */
  159 + mtdcr(UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */
  160 + mtdcr(UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
  161 + mtdcr(UIC1SR, 0x00000000); /* clear all interrupts */
  162 + mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts */
  163 +
  164 + mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */
  165 + mtdcr(UIC0ER, 0x0000000a); /* Disable all interrupts */
  166 + /* Except cascade UIC0 and UIC1 */
  167 + mtdcr(UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */
  168 + mtdcr(UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */
  169 + mtdcr(UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */
  170 + mtdcr(UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
  171 + mtdcr(UIC0SR, 0x00000000); /* clear all interrupts */
  172 + mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts */
  173 +
  174 + /*
  175 + * Note: Some cores are still in reset when the chip starts, so
  176 + * take them out of reset
  177 + */
  178 + mtsdr(SDR0_SRST, 0);
  179 +
  180 + /*
  181 + * Configure PFC (Pin Function Control) registers
  182 + */
  183 + val = SDR0_PFC1_GPT_FREQ;
  184 + mtsdr(SDR0_PFC1, val);
  185 +
  186 + return 0;
  187 +}
  188 +
  189 +int board_early_init_r(void)
  190 +{
  191 + unsigned k;
  192 + unsigned ctr;
  193 +
  194 + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
  195 + gd->fpga_state[k] = 0;
  196 +
  197 + /*
  198 + * reset FPGA
  199 + */
  200 + gd405ex_init();
  201 +
  202 + gd405ex_set_fpga_reset(1);
  203 +
  204 + gd405ex_setup_hw();
  205 +
  206 + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
  207 + ctr = 0;
  208 + while (!gd405ex_get_fpga_done(k)) {
  209 + udelay(100000);
  210 + if (ctr++ > 5) {
  211 + gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED;
  212 + break;
  213 + }
  214 + }
  215 + }
  216 +
  217 + udelay(10);
  218 +
  219 + gd405ex_set_fpga_reset(0);
  220 +
  221 + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
  222 + ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k);
  223 +#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
  224 + u16 *reflection_target = &fpga->reflection_low;
  225 +#else
  226 + u16 *reflection_target = &fpga->reflection_high;
  227 +#endif
  228 + /*
  229 + * wait for fpga out of reset
  230 + */
  231 + ctr = 0;
  232 + while (1) {
  233 + out_le16(&fpga->reflection_low,
  234 + REFLECTION_TESTPATTERN);
  235 +
  236 + if (in_le16(reflection_target) ==
  237 + REFLECTION_TESTPATTERN_INV)
  238 + break;
  239 +
  240 + udelay(100000);
  241 + if (ctr++ > 5) {
  242 + gd->fpga_state[k] |=
  243 + FPGA_STATE_REFLECTION_FAILED;
  244 + break;
  245 + }
  246 + }
  247 + }
  248 +
  249 + return 0;
  250 +}
board/gdsys/405ex/405ex.h
Diff comments   View file @ 255ef4d
  1 +#ifndef __405EX_H_
  2 +#define __405EX_H_
  3 +
  4 +/* functions to be provided by board implementation */
  5 +void gd405ex_init(void);
  6 +void gd405ex_set_fpga_reset(unsigned state);
  7 +void gd405ex_setup_hw(void);
  8 +int gd405ex_get_fpga_done(unsigned fpga);
  9 +
  10 +#endif /* __405EX_H_ */
board/gdsys/405ex/Makefile
Diff comments   View file @ 255ef4d
  1 +#
  2 +# (C) Copyright 2007
  3 +# Stefan Roese, DENX Software Engineering, sr@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +include $(TOPDIR)/config.mk
  25 +
  26 +LIB = $(obj)lib$(BOARD).o
  27 +
  28 +COBJS-$(CONFIG_IO64) += io64.o
  29 +
  30 +COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
  31 +
  32 +COBJS := $(BOARD).o $(COBJS-y)
  33 +
  34 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
  35 +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
  36 +
  37 +$(LIB): $(obj).depend $(OBJS)
  38 + $(call cmd_link_o_target, $(OBJS))
  39 +
  40 +clean:
  41 + rm -f $(OBJS)
  42 +
  43 +distclean: clean
  44 + rm -f $(LIB) core *.bak $(obj).depend
  45 +
  46 +#########################################################################
  47 +
  48 +# defines $(obj).depend target
  49 +include $(SRCTREE)/rules.mk
  50 +
  51 +sinclude $(obj).depend
  52 +
  53 +#########################################################################
board/gdsys/405ex/chip_config.c
Diff comments   View file @ 255ef4d
  1 +/*
  2 + * (C) Copyright 2009
  3 + * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + *
  23 + */
  24 +
  25 +#include <common.h>
  26 +#include <asm/ppc4xx_config.h>
  27 +
  28 +/* NAND booting versions differ in bytes: 6, 8, 9, 11, 12 */
  29 +
  30 +struct ppc4xx_config ppc4xx_config_val[] = {
  31 + {
  32 + "333-nor", "NOR CPU: 333 PLB: 166 OPB: 83 EBC: 83",
  33 + {
  34 + 0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00,
  35 + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
  36 + }
  37 + },
  38 + {
  39 + "400-133-nor", "NOR CPU: 400 PLB: 133 OPB: 66 EBC: 66",
  40 + {
  41 + 0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00,
  42 + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
  43 + }
  44 + },
  45 + {
  46 + "400-200-66-nor", "NOR CPU: 400 PLB: 200 OPB: 66 EBC: 66",
  47 + {
  48 + 0x8e, 0x0e, 0xe8, 0x12, 0xd8, 0x00, 0x0a, 0x00,
  49 + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
  50 + }
  51 + },
  52 + {
  53 + "400-nor", "NOR CPU: 400 PLB: 200 OPB: 100 EBC: 100",
  54 + {
  55 + 0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00,
  56 + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
  57 + }
  58 + },
  59 + {
  60 + "533-nor", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88",
  61 + {
  62 + 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00,
  63 + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
  64 + }
  65 + },
  66 + {
  67 + "533-nand", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88",
  68 + {
  69 + 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0f, 0x00,
  70 + 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
  71 + }
  72 + },
  73 + {
  74 + "600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100",
  75 + {
  76 + 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00,
  77 + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
  78 + }
  79 + },
  80 + {
  81 + "600-nand", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100",
  82 + {
  83 + 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0f, 0x00,
  84 + 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
  85 + }
  86 + },
  87 + {
  88 + "666-nor", "NOR CPU: 666 PLB: 222 OPB: 111 EBC: 111",
  89 + {
  90 + 0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00,
  91 + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
  92 + }
  93 + },
  94 +};
  95 +
  96 +int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
board/gdsys/405ex/io64.c
Diff comments   View file @ 255ef4d
  1 +/*
  2 + * (C) Copyright 2010
  3 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
  4 + *
  5 + * based on kilauea.c
  6 + * by Stefan Roese, DENX Software Engineering, sr@denx.de.
  7 + *
  8 + * See file CREDITS for list of people who contributed to this
  9 + * project.
  10 + *
  11 + * This program is free software; you can redistribute it and/or
  12 + * modify it under the terms of the GNU General Public License as
  13 + * published by the Free Software Foundation; either version 2 of
  14 + * the License, or (at your option) any later version.
  15 + *
  16 + * This program is distributed in the hope that it will be useful,
  17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19 + * GNU General Public License for more details.
  20 + *
  21 + * You should have received a copy of the GNU General Public License
  22 + * along with this program; if not, write to the Free Software
  23 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 + * MA 02111-1307 USA
  25 + */
  26 +
  27 +#include <common.h>
  28 +#include <asm/ppc4xx.h>
  29 +#include <asm/ppc405.h>
  30 +#include <libfdt.h>
  31 +#include <fdt_support.h>
  32 +#include <asm/processor.h>
  33 +#include <asm/io.h>
  34 +#include <asm/errno.h>
  35 +#include <asm/ppc4xx-gpio.h>
  36 +#include <flash.h>
  37 +
  38 +#include <pca9698.h>
  39 +
  40 +#include "405ex.h"
  41 +#include <gdsys_fpga.h>
  42 +
  43 +#include <miiphy.h>
  44 +#include <i2c.h>
  45 +#include <dtt.h>
  46 +
  47 +DECLARE_GLOBAL_DATA_PTR;
  48 +
  49 +#define PHYREG_CONTROL 0
  50 +#define PHYREG_PAGE_ADDRESS 22
  51 +#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
  52 +#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
  53 +#define PHYREG_PG2_MAC_SPECIFIC_STATUS_1 17
  54 +#define PHYREG_PG2_MAC_SPECIFIC_CONTROL 21
  55 +
  56 +#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
  57 +#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
  58 +#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
  59 +#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
  60 +
  61 +enum {
  62 + UNITTYPE_CCD_SWITCH = 1,
  63 +};
  64 +
  65 +enum {
  66 + HWVER_100 = 0,
  67 + HWVER_110 = 1,
  68 +};
  69 +
  70 +static inline void blank_string(int size)
  71 +{
  72 + int i;
  73 +
  74 + for (i = 0; i < size; i++)
  75 + putc('\b');
  76 + for (i = 0; i < size; i++)
  77 + putc(' ');
  78 + for (i = 0; i < size; i++)
  79 + putc('\b');
  80 +}
  81 +
  82 +/*
  83 + * Board early initialization function
  84 + */
  85 +int misc_init_r(void)
  86 +{
  87 + /* startup fans */
  88 + dtt_init();
  89 +
  90 +#ifdef CONFIG_ENV_IS_IN_FLASH
  91 + /* Monitor protection ON by default */
  92 + flash_protect(FLAG_PROTECT_SET,
  93 + -CONFIG_SYS_MONITOR_LEN,
  94 + 0xffffffff,
  95 + &flash_info[0]);
  96 +#endif
  97 +
  98 + return 0;
  99 +}
  100 +
  101 +static void print_fpga_info(unsigned dev)
  102 +{
  103 + ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev);
  104 + u16 versions = in_le16(&fpga->versions);
  105 + u16 fpga_version = in_le16(&fpga->fpga_version);
  106 + u16 fpga_features = in_le16(&fpga->fpga_features);
  107 + int fpga_state = get_fpga_state(dev);
  108 +
  109 + unsigned unit_type;
  110 + unsigned hardware_version;
  111 + unsigned feature_channels;
  112 + unsigned feature_expansion;
  113 +
  114 + printf("FPGA%d: ", dev);
  115 + if (fpga_state & FPGA_STATE_PLATFORM)
  116 + printf("(legacy) ");
  117 +
  118 + if (fpga_state & FPGA_STATE_DONE_FAILED) {
  119 + printf(" done timed out\n");
  120 + return;
  121 + }
  122 +
  123 + if (fpga_state & FPGA_STATE_REFLECTION_FAILED) {
  124 + printf(" refelectione test failed\n");
  125 + return;
  126 + }
  127 +
  128 + unit_type = (versions & 0xf000) >> 12;
  129 + hardware_version = versions & 0x000f;
  130 + feature_channels = fpga_features & 0x007f;
  131 + feature_expansion = fpga_features & (1<<15);
  132 +
  133 + switch (unit_type) {
  134 + case UNITTYPE_CCD_SWITCH:
  135 + printf("CCD-Switch");
  136 + break;
  137 +
  138 + default:
  139 + printf("UnitType %d(not supported)", unit_type);
  140 + break;
  141 + }
  142 +
  143 + switch (hardware_version) {
  144 + case HWVER_100:
  145 + printf(" HW-Ver 1.00\n");
  146 + break;
  147 +
  148 + case HWVER_110:
  149 + printf(" HW-Ver 1.10\n");
  150 + break;
  151 +
  152 + default:
  153 + printf(" HW-Ver %d(not supported)\n",
  154 + hardware_version);
  155 + break;
  156 + }
  157 +
  158 + printf(" FPGA V %d.%02d, features:",
  159 + fpga_version / 100, fpga_version % 100);
  160 +
  161 + printf(" %d channel(s)", feature_channels);
  162 +
  163 + printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
  164 +}
  165 +
  166 +int checkboard(void)
  167 +{
  168 + char *s = getenv("serial#");
  169 +
  170 + printf("Board: CATCenter Io64\n");
  171 +
  172 + if (s != NULL) {
  173 + puts(", serial# ");
  174 + puts(s);
  175 + }
  176 +
  177 + return 0;
  178 +}
  179 +
  180 +int configure_gbit_phy(char *bus, unsigned char addr)
  181 +{
  182 + unsigned short value;
  183 +
  184 + /* select page 0 */
  185 + if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000))
  186 + goto err_out;
  187 + /* switch to powerdown */
  188 + if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
  189 + &value))
  190 + goto err_out;
  191 + if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
  192 + value | 0x0004))
  193 + goto err_out;
  194 + /* select page 2 */
  195 + if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002))
  196 + goto err_out;
  197 + /* disable SGMII autonegotiation */
  198 + if (miiphy_write(bus, addr, PHYREG_PG2_MAC_SPECIFIC_CONTROL, 48))
  199 + goto err_out;
  200 + /* select page 0 */
  201 + if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000))
  202 + goto err_out;
  203 + /* switch from powerdown to normal operation */
  204 + if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
  205 + &value))
  206 + goto err_out;
  207 + if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
  208 + value & ~0x0004))
  209 + goto err_out;
  210 + /* reset phy so settings take effect */
  211 + if (miiphy_write(bus, addr, PHYREG_CONTROL, 0x9140))
  212 + goto err_out;
  213 +
  214 + return 0;
  215 +
  216 +err_out:
  217 + printf("Error writing to the PHY addr=%02x\n", addr);
  218 + return -1;
  219 +}
  220 +
  221 +int verify_gbit_phy(char *bus, unsigned char addr)
  222 +{
  223 + unsigned short value;
  224 +
  225 + /* select page 2 */
  226 + if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002))
  227 + goto err_out;
  228 + /* verify SGMII link status */
  229 + if (miiphy_read(bus, addr, PHYREG_PG2_MAC_SPECIFIC_STATUS_1, &value))
  230 + goto err_out;
  231 + if (!(value & (1 << 10)))
  232 + return -2;
  233 +
  234 + return 0;
  235 +
  236 +err_out:
  237 + printf("Error writing to the PHY addr=%02x\n", addr);
  238 + return -1;
  239 +}
  240 +
  241 +int last_stage_init(void)
  242 +{
  243 + unsigned int k;
  244 + unsigned int fpga;
  245 + ihs_fpga_t *fpga0 = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
  246 + ihs_fpga_t *fpga1 = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(1);
  247 + int failed = 0;
  248 + char str_phys[] = "Setup PHYs -";
  249 + char str_serdes[] = "Start SERDES blocks";
  250 + char str_channels[] = "Start FPGA channels";
  251 + char str_locks[] = "Verify SERDES locks";
  252 + char str_status[] = "Verify PHY status -";
  253 + char slash[] = "\\|/-\\|/-";
  254 +
  255 + print_fpga_info(0);
  256 + print_fpga_info(1);
  257 +
  258 + /* setup Gbit PHYs */
  259 + puts("TRANS: ");
  260 + puts(str_phys);
  261 + miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
  262 + bb_miiphy_read, bb_miiphy_write);
  263 +
  264 + for (k = 0; k < 32; ++k) {
  265 + configure_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k);
  266 + putc('\b');
  267 + putc(slash[k % 8]);
  268 + }
  269 +
  270 + miiphy_register(CONFIG_SYS_GBIT_MII1_BUSNAME,
  271 + bb_miiphy_read, bb_miiphy_write);
  272 +
  273 + for (k = 0; k < 32; ++k) {
  274 + configure_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k);
  275 + putc('\b');
  276 + putc(slash[k % 8]);
  277 + }
  278 + blank_string(strlen(str_phys));
  279 +
  280 + /* take fpga serdes blocks out of reset */
  281 + puts(str_serdes);
  282 + udelay(500000);
  283 + out_le16(&fpga0->quad_serdes_reset, 0);
  284 + out_le16(&fpga1->quad_serdes_reset, 0);
  285 + blank_string(strlen(str_serdes));
  286 +
  287 + /* take channels out of reset */
  288 + puts(str_channels);
  289 + udelay(500000);
  290 + for (fpga = 0; fpga < 2; ++fpga) {
  291 + u16 *ch0_config_int = &(fpga ? fpga1 : fpga0)->ch0_config_int;
  292 + for (k = 0; k < 32; ++k)
  293 + out_le16(ch0_config_int + 4 * k, 0);
  294 + }
  295 + blank_string(strlen(str_channels));
  296 +
  297 + /* verify channels serdes lock */
  298 + puts(str_locks);
  299 + udelay(500000);
  300 + for (fpga = 0; fpga < 2; ++fpga) {
  301 + u16 *ch0_status_int = &(fpga ? fpga1 : fpga0)->ch0_status_int;
  302 + for (k = 0; k < 32; ++k) {
  303 + u16 status = in_le16(ch0_status_int + 4*k);
  304 + if (!(status & (1 << 4))) {
  305 + failed = 1;
  306 + printf("fpga %d channel %d: no serdes lock\n",
  307 + fpga, k);
  308 + }
  309 + /* reset events */
  310 + out_le16(ch0_status_int + 4*k, status);
  311 + }
  312 + }
  313 + blank_string(strlen(str_locks));
  314 +
  315 + /* verify phy status */
  316 + puts(str_status);
  317 + for (k = 0; k < 32; ++k) {
  318 + if (verify_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k)) {
  319 + printf("verify baseboard phy %d failed\n", k);
  320 + failed = 1;
  321 + }
  322 + putc('\b');
  323 + putc(slash[k % 8]);
  324 + }
  325 + for (k = 0; k < 32; ++k) {
  326 + if (verify_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k)) {
  327 + printf("verify extensionboard phy %d failed\n", k);
  328 + failed = 1;
  329 + }
  330 + putc('\b');
  331 + putc(slash[k % 8]);
  332 + }
  333 + blank_string(strlen(str_status));
  334 +
  335 + printf("Starting 64 channels %s\n", failed ? "failed" : "ok");
  336 +
  337 + return 0;
  338 +}
  339 +
  340 +void gd405ex_init(void)
  341 +{
  342 + unsigned int k;
  343 +
  344 + if (i2c_probe(0x22)) { /* i2c_probe returns 0 on success */
  345 + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
  346 + gd->fpga_state[k] |= FPGA_STATE_PLATFORM;
  347 + } else {
  348 + pca9698_direction_output(0x22, 39, 1);
  349 + }
  350 +}
  351 +
  352 +void gd405ex_set_fpga_reset(unsigned state)
  353 +{
  354 + int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
  355 +
  356 + if (legacy) {
  357 + if (state) {
  358 + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
  359 + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
  360 + } else {
  361 + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
  362 + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
  363 + }
  364 + } else {
  365 + pca9698_set_value(0x22, 39, state ? 0 : 1);
  366 + }
  367 +}
  368 +
  369 +void gd405ex_setup_hw(void)
  370 +{
  371 + gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED_N, 0);
  372 + gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED, 1);
  373 +}
  374 +
  375 +int gd405ex_get_fpga_done(unsigned fpga)
  376 +{
  377 + int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
  378 +
  379 + if (legacy)
  380 + return in_le16((void *)LATCH3_BASE)
  381 + & CONFIG_SYS_FPGA_DONE(fpga);
  382 + else
  383 + return pca9698_get_value(0x22, fpga ? 9 : 8);
  384 +}
board/gdsys/common/Makefile
Diff comments   View file @ 255ef4d
... ... @@ -30,6 +30,7 @@
30 30 LIB = $(obj)lib$(VENDOR).o
31 31  
32 32 COBJS-$(CONFIG_IO) += miiphybb.o
  33 +COBJS-$(CONFIG_IO64) += miiphybb.o
33 34 COBJS-$(CONFIG_IOCON) += osd.o
34 35 COBJS-$(CONFIG_DLVISION_10G) += osd.o
35 36  
board/gdsys/common/miiphybb.c
Diff comments   View file @ 255ef4d
... ... @@ -26,6 +26,11 @@
26 26  
27 27 #include <asm/io.h>
28 28  
  29 +struct io_bb_pinset {
  30 + int mdio;
  31 + int mdc;
  32 +};
  33 +
29 34 static int io_bb_mii_init(struct bb_miiphy_bus *bus)
30 35 {
31 36 return 0;
32 37  
33 38  
34 39  
35 40  
36 41  
37 42  
38 43  
39 44  
40 45  
41 46  
42 47  
... ... @@ -33,47 +38,57 @@
33 38  
34 39 static int io_bb_mdio_active(struct bb_miiphy_bus *bus)
35 40 {
  41 + struct io_bb_pinset *pins = bus->priv;
  42 +
36 43 out_be32((void *)GPIO0_TCR,
37   - in_be32((void *)GPIO0_TCR) | CONFIG_SYS_MDIO_PIN);
  44 + in_be32((void *)GPIO0_TCR) | pins->mdio);
38 45  
39 46 return 0;
40 47 }
41 48  
42 49 static int io_bb_mdio_tristate(struct bb_miiphy_bus *bus)
43 50 {
  51 + struct io_bb_pinset *pins = bus->priv;
  52 +
44 53 out_be32((void *)GPIO0_TCR,
45   - in_be32((void *)GPIO0_TCR) & ~CONFIG_SYS_MDIO_PIN);
  54 + in_be32((void *)GPIO0_TCR) & ~pins->mdio);
46 55  
47 56 return 0;
48 57 }
49 58  
50 59 static int io_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
51 60 {
  61 + struct io_bb_pinset *pins = bus->priv;
  62 +
52 63 if (v)
53 64 out_be32((void *)GPIO0_OR,
54   - in_be32((void *)GPIO0_OR) | CONFIG_SYS_MDIO_PIN);
  65 + in_be32((void *)GPIO0_OR) | pins->mdio);
55 66 else
56 67 out_be32((void *)GPIO0_OR,
57   - in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_MDIO_PIN);
  68 + in_be32((void *)GPIO0_OR) & ~pins->mdio);
58 69  
59 70 return 0;
60 71 }
61 72  
62 73 static int io_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
63 74 {
64   - *v = ((in_be32((void *)GPIO0_IR) & CONFIG_SYS_MDIO_PIN) != 0);
  75 + struct io_bb_pinset *pins = bus->priv;
65 76  
  77 + *v = ((in_be32((void *)GPIO0_IR) & pins->mdio) != 0);
  78 +
66 79 return 0;
67 80 }
68 81  
69 82 static int io_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
70 83 {
  84 + struct io_bb_pinset *pins = bus->priv;
  85 +
71 86 if (v)
72 87 out_be32((void *)GPIO0_OR,
73   - in_be32((void *)GPIO0_OR) | CONFIG_SYS_MDC_PIN);
  88 + in_be32((void *)GPIO0_OR) | pins->mdc);
74 89 else
75 90 out_be32((void *)GPIO0_OR,
76   - in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_MDC_PIN);
  91 + in_be32((void *)GPIO0_OR) & ~pins->mdc);
77 92  
78 93 return 0;
79 94 }
... ... @@ -85,6 +100,19 @@
85 100 return 0;
86 101 }
87 102  
  103 +struct io_bb_pinset io_bb_pinsets[] = {
  104 + {
  105 + .mdio = CONFIG_SYS_MDIO_PIN,
  106 + .mdc = CONFIG_SYS_MDC_PIN,
  107 + },
  108 +#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME
  109 + {
  110 + .mdio = CONFIG_SYS_MDIO1_PIN,
  111 + .mdc = CONFIG_SYS_MDC1_PIN,
  112 + },
  113 +#endif
  114 +};
  115 +
88 116 struct bb_miiphy_bus bb_miiphy_buses[] = {
89 117 {
90 118 .name = CONFIG_SYS_GBIT_MII_BUSNAME,
... ... @@ -95,7 +123,21 @@
95 123 .get_mdio = io_bb_get_mdio,
96 124 .set_mdc = io_bb_set_mdc,
97 125 .delay = io_bb_delay,
98   - }
  126 + .priv = &io_bb_pinsets[0],
  127 + },
  128 +#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME
  129 + {
  130 + .name = CONFIG_SYS_GBIT_MII1_BUSNAME,
  131 + .init = io_bb_mii_init,
  132 + .mdio_active = io_bb_mdio_active,
  133 + .mdio_tristate = io_bb_mdio_tristate,
  134 + .set_mdio = io_bb_set_mdio,
  135 + .get_mdio = io_bb_get_mdio,
  136 + .set_mdc = io_bb_set_mdc,
  137 + .delay = io_bb_delay,
  138 + .priv = &io_bb_pinsets[1],
  139 + },
  140 +#endif
99 141 };
100 142  
101 143 int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
... ... @@ -954,6 +954,7 @@
954 954 gdppc440etx powerpc ppc4xx - gdsys
955 955 intip powerpc ppc4xx intip gdsys - intip:INTIB
956 956 io powerpc ppc4xx 405ep gdsys
  957 +io64 powerpc ppc4xx 405ex gdsys
957 958 iocon powerpc ppc4xx 405ep gdsys
958 959 neo powerpc ppc4xx - gdsys
959 960 icon powerpc ppc4xx - mosaixtech
include/configs/io64.h
Diff comments   View file @ 255ef4d
  1 +/*
  2 + * (C) Copyright 2011
  3 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
  4 + *
  5 + * based on kilauea.h
  6 + * by Stefan Roese, DENX Software Engineering, sr@denx.de.
  7 + * and Grant Erickson <gerickson@nuovations.com>
  8 + *
  9 + * See file CREDITS for list of people who contributed to this
  10 + * project.
  11 + *
  12 + * This program is free software; you can redistribute it and/or
  13 + * modify it under the terms of the GNU General Public License as
  14 + * published by the Free Software Foundation; either version 2 of
  15 + * the License, or (at your option) any later version.
  16 + *
  17 + * This program is distributed in the hope that it will be useful,
  18 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20 + * GNU General Public License for more details.
  21 + *
  22 + * You should have received a copy of the GNU General Public License
  23 + * along with this program; if not, write to the Free Software
  24 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25 + * MA 02111-1307 USA
  26 + */
  27 +
  28 +/************************************************************************
  29 + * io64.h - configuration for Guntermann & Drunck Io64 (405EX)
  30 + ***********************************************************************/
  31 +
  32 +#ifndef __CONFIG_H
  33 +#define __CONFIG_H
  34 +
  35 +/*-----------------------------------------------------------------------
  36 + * High Level Configuration Options
  37 + *----------------------------------------------------------------------*/
  38 +#define CONFIG_IO64 1 /* Board is Io64 */
  39 +#define CONFIG_4xx 1 /* ... PPC4xx family */
  40 +#define CONFIG_405EX 1 /* Specifc 405EX support*/
  41 +#define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */
  42 +
  43 +#ifndef CONFIG_SYS_TEXT_BASE
  44 +#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
  45 +#endif
  46 +
  47 +/*
  48 + * CHIP_21 errata
  49 + */
  50 +#define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
  51 +
  52 +/*
  53 + * Include common defines/options for all AMCC eval boards
  54 + */
  55 +#define CONFIG_HOSTNAME io64
  56 +#define CONFIG_IDENT_STRING " io64 0.01"
  57 +#include "amcc-common.h"
  58 +
  59 +#define CONFIG_BOARD_EARLY_INIT_F
  60 +#define CONFIG_BOARD_EARLY_INIT_R
  61 +#define CONFIG_MISC_INIT_R
  62 +#define CONFIG_LAST_STAGE_INIT
  63 +
  64 +#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
  65 +#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
  66 +#define CONFIG_AUTOBOOT_STOP_STR " "
  67 +
  68 +/* new uImage format support */
  69 +#define CONFIG_FIT
  70 +#define CONFIG_FIT_VERBOSE
  71 +
  72 +/*-----------------------------------------------------------------------
  73 + * Base addresses -- Note these are effective addresses where the
  74 + * actual resources get mapped (not physical addresses)
  75 + *----------------------------------------------------------------------*/
  76 +#define CONFIG_SYS_FLASH_BASE 0xFC000000
  77 +#define CONFIG_SYS_NVRAM_BASE 0xF0000000
  78 +#define CONFIG_SYS_FPGA0_BASE 0xF0100000
  79 +#define CONFIG_SYS_FPGA1_BASE 0xF0108000
  80 +#define CONFIG_SYS_LATCH_BASE 0xF0200000
  81 +
  82 +/*-----------------------------------------------------------------------
  83 + * Initial RAM & Stack Pointer Configuration Options
  84 + *
  85 + * There are traditionally three options for the primordial
  86 + * (i.e. initial) stack usage on the 405-series:
  87 + *
  88 + * 1) On-chip Memory (OCM) (i.e. SRAM)
  89 + * 2) Data cache
  90 + * 3) SDRAM
  91 + *
  92 + * For the 405EX(r), there is no OCM, so we are left with (2) or (3)
  93 + * the latter of which is less than desireable since it requires
  94 + * setting up the SDRAM and ECC in assembly code.
  95 + *
  96 + * To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
  97 + * select on the External Bus Controller (EBC) and then select a
  98 + * value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
  99 + * physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
  100 + * select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
  101 + * physical SDRAM to use (3).
  102 + *-----------------------------------------------------------------------*/
  103 +
  104 +#define CONFIG_SYS_INIT_DCACHE_CS 4
  105 +
  106 +#if defined(CONFIG_SYS_INIT_DCACHE_CS)
  107 +#define CONFIG_SYS_INIT_RAM_ADDR \
  108 + (CONFIG_SYS_SDRAM_BASE + (1 << 30)) /* 1 GiB */
  109 +#else
  110 +#define CONFIG_SYS_INIT_RAM_ADDR \
  111 + (CONFIG_SYS_SDRAM_BASE + (32 << 20)) /* 32 MiB */
  112 +#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
  113 +
  114 +#define CONFIG_SYS_INIT_RAM_SIZE \
  115 + (4 << 10) /* 4 KiB */
  116 +#define CONFIG_SYS_GBL_DATA_OFFSET \
  117 + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  118 +
  119 +/*
  120 + * If the data cache is being used for the primordial stack and global
  121 + * data area, the POST word must be placed somewhere else. The General
  122 + * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
  123 + * its compare and mask register contents across reset, so it is used
  124 + * for the POST word.
  125 + */
  126 +
  127 +#if defined(CONFIG_SYS_INIT_DCACHE_CS)
  128 +# define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  129 +# define CONFIG_SYS_POST_WORD_ADDR \
  130 + (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
  131 +#else
  132 +# define CONFIG_SYS_INIT_EXTRA_SIZE 16
  133 +# define CONFIG_SYS_INIT_SP_OFFSET \
  134 + (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
  135 +# define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_INIT_RAM_ADDR
  136 +#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
  137 +
  138 +/*-----------------------------------------------------------------------
  139 + * Serial Port
  140 + *----------------------------------------------------------------------*/
  141 +#define CONFIG_CONS_INDEX 1 /* Use UART0 */
  142 +#define CONFIG_SYS_BASE_BAUD 691200
  143 +
  144 +/*-----------------------------------------------------------------------
  145 + * Environment
  146 + *----------------------------------------------------------------------*/
  147 +#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
  148 +
  149 +/*-----------------------------------------------------------------------
  150 + * FLASH related
  151 + *----------------------------------------------------------------------*/
  152 +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
  153 +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
  154 +
  155 +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
  156 +#define CONFIG_SYS_MAX_FLASH_BANKS 1
  157 +#define CONFIG_SYS_MAX_FLASH_SECT 512
  158 +
  159 +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
  160 +#define CONFIG_SYS_FLASH_WRITE_TOUT 500
  161 +
  162 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  163 +#define CONFIG_SYS_FLASH_EMPTY_INFO
  164 +
  165 +#ifdef CONFIG_ENV_IS_IN_FLASH
  166 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
  167 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
  168 +#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
  169 +
  170 +/* Address and size of Redundant Environment Sector */
  171 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
  172 +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  173 +#endif /* CONFIG_ENV_IS_IN_FLASH */
  174 +
  175 +/* Gbit PHYs */
  176 +#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
  177 +#define CONFIG_BITBANGMII_MULTI
  178 +
  179 +#define CONFIG_SYS_MDIO_PIN (0x80000000 >> 12) /* MDIO is GPIO12 */
  180 +#define CONFIG_SYS_MDC_PIN (0x80000000 >> 13) /* MDC is GPIO13 */
  181 +
  182 +#define CONFIG_SYS_GBIT_MII_BUSNAME "io_miiphy0"
  183 +
  184 +#define CONFIG_SYS_MDIO1_PIN (0x80000000 >> 2) /* MDIO is GPIO2 */
  185 +#define CONFIG_SYS_MDC1_PIN (0x80000000 >> 3) /* MDC is GPIO3 */
  186 +
  187 +#define CONFIG_SYS_GBIT_MII1_BUSNAME "io_miiphy1"
  188 +
  189 +/*-----------------------------------------------------------------------
  190 + * DDR SDRAM
  191 + *----------------------------------------------------------------------*/
  192 +#define CONFIG_SYS_MBYTES_SDRAM (128) /* 128MB */
  193 +
  194 +/*
  195 + * CONFIG_PPC4xx_DDR_AUTOCALIBRATION
  196 + *
  197 + * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx
  198 + * SDRAM Controller DDR autocalibration values and takes a lot longer
  199 + * to run than Method_B.
  200 + * (See the Method_A and Method_B algorithm discription in the file:
  201 + * arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
  202 + * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
  203 + *
  204 + * DDR Autocalibration Method_B is the default.
  205 + */
  206 +#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION
  207 +#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION
  208 +#undef CONFIG_PPC4xx_DDR_METHOD_A
  209 +
  210 +#define CONFIG_SYS_SDRAM0_MB0CF_BASE ((0 << 20) + CONFIG_SYS_SDRAM_BASE)
  211 +
  212 +/* DDR1/2 SDRAM Device Control Register Data Values */
  213 +#define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3) | \
  214 + SDRAM_RXBAS_SDSZ_128MB | \
  215 + SDRAM_RXBAS_SDAM_MODE2 | \
  216 + SDRAM_RXBAS_SDBE_ENABLE)
  217 +#define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
  218 +#define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
  219 +#define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
  220 +#define CONFIG_SYS_SDRAM0_MCOPT1 (SDRAM_MCOPT1_PMU_OPEN | \
  221 + SDRAM_MCOPT1_4_BANKS | \
  222 + SDRAM_MCOPT1_DDR2_TYPE | \
  223 + SDRAM_MCOPT1_QDEP | \
  224 + SDRAM_MCOPT1_DCOO_DISABLED)
  225 +#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
  226 +#define CONFIG_SYS_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \
  227 + SDRAM_MODT_EB0R_ENABLE)
  228 +#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
  229 +#define CONFIG_SYS_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \
  230 + SDRAM_CODT_CKLZ_36OHM | \
  231 + SDRAM_CODT_DQS_1_8_V_DDR2 | \
  232 + SDRAM_CODT_IO_NMODE)
  233 +#define CONFIG_SYS_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560)
  234 +#define CONFIG_SYS_SDRAM0_INITPLR0 (SDRAM_INITPLR_ENABLE | \
  235 + SDRAM_INITPLR_IMWT_ENCODE(80) | \
  236 + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
  237 +#define CONFIG_SYS_SDRAM0_INITPLR1 (SDRAM_INITPLR_ENABLE | \
  238 + SDRAM_INITPLR_IMWT_ENCODE(3) | \
  239 + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
  240 + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
  241 + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
  242 +#define CONFIG_SYS_SDRAM0_INITPLR2 (SDRAM_INITPLR_ENABLE | \
  243 + SDRAM_INITPLR_IMWT_ENCODE(2) | \
  244 + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
  245 + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \
  246 + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
  247 +#define CONFIG_SYS_SDRAM0_INITPLR3 (SDRAM_INITPLR_ENABLE | \
  248 + SDRAM_INITPLR_IMWT_ENCODE(2) | \
  249 + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
  250 + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \
  251 + SDRAM_INITPLR_IMA_ENCODE(0))
  252 +#define CONFIG_SYS_SDRAM0_INITPLR4 (SDRAM_INITPLR_ENABLE | \
  253 + SDRAM_INITPLR_IMWT_ENCODE(2) | \
  254 + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
  255 + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
  256 + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
  257 + JEDEC_MA_EMR_RTT_75OHM))
  258 +#define CONFIG_SYS_SDRAM0_INITPLR5 (SDRAM_INITPLR_ENABLE | \
  259 + SDRAM_INITPLR_IMWT_ENCODE(2) | \
  260 + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
  261 + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
  262 + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
  263 + JEDEC_MA_MR_CL_DDR2_5_0_CLK | \
  264 + JEDEC_MA_MR_BLEN_4 | \
  265 + JEDEC_MA_MR_DLL_RESET))
  266 +#define CONFIG_SYS_SDRAM0_INITPLR6 (SDRAM_INITPLR_ENABLE | \
  267 + SDRAM_INITPLR_IMWT_ENCODE(3) | \
  268 + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
  269 + SDRAM_INITPLR_IBA_ENCODE(0x0) | \
  270 + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
  271 +#define CONFIG_SYS_SDRAM0_INITPLR7 (SDRAM_INITPLR_ENABLE | \
  272 + SDRAM_INITPLR_IMWT_ENCODE(26) | \
  273 + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
  274 +#define CONFIG_SYS_SDRAM0_INITPLR8 (SDRAM_INITPLR_ENABLE | \
  275 + SDRAM_INITPLR_IMWT_ENCODE(26) | \
  276 + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
  277 +#define CONFIG_SYS_SDRAM0_INITPLR9 (SDRAM_INITPLR_ENABLE | \
  278 + SDRAM_INITPLR_IMWT_ENCODE(26) | \
  279 + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
  280 +#define CONFIG_SYS_SDRAM0_INITPLR10 (SDRAM_INITPLR_ENABLE | \
  281 + SDRAM_INITPLR_IMWT_ENCODE(26) | \
  282 + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
  283 +#define CONFIG_SYS_SDRAM0_INITPLR11 (SDRAM_INITPLR_ENABLE | \
  284 + SDRAM_INITPLR_IMWT_ENCODE(2) | \
  285 + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
  286 + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
  287 + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
  288 + JEDEC_MA_MR_CL_DDR2_5_0_CLK | \
  289 + JEDEC_MA_MR_BLEN_4))
  290 +#define CONFIG_SYS_SDRAM0_INITPLR12 (SDRAM_INITPLR_ENABLE | \
  291 + SDRAM_INITPLR_IMWT_ENCODE(2) | \
  292 + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
  293 + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
  294 + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
  295 + JEDEC_MA_EMR_RDQS_DISABLE | \
  296 + JEDEC_MA_EMR_DQS_DISABLE | \
  297 + JEDEC_MA_EMR_RTT_DISABLED | \
  298 + JEDEC_MA_EMR_ODS_NORMAL))
  299 +#define CONFIG_SYS_SDRAM0_INITPLR13 (SDRAM_INITPLR_ENABLE | \
  300 + SDRAM_INITPLR_IMWT_ENCODE(2) | \
  301 + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
  302 + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
  303 + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
  304 + JEDEC_MA_EMR_RDQS_DISABLE | \
  305 + JEDEC_MA_EMR_DQS_DISABLE | \
  306 + JEDEC_MA_EMR_RTT_DISABLED | \
  307 + JEDEC_MA_EMR_ODS_NORMAL))
  308 +#define CONFIG_SYS_SDRAM0_INITPLR14 (SDRAM_INITPLR_DISABLE)
  309 +#define CONFIG_SYS_SDRAM0_INITPLR15 (SDRAM_INITPLR_DISABLE)
  310 +#define CONFIG_SYS_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \
  311 + SDRAM_RQDC_RQFD_ENCODE(56))
  312 +#define CONFIG_SYS_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(521)
  313 +#define CONFIG_SYS_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2)
  314 +#define CONFIG_SYS_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \
  315 + SDRAM_DLCR_DLCS_CONT_DONE | \
  316 + SDRAM_DLCR_DLCV_ENCODE(165))
  317 +#define CONFIG_SYS_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV)
  318 +#define CONFIG_SYS_SDRAM0_WRDTR 0x00000000
  319 +#define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \
  320 + SDRAM_SDTR1_RTW_2_CLK | \
  321 + SDRAM_SDTR1_WTWO_1_CLK | \
  322 + SDRAM_SDTR1_RTRO_1_CLK)
  323 +#define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \
  324 + SDRAM_SDTR2_WTR_2_CLK | \
  325 + SDRAM_SDTR2_XSNR_32_CLK | \
  326 + SDRAM_SDTR2_WPC_4_CLK | \
  327 + SDRAM_SDTR2_RPC_2_CLK | \
  328 + SDRAM_SDTR2_RP_3_CLK | \
  329 + SDRAM_SDTR2_RRD_2_CLK)
  330 +#define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(9) | \
  331 + SDRAM_SDTR3_RC_ENCODE(12) | \
  332 + SDRAM_SDTR3_XCS | \
  333 + SDRAM_SDTR3_RFC_ENCODE(21))
  334 +#define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \
  335 + SDRAM_MMODE_DCL_DDR2_5_0_CLK | \
  336 + SDRAM_MMODE_BLEN_4)
  337 +#define CONFIG_SYS_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_DISABLE | \
  338 + SDRAM_MEMODE_RTT_75OHM)
  339 +
  340 +/*-----------------------------------------------------------------------
  341 + * I2C
  342 + *----------------------------------------------------------------------*/
  343 +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  344 +
  345 +#define CONFIG_PCA9698 1 /* NXP PCA9698 */
  346 +
  347 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */
  348 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
  349 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  350 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
  351 +
  352 +/* I2C bootstrap EEPROM */
  353 +#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54
  354 +#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
  355 +#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
  356 +
  357 +/* Temp sensor/hwmon/dtt */
  358 +#define CONFIG_DTT_LM63 1 /* National LM63 */
  359 +#define CONFIG_DTT_SENSORS { 0x18, 0x4c, 0x4e } /* Sensor addresses */
  360 +#define CONFIG_DTT_PWM_LOOKUPTABLE \
  361 + { { 40, 10 }, { 43, 13 }, { 46, 16 }, \
  362 + { 50, 20 }, { 53, 27 }, { 56, 34 }, { 60, 40 } }
  363 +#define CONFIG_DTT_TACH_LIMIT 0xa10
  364 +
  365 +/*-----------------------------------------------------------------------
  366 + * Ethernet
  367 + *----------------------------------------------------------------------*/
  368 +#define CONFIG_M88E1111_PHY 1
  369 +#define CONFIG_IBM_EMAC4_V4 1
  370 +#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII
  371 +#define CONFIG_PHY_ADDR 0x12 /* PHY address, See schematics */
  372 +
  373 +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
  374 +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
  375 +
  376 +#define CONFIG_HAS_ETH0 1
  377 +
  378 +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
  379 +#define CONFIG_PHY1_ADDR 0x13
  380 +
  381 +/* Debug messages for the DDR autocalibration */
  382 +#define CONFIG_AUTOCALIB "silent\0"
  383 +
  384 +/*
  385 + * Default environment variables
  386 + */
  387 +#define CONFIG_EXTRA_ENV_SETTINGS \
  388 + CONFIG_AMCC_DEF_ENV \
  389 + CONFIG_AMCC_DEF_ENV_POWERPC \
  390 + CONFIG_AMCC_DEF_ENV_PPC_OLD \
  391 + CONFIG_AMCC_DEF_ENV_NOR_UPD \
  392 + "logversion=2\0" \
  393 + "kernel_addr=fc000000\0" \
  394 + "fdt_addr=fc1e0000\0" \
  395 + "ramdisk_addr=fc200000\0" \
  396 + "pciconfighost=1\0" \
  397 + "pcie_mode=RP:RP\0" \
  398 + ""
  399 +
  400 +/*
  401 + * Commands additional to the ones defined in amcc-common.h
  402 + */
  403 +#define CONFIG_CMD_CHIP_CONFIG
  404 +#define CONFIG_CMD_DTT
  405 +
  406 +#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
  407 +
  408 +/* POST support */
  409 +#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
  410 + CONFIG_SYS_POST_CPU | \
  411 + CONFIG_SYS_POST_ETHER | \
  412 + CONFIG_SYS_POST_I2C | \
  413 + CONFIG_SYS_POST_MEMORY_ON | \
  414 + CONFIG_SYS_POST_UART)
  415 +
  416 +/* Define here the base-addresses of the UARTs to test in POST */
  417 +#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
  418 + CONFIG_SYS_NS16550_COM2 }
  419 +
  420 +#define CONFIG_LOGBUFFER
  421 +#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
  422 +
  423 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV
  424 +
  425 +/*-----------------------------------------------------------------------
  426 + * External Bus Controller (EBC) Setup
  427 + *----------------------------------------------------------------------*/
  428 +
  429 +/* Memory Bank 0 (NOR-flash) */
  430 +#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
  431 + EBC_BXAP_TWT_ENCODE(11) | \
  432 + EBC_BXAP_BCE_DISABLE | \
  433 + EBC_BXAP_BCT_2TRANS | \
  434 + EBC_BXAP_CSN_ENCODE(0) | \
  435 + EBC_BXAP_OEN_ENCODE(0) | \
  436 + EBC_BXAP_WBN_ENCODE(1) | \
  437 + EBC_BXAP_WBF_ENCODE(2) | \
  438 + EBC_BXAP_TH_ENCODE(2) | \
  439 + EBC_BXAP_RE_DISABLED | \
  440 + EBC_BXAP_SOR_NONDELAYED | \
  441 + EBC_BXAP_BEM_WRITEONLY | \
  442 + EBC_BXAP_PEN_DISABLED)
  443 +#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
  444 + EBC_BXCR_BS_64MB | \
  445 + EBC_BXCR_BU_RW | \
  446 + EBC_BXCR_BW_16BIT)
  447 +
  448 +/* Memory Bank 1 (NVRAM/Uart) */
  449 +#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_ENABLED | \
  450 + EBC_BXAP_FWT_ENCODE(8) | \
  451 + EBC_BXAP_BWT_ENCODE(4) | \
  452 + EBC_BXAP_BCE_DISABLE | \
  453 + EBC_BXAP_BCT_2TRANS | \
  454 + EBC_BXAP_CSN_ENCODE(0) | \
  455 + EBC_BXAP_OEN_ENCODE(1) | \
  456 + EBC_BXAP_WBN_ENCODE(1) | \
  457 + EBC_BXAP_WBF_ENCODE(1) | \
  458 + EBC_BXAP_TH_ENCODE(2) | \
  459 + EBC_BXAP_RE_DISABLED | \
  460 + EBC_BXAP_SOR_NONDELAYED | \
  461 + EBC_BXAP_BEM_WRITEONLY | \
  462 + EBC_BXAP_PEN_DISABLED)
  463 +#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_NVRAM_BASE) | \
  464 + EBC_BXCR_BS_1MB | \
  465 + EBC_BXCR_BU_RW | \
  466 + EBC_BXCR_BW_8BIT)
  467 +
  468 +/* Memory Bank 2 (FPGA) */
  469 +#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \
  470 + EBC_BXAP_TWT_ENCODE(5) | \
  471 + EBC_BXAP_BCE_DISABLE | \
  472 + EBC_BXAP_BCT_2TRANS | \
  473 + EBC_BXAP_CSN_ENCODE(0) | \
  474 + EBC_BXAP_OEN_ENCODE(2) | \
  475 + EBC_BXAP_WBN_ENCODE(1) | \
  476 + EBC_BXAP_WBF_ENCODE(1) | \
  477 + EBC_BXAP_TH_ENCODE(0) | \
  478 + EBC_BXAP_RE_DISABLED | \
  479 + EBC_BXAP_SOR_NONDELAYED | \
  480 + EBC_BXAP_BEM_WRITEONLY | \
  481 + EBC_BXAP_PEN_DISABLED)
  482 +#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
  483 + EBC_BXCR_BS_1MB | \
  484 + EBC_BXCR_BU_RW | \
  485 + EBC_BXCR_BW_16BIT)
  486 +
  487 +/* Memory Bank 3 (Latches) */
  488 +#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_ENABLED | \
  489 + EBC_BXAP_FWT_ENCODE(8) | \
  490 + EBC_BXAP_BWT_ENCODE(4) | \
  491 + EBC_BXAP_BCE_DISABLE | \
  492 + EBC_BXAP_BCT_2TRANS | \
  493 + EBC_BXAP_CSN_ENCODE(0) | \
  494 + EBC_BXAP_OEN_ENCODE(1) | \
  495 + EBC_BXAP_WBN_ENCODE(1) | \
  496 + EBC_BXAP_WBF_ENCODE(1) | \
  497 + EBC_BXAP_TH_ENCODE(2) | \
  498 + EBC_BXAP_RE_DISABLED | \
  499 + EBC_BXAP_SOR_NONDELAYED | \
  500 + EBC_BXAP_BEM_WRITEONLY | \
  501 + EBC_BXAP_PEN_DISABLED)
  502 +#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
  503 + EBC_BXCR_BS_1MB | \
  504 + EBC_BXCR_BU_RW | \
  505 + EBC_BXCR_BW_16BIT)
  506 +
  507 +/* EBC peripherals */
  508 +
  509 +#define CONFIG_SYS_FPGA_BASE(k) \
  510 + (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
  511 +
  512 +#define CONFIG_SYS_FPGA_DONE(k) \
  513 + (k ? 0x0040 : 0x0080)
  514 +
  515 +#define CONFIG_SYS_FPGA_COUNT 2
  516 +
  517 +#define CONFIG_SYS_LATCH0_RESET 0xffff
  518 +#define CONFIG_SYS_LATCH0_BOOT 0xffff
  519 +#define CONFIG_SYS_LATCH1_RESET 0xffbf
  520 +#define CONFIG_SYS_LATCH1_BOOT 0xffff
  521 +
  522 +/*-----------------------------------------------------------------------
  523 + * GPIO Setup
  524 + *----------------------------------------------------------------------*/
  525 +#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO */ \
  526 +{ \
  527 +/* GPIO Core 0 */ \
  528 +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO0 */ \
  529 +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO1 */ \
  530 +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO2 */ \
  531 +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO3 */ \
  532 +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO4 */ \
  533 +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO5 */ \
  534 +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO6 */ \
  535 +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 */ \
  536 +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO8 */ \
  537 +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO9 */ \
  538 +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO10 */ \
  539 +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO11 */ \
  540 +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO12 */ \
  541 +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO13 */ \
  542 +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO14 */ \
  543 +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO15 */ \
  544 +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO16 */ \
  545 +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO17 */ \
  546 +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO18 */ \
  547 +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO19 */ \
  548 +{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO20 */ \
  549 +{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO21 */ \
  550 +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO22 */ \
  551 +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO23 */ \
  552 +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO24 */ \
  553 +{GPIO0_BASE, GPIO_IN, GPIO_ALT3, GPIO_OUT_0 }, /* GPIO25 */ \
  554 +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO26 */ \
  555 +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO27 */ \
  556 +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO28 */ \
  557 +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO29 */ \
  558 +{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO30 */ \
  559 +{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO31 */ \
  560 +} \
  561 +}
  562 +
  563 +#define CONFIG_SYS_GPIO_STARTUP_FINISHED 15
  564 +#define CONFIG_SYS_GPIO_STARTUP_FINISHED_N 14
  565 +
  566 +#endif /* __CONFIG_H */
include/gdsys_fpga.h
Diff comments   View file @ 255ef4d
... ... @@ -24,9 +24,12 @@
24 24 #ifndef __GDSYS_FPGA_H
25 25 #define __GDSYS_FPGA_H
26 26  
  27 +int init_func_fpga(void);
  28 +
27 29 enum {
28 30 FPGA_STATE_DONE_FAILED = 1 << 0,
29 31 FPGA_STATE_REFLECTION_FAILED = 1 << 1,
  32 + FPGA_STATE_PLATFORM = 1 << 2,
30 33 };
31 34  
32 35 int get_fpga_state(unsigned dev);
... ... @@ -64,6 +67,22 @@
64 67 u16 reserved_0[5]; /* 0x0008 */
65 68 u16 quad_serdes_reset; /* 0x0012 */
66 69 u16 reserved_1[8181]; /* 0x0014 */
  70 + u16 reflection_high; /* 0x3ffe */
  71 +} ihs_fpga_t;
  72 +#endif
  73 +
  74 +#ifdef CONFIG_IO64
  75 +typedef struct ihs_fpga {
  76 + u16 reflection_low; /* 0x0000 */
  77 + u16 versions; /* 0x0002 */
  78 + u16 fpga_features; /* 0x0004 */
  79 + u16 fpga_version; /* 0x0006 */
  80 + u16 reserved_0[5]; /* 0x0008 */
  81 + u16 quad_serdes_reset; /* 0x0012 */
  82 + u16 reserved_1[502]; /* 0x0014 */
  83 + u16 ch0_status_int; /* 0x0400 */
  84 + u16 ch0_config_int; /* 0x0402 */
  85 + u16 reserved_2[7677]; /* 0x0404 */
67 86 u16 reflection_high; /* 0x3ffe */
68 87 } ihs_fpga_t;
69 88 #endif