arm: vf610: fix anadig register struct

The anadig_reg structure started at the wrong offset (fixed by adding reserved_0x000[4]), was missing some reserved field required for alignment purpose (reserved_0x094[3] between pll4_denom and pll6_ctrl) and further contained a too short reserved field causing further miss- alignment (reserved_0x0C4[7]). Also, rename all the reserved fields and using a memory offset based scheme for. Discovered and tested by temporarily putting the following debug instrumentation into board_init(): struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR; printf("&anadig->pll3_ctrl=0x%p\n", &anadig->pll3_ctrl); printf("&anadig->pll5_ctrl=0x%p\n", &anadig->pll5_ctrl); Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> [stefan@agner.ch: regrouped patch] Signed-off-by: Stefan Agner <stefan@agner.ch>

arm: vf610: fix anadig register struct
The anadig_reg structure started at the wrong offset (fixed by adding reserved_0x000[4]), was missing some reserved field required for alignment purpose (reserved_0x094[3] between pll4_denom and pll6_ctrl) and further contained a too short reserved field causing further miss- alignment (reserved_0x0C4[7]). Also, rename all the reserved fields and using a memory offset based scheme for. Discovered and tested by temporarily putting the following debug instrumentation into board_init(): struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR; printf("&anadig->pll3_ctrl=0x%p\n", &anadig->pll3_ctrl); printf("&anadig->pll5_ctrl=0x%p\n", &anadig->pll5_ctrl); Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> [stefan@agner.ch: regrouped patch] Signed-off-by: Stefan Agner <stefan@agner.ch>
Marcel Ziswiler · Albert ARIBAUD
1 parent 42f5e8a25a
Showing 1 changed file with 27 additions and 25 deletions Side-by-side Diff
arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -55,57 +55,59 @@
  
 /* Analog components control digital interface (ANADIG) */
 struct anadig_reg {
+	u32 reserved_0x000[4];
 	u32 pll3_ctrl;
-	u32 resv0[3];
+	u32 reserved_0x014[3];
 	u32 pll7_ctrl;
-	u32 resv1[3];
+	u32 reserved_0x024[3];
 	u32 pll2_ctrl;
-	u32 resv2[3];
+	u32 reserved_0x034[3];
 	u32 pll2_ss;
-	u32 resv3[3];
+	u32 reserved_0x044[3];
 	u32 pll2_num;
-	u32 resv4[3];
+	u32 reserved_0x054[3];
 	u32 pll2_denom;
-	u32 resv5[3];
+	u32 reserved_0x064[3];
 	u32 pll4_ctrl;
-	u32 resv6[3];
+	u32 reserved_0x074[3];
 	u32 pll4_num;
-	u32 resv7[3];
+	u32 reserved_0x084[3];
 	u32 pll4_denom;
+	u32 reserved_0x094[3];
 	u32 pll6_ctrl;
-	u32 resv8[3];
+	u32 reserved_0x0A4[3];
 	u32 pll6_num;
-	u32 resv9[3];
+	u32 reserved_0x0B4[3];
 	u32 pll6_denom;
-	u32 resv10[3];
+	u32 reserved_0x0C4[7];
 	u32 pll5_ctrl;
-	u32 resv11[3];
+	u32 reserved_0x0E4[3];
 	u32 pll3_pfd;
-	u32 resv12[3];
+	u32 reserved_0x0F4[3];
 	u32 pll2_pfd;
-	u32 resv13[3];
+	u32 reserved_0x104[3];
 	u32 reg_1p1;
-	u32 resv14[3];
+	u32 reserved_0x114[3];
 	u32 reg_3p0;
-	u32 resv15[3];
+	u32 reserved_0x124[3];
 	u32 reg_2p5;
-	u32 resv16[7];
+	u32 reserved_0x134[7];
 	u32 ana_misc0;
-	u32 resv17[3];
+	u32 reserved_0x154[3];
 	u32 ana_misc1;
-	u32 resv18[63];
+	u32 reserved_0x164[63];
 	u32 anadig_digprog;
-	u32 resv19[3];
+	u32 reserved_0x264[3];
 	u32 pll1_ctrl;
-	u32 resv20[3];
+	u32 reserved_0x274[3];
 	u32 pll1_ss;
-	u32 resv21[3];
+	u32 reserved_0x284[3];
 	u32 pll1_num;
-	u32 resv22[3];
+	u32 reserved_0x294[3];
 	u32 pll1_denom;
-	u32 resv23[3];
+	u32 reserved_0x2A4[3];
 	u32 pll1_pdf;
-	u32 resv24[3];
+	u32 reserved_0x2B4[3];
 	u32 pll_lock;
 };
 #endif
...	...	@@ -55,57 +55,59 @@
55	55
56	56	/* Analog components control digital interface (ANADIG) */
57	57	struct anadig_reg {
	58	+ u32 reserved_0x000[4];
58	59	u32 pll3_ctrl;
59		- u32 resv0[3];
	60	+ u32 reserved_0x014[3];
60	61	u32 pll7_ctrl;
61		- u32 resv1[3];
	62	+ u32 reserved_0x024[3];
62	63	u32 pll2_ctrl;
63		- u32 resv2[3];
	64	+ u32 reserved_0x034[3];
64	65	u32 pll2_ss;
65		- u32 resv3[3];
	66	+ u32 reserved_0x044[3];
66	67	u32 pll2_num;
67		- u32 resv4[3];
	68	+ u32 reserved_0x054[3];
68	69	u32 pll2_denom;
69		- u32 resv5[3];
	70	+ u32 reserved_0x064[3];
70	71	u32 pll4_ctrl;
71		- u32 resv6[3];
	72	+ u32 reserved_0x074[3];
72	73	u32 pll4_num;
73		- u32 resv7[3];
	74	+ u32 reserved_0x084[3];
74	75	u32 pll4_denom;
	76	+ u32 reserved_0x094[3];
75	77	u32 pll6_ctrl;
76		- u32 resv8[3];
	78	+ u32 reserved_0x0A4[3];
77	79	u32 pll6_num;
78		- u32 resv9[3];
	80	+ u32 reserved_0x0B4[3];
79	81	u32 pll6_denom;
80		- u32 resv10[3];
	82	+ u32 reserved_0x0C4[7];
81	83	u32 pll5_ctrl;
82		- u32 resv11[3];
	84	+ u32 reserved_0x0E4[3];
83	85	u32 pll3_pfd;
84		- u32 resv12[3];
	86	+ u32 reserved_0x0F4[3];
85	87	u32 pll2_pfd;
86		- u32 resv13[3];
	88	+ u32 reserved_0x104[3];
87	89	u32 reg_1p1;
88		- u32 resv14[3];
	90	+ u32 reserved_0x114[3];
89	91	u32 reg_3p0;
90		- u32 resv15[3];
	92	+ u32 reserved_0x124[3];
91	93	u32 reg_2p5;
92		- u32 resv16[7];
	94	+ u32 reserved_0x134[7];
93	95	u32 ana_misc0;
94		- u32 resv17[3];
	96	+ u32 reserved_0x154[3];
95	97	u32 ana_misc1;
96		- u32 resv18[63];
	98	+ u32 reserved_0x164[63];
97	99	u32 anadig_digprog;
98		- u32 resv19[3];
	100	+ u32 reserved_0x264[3];
99	101	u32 pll1_ctrl;
100		- u32 resv20[3];
	102	+ u32 reserved_0x274[3];
101	103	u32 pll1_ss;
102		- u32 resv21[3];
	104	+ u32 reserved_0x284[3];
103	105	u32 pll1_num;
104		- u32 resv22[3];
	106	+ u32 reserved_0x294[3];
105	107	u32 pll1_denom;
106		- u32 resv23[3];
	108	+ u32 reserved_0x2A4[3];
107	109	u32 pll1_pdf;
108		- u32 resv24[3];
	110	+ u32 reserved_0x2B4[3];
109	111	u32 pll_lock;
110	112	};
111	113	#endif