Commit 25b0a729aa5f771edb277f2ef9cfd9b737ec0e9e
Committed by
Tom Rini
Tom Rini
1 parent
ccd2f8db81
Exists in
v2017.01-smarct4x
and in
40 other branches
arch-am33xx: Add defines for timer0-7
For usage of timer6 within B&R we need this defines to enable clock modules and clk-source. Also the 'Timer register bits' are expanded. By the way we add defines for all timers within AM335x SoC. Cc: trini@ti.com Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
Showing 1 changed file with 29 additions and 6 deletions Side-by-side Diff
arch/arm/include/asm/arch-am33xx/cpu.h
| ... | ... | @@ -26,7 +26,17 @@ |
| 26 | 26 | #define TCLR_PRE BIT(5) /* Pre-scaler enable */ |
| 27 | 27 | #define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */ |
| 28 | 28 | #define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */ |
| 29 | +#define TCLR_CE BIT(6) /* compare mode enable */ | |
| 30 | +#define TCLR_SCPWM BIT(7) /* pwm outpin behaviour */ | |
| 31 | +#define TCLR_TCM BIT(8) /* edge detection of input pin*/ | |
| 32 | +#define TCLR_TRG_SHIFT (10) /* trigmode on pwm outpin */ | |
| 33 | +#define TCLR_PT BIT(12) /* pulse/toggle mode of outpin*/ | |
| 34 | +#define TCLR_CAPTMODE BIT(13) /* capture mode */ | |
| 35 | +#define TCLR_GPOCFG BIT(14) /* 0=output,1=input */ | |
| 29 | 36 | |
| 37 | +#define TCFG_RESET BIT(0) /* software reset */ | |
| 38 | +#define TCFG_EMUFREE BIT(1) /* behaviour of tmr on debug */ | |
| 39 | +#define TCFG_IDLEMOD_SHIFT (2) /* power management */ | |
| 30 | 40 | /* device type */ |
| 31 | 41 | #define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10)) |
| 32 | 42 | #define TST_DEVICE 0x0 |
| ... | ... | @@ -87,7 +97,8 @@ |
| 87 | 97 | unsigned int wkctrlclkctrl; /* offset 0x04 */ |
| 88 | 98 | unsigned int wkgpio0clkctrl; /* offset 0x08 */ |
| 89 | 99 | unsigned int wkl4wkclkctrl; /* offset 0x0c */ |
| 90 | - unsigned int resv2[4]; | |
| 100 | + unsigned int timer0clkctrl; /* offset 0x10 */ | |
| 101 | + unsigned int resv2[3]; | |
| 91 | 102 | unsigned int idlestdpllmpu; /* offset 0x20 */ |
| 92 | 103 | unsigned int resv3[2]; |
| 93 | 104 | unsigned int clkseldpllmpu; /* offset 0x2c */ |
| ... | ... | @@ -121,7 +132,9 @@ |
| 121 | 132 | unsigned int wkup_uart0ctrl; /* offset 0xB4 */ |
| 122 | 133 | unsigned int wkup_i2c0ctrl; /* offset 0xB8 */ |
| 123 | 134 | unsigned int wkup_adctscctrl; /* offset 0xBC */ |
| 124 | - unsigned int resv12[6]; | |
| 135 | + unsigned int resv12; | |
| 136 | + unsigned int timer1clkctrl; /* offset 0xC4 */ | |
| 137 | + unsigned int resv13[4]; | |
| 125 | 138 | unsigned int divm6dpllcore; /* offset 0xD8 */ |
| 126 | 139 | }; |
| 127 | 140 | |
| ... | ... | @@ -178,7 +191,9 @@ |
| 178 | 191 | unsigned int epwmss2clkctrl; /* offset 0xD8 */ |
| 179 | 192 | unsigned int l3instrclkctrl; /* offset 0xDC */ |
| 180 | 193 | unsigned int l3clkctrl; /* Offset 0xE0 */ |
| 181 | - unsigned int resv8[4]; | |
| 194 | + unsigned int resv8[2]; | |
| 195 | + unsigned int timer5clkctrl; /* offset 0xEC */ | |
| 196 | + unsigned int timer6clkctrl; /* offset 0xF0 */ | |
| 182 | 197 | unsigned int mmc1clkctrl; /* offset 0xF4 */ |
| 183 | 198 | unsigned int mmc2clkctrl; /* offset 0xF8 */ |
| 184 | 199 | unsigned int resv9[8]; |
| 185 | 200 | |
| ... | ... | @@ -191,9 +206,17 @@ |
| 191 | 206 | |
| 192 | 207 | /* Encapsulating Display pll registers */ |
| 193 | 208 | struct cm_dpll { |
| 194 | - unsigned int resv1[2]; | |
| 209 | + unsigned int resv1; | |
| 210 | + unsigned int clktimer7clk; /* offset 0x04 */ | |
| 195 | 211 | unsigned int clktimer2clk; /* offset 0x08 */ |
| 196 | - unsigned int resv2[10]; | |
| 212 | + unsigned int clktimer3clk; /* offset 0x0C */ | |
| 213 | + unsigned int clktimer4clk; /* offset 0x10 */ | |
| 214 | + unsigned int resv2; | |
| 215 | + unsigned int clktimer5clk; /* offset 0x18 */ | |
| 216 | + unsigned int clktimer6clk; /* offset 0x1C */ | |
| 217 | + unsigned int resv3[2]; | |
| 218 | + unsigned int clktimer1clk; /* offset 0x28 */ | |
| 219 | + unsigned int resv4[2]; | |
| 197 | 220 | unsigned int clklcdcpixelclk; /* offset 0x34 */ |
| 198 | 221 | }; |
| 199 | 222 | #else |