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Commit 2661dfd0046285e9007c1de126255bee11c0b8cd

Authored by Masahiro Yamada
1 parent 5e165b258f
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

ARM: UniPhier: enable output of system bus 

For NAND boot on PH1-LD4, PH1-sLD8, and some other SoCs,
the output of the system bus is disabled by default.
It must be enabled by software to have access to the system bus.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Showing 3 changed files with 15 additions and 0 deletions Inline Diff

arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c
Diff comments   View file @ 2661dfd
1 /* 1 /*
2 * Copyright (C) 2011-2014 Panasonic Corporation 2 * Copyright (C) 2011-2014 Panasonic Corporation
3 * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> 3 * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #include <common.h> 8 #include <common.h>
9 #include <asm/io.h> 9 #include <asm/io.h>
10 #include <asm/arch/sbc-regs.h> 10 #include <asm/arch/sbc-regs.h>
11 #include <asm/arch/sg-regs.h> 11 #include <asm/arch/sg-regs.h>
12 12
13 void sbc_init(void) 13 void sbc_init(void)
14 { 14 {
15 u32 tmp;
16
17 /* system bus output enable */
18 tmp = readl(PC0CTRL);
19 tmp &= 0xfffffcff;
20 writel(tmp, PC0CTRL);
21
15 /* XECS1: sub/boot memory (boot swap = off/on) */ 22 /* XECS1: sub/boot memory (boot swap = off/on) */
16 writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10); 23 writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
17 writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11); 24 writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
18 writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12); 25 writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
19 writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14); 26 writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
20 27
21 #if !defined(CONFIG_SPL_BUILD) 28 #if !defined(CONFIG_SPL_BUILD)
22 /* XECS0: boot/sub memory (boot swap = off/on) */ 29 /* XECS0: boot/sub memory (boot swap = off/on) */
23 writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00); 30 writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
24 writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01); 31 writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
25 writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02); 32 writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
26 writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04); 33 writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
27 #endif 34 #endif
28 /* XECS3: peripherals */ 35 /* XECS3: peripherals */
29 writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30); 36 writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
30 writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31); 37 writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
31 writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32); 38 writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
32 writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34); 39 writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
33 40
34 /* base address regsiters */ 41 /* base address regsiters */
35 writel(0x0000bc01, SBBASE0); 42 writel(0x0000bc01, SBBASE0);
36 writel(0x0400bc01, SBBASE1); 43 writel(0x0400bc01, SBBASE1);
37 writel(0x0800bf01, SBBASE3); 44 writel(0x0800bf01, SBBASE3);
38 45
39 #if !defined(CONFIG_SPL_BUILD) 46 #if !defined(CONFIG_SPL_BUILD)
40 /* enable access to sub memory when boot swap is on */ 47 /* enable access to sub memory when boot swap is on */
41 sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */ 48 sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */
42 #endif 49 #endif
43 sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */ 50 sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */
44 } 51 }
45 52
arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c
Diff comments   View file @ 2661dfd
1 /* 1 /*
2 * Copyright (C) 2011-2014 Panasonic Corporation 2 * Copyright (C) 2011-2014 Panasonic Corporation
3 * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> 3 * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #include <common.h> 8 #include <common.h>
9 #include <asm/io.h> 9 #include <asm/io.h>
10 #include <asm/arch/sbc-regs.h> 10 #include <asm/arch/sbc-regs.h>
11 #include <asm/arch/sg-regs.h> 11 #include <asm/arch/sg-regs.h>
12 12
13 void sbc_init(void) 13 void sbc_init(void)
14 { 14 {
15 u32 tmp;
16
17 /* system bus output enable */
18 tmp = readl(PC0CTRL);
19 tmp &= 0xfffffcff;
20 writel(tmp, PC0CTRL);
21
15 #if !defined(CONFIG_SPL_BUILD) 22 #if !defined(CONFIG_SPL_BUILD)
16 /* XECS0 : dummy */ 23 /* XECS0 : dummy */
17 writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00); 24 writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
18 writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01); 25 writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
19 writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02); 26 writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
20 writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04); 27 writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
21 #endif 28 #endif
22 /* XECS1 : boot memory (always boot swap = on) */ 29 /* XECS1 : boot memory (always boot swap = on) */
23 writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10); 30 writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
24 writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11); 31 writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
25 writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12); 32 writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
26 writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14); 33 writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
27 34
28 /* XECS4 : sub memory */ 35 /* XECS4 : sub memory */
29 writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40); 36 writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40);
30 writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL41); 37 writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL41);
31 writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL42); 38 writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL42);
32 writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL44); 39 writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL44);
33 40
34 /* XECS5 : peripherals */ 41 /* XECS5 : peripherals */
35 writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL50); 42 writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL50);
36 writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL51); 43 writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL51);
37 writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL52); 44 writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL52);
38 writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL54); 45 writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL54);
39 46
40 /* base address regsiters */ 47 /* base address regsiters */
41 writel(0x0000bc01, SBBASE0); /* boot memory */ 48 writel(0x0000bc01, SBBASE0); /* boot memory */
42 writel(0x0900bfff, SBBASE1); /* dummy */ 49 writel(0x0900bfff, SBBASE1); /* dummy */
43 writel(0x0400bc01, SBBASE4); /* sub memory */ 50 writel(0x0400bc01, SBBASE4); /* sub memory */
44 writel(0x0800bf01, SBBASE5); /* peripherals */ 51 writel(0x0800bf01, SBBASE5); /* peripherals */
45 52
46 sg_set_pinsel(134, 16); /* XIRQ6 -> XECS4 */ 53 sg_set_pinsel(134, 16); /* XIRQ6 -> XECS4 */
47 sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */ 54 sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */
48 55
49 /* dummy read to assure write process */ 56 /* dummy read to assure write process */
50 readl(SG_PINCTRL(33)); 57 readl(SG_PINCTRL(33));
51 } 58 }
52 59
arch/arm/include/asm/arch-uniphier/sbc-regs.h
Diff comments   View file @ 2661dfd
1 /* 1 /*
2 * UniPhier SBC (System Bus Controller) registers 2 * UniPhier SBC (System Bus Controller) registers
3 * 3 *
4 * Copyright (C) 2011-2014 Panasonic Corporation 4 * Copyright (C) 2011-2014 Panasonic Corporation
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0+ 6 * SPDX-License-Identifier: GPL-2.0+
7 */ 7 */
8 8
9 #ifndef ARCH_SBC_REGS_H 9 #ifndef ARCH_SBC_REGS_H
10 #define ARCH_SBC_REGS_H 10 #define ARCH_SBC_REGS_H
11 11
12 #define SBBASE_BASE 0x58c00100 12 #define SBBASE_BASE 0x58c00100
13 #define SBBASE(x) (SBBASE_BASE + (x) * 0x10) 13 #define SBBASE(x) (SBBASE_BASE + (x) * 0x10)
14 14
15 #define SBBASE0 (SBBASE(0)) 15 #define SBBASE0 (SBBASE(0))
16 #define SBBASE1 (SBBASE(1)) 16 #define SBBASE1 (SBBASE(1))
17 #define SBBASE2 (SBBASE(2)) 17 #define SBBASE2 (SBBASE(2))
18 #define SBBASE3 (SBBASE(3)) 18 #define SBBASE3 (SBBASE(3))
19 #define SBBASE4 (SBBASE(4)) 19 #define SBBASE4 (SBBASE(4))
20 #define SBBASE5 (SBBASE(5)) 20 #define SBBASE5 (SBBASE(5))
21 #define SBBASE6 (SBBASE(6)) 21 #define SBBASE6 (SBBASE(6))
22 #define SBBASE7 (SBBASE(7)) 22 #define SBBASE7 (SBBASE(7))
23 23
24 #define SBBASE_BANK_ENABLE (0x00000001) 24 #define SBBASE_BANK_ENABLE (0x00000001)
25 25
26 #define SBCTRL_BASE 0x58c00200 26 #define SBCTRL_BASE 0x58c00200
27 #define SBCTRL(x, y) (SBCTRL_BASE + (x) * 0x10 + (y) * 4) 27 #define SBCTRL(x, y) (SBCTRL_BASE + (x) * 0x10 + (y) * 4)
28 28
29 #define SBCTRL00 SBCTRL(0, 0) 29 #define SBCTRL00 SBCTRL(0, 0)
30 #define SBCTRL01 SBCTRL(0, 1) 30 #define SBCTRL01 SBCTRL(0, 1)
31 #define SBCTRL02 SBCTRL(0, 2) 31 #define SBCTRL02 SBCTRL(0, 2)
32 #define SBCTRL03 SBCTRL(0, 3) 32 #define SBCTRL03 SBCTRL(0, 3)
33 #define SBCTRL04 (SBCTRL_BASE + 0x100) 33 #define SBCTRL04 (SBCTRL_BASE + 0x100)
34 34
35 #define SBCTRL10 SBCTRL(1, 0) 35 #define SBCTRL10 SBCTRL(1, 0)
36 #define SBCTRL11 SBCTRL(1, 1) 36 #define SBCTRL11 SBCTRL(1, 1)
37 #define SBCTRL12 SBCTRL(1, 2) 37 #define SBCTRL12 SBCTRL(1, 2)
38 #define SBCTRL13 SBCTRL(1, 3) 38 #define SBCTRL13 SBCTRL(1, 3)
39 #define SBCTRL14 (SBCTRL_BASE + 0x110) 39 #define SBCTRL14 (SBCTRL_BASE + 0x110)
40 40
41 #define SBCTRL20 SBCTRL(2, 0) 41 #define SBCTRL20 SBCTRL(2, 0)
42 #define SBCTRL21 SBCTRL(2, 1) 42 #define SBCTRL21 SBCTRL(2, 1)
43 #define SBCTRL22 SBCTRL(2, 2) 43 #define SBCTRL22 SBCTRL(2, 2)
44 #define SBCTRL23 SBCTRL(2, 3) 44 #define SBCTRL23 SBCTRL(2, 3)
45 #define SBCTRL24 (SBCTRL_BASE + 0x120) 45 #define SBCTRL24 (SBCTRL_BASE + 0x120)
46 46
47 #define SBCTRL30 SBCTRL(3, 0) 47 #define SBCTRL30 SBCTRL(3, 0)
48 #define SBCTRL31 SBCTRL(3, 1) 48 #define SBCTRL31 SBCTRL(3, 1)
49 #define SBCTRL32 SBCTRL(3, 2) 49 #define SBCTRL32 SBCTRL(3, 2)
50 #define SBCTRL33 SBCTRL(3, 3) 50 #define SBCTRL33 SBCTRL(3, 3)
51 #define SBCTRL34 (SBCTRL_BASE + 0x130) 51 #define SBCTRL34 (SBCTRL_BASE + 0x130)
52 52
53 #define SBCTRL40 SBCTRL(4, 0) 53 #define SBCTRL40 SBCTRL(4, 0)
54 #define SBCTRL41 SBCTRL(4, 1) 54 #define SBCTRL41 SBCTRL(4, 1)
55 #define SBCTRL42 SBCTRL(4, 2) 55 #define SBCTRL42 SBCTRL(4, 2)
56 #define SBCTRL43 SBCTRL(4, 3) 56 #define SBCTRL43 SBCTRL(4, 3)
57 #define SBCTRL44 (SBCTRL_BASE + 0x140) 57 #define SBCTRL44 (SBCTRL_BASE + 0x140)
58 58
59 #define SBCTRL50 SBCTRL(5, 0) 59 #define SBCTRL50 SBCTRL(5, 0)
60 #define SBCTRL51 SBCTRL(5, 1) 60 #define SBCTRL51 SBCTRL(5, 1)
61 #define SBCTRL52 SBCTRL(5, 2) 61 #define SBCTRL52 SBCTRL(5, 2)
62 #define SBCTRL53 SBCTRL(5, 3) 62 #define SBCTRL53 SBCTRL(5, 3)
63 #define SBCTRL54 (SBCTRL_BASE + 0x150) 63 #define SBCTRL54 (SBCTRL_BASE + 0x150)
64 64
65 #define SBCTRL60 SBCTRL(6, 0) 65 #define SBCTRL60 SBCTRL(6, 0)
66 #define SBCTRL61 SBCTRL(6, 1) 66 #define SBCTRL61 SBCTRL(6, 1)
67 #define SBCTRL62 SBCTRL(6, 2) 67 #define SBCTRL62 SBCTRL(6, 2)
68 #define SBCTRL63 SBCTRL(6, 3) 68 #define SBCTRL63 SBCTRL(6, 3)
69 #define SBCTRL64 (SBCTRL_BASE + 0x160) 69 #define SBCTRL64 (SBCTRL_BASE + 0x160)
70 70
71 #define SBCTRL70 SBCTRL(7, 0) 71 #define SBCTRL70 SBCTRL(7, 0)
72 #define SBCTRL71 SBCTRL(7, 1) 72 #define SBCTRL71 SBCTRL(7, 1)
73 #define SBCTRL72 SBCTRL(7, 2) 73 #define SBCTRL72 SBCTRL(7, 2)
74 #define SBCTRL73 SBCTRL(7, 3) 74 #define SBCTRL73 SBCTRL(7, 3)
75 #define SBCTRL74 (SBCTRL_BASE + 0x170) 75 #define SBCTRL74 (SBCTRL_BASE + 0x170)
76 76
77 /* slower but LED works */ 77 /* slower but LED works */
78 #define SBCTRL0_SAVEPIN_PERI_VALUE 0x55450000 78 #define SBCTRL0_SAVEPIN_PERI_VALUE 0x55450000
79 #define SBCTRL1_SAVEPIN_PERI_VALUE 0x07168d00 79 #define SBCTRL1_SAVEPIN_PERI_VALUE 0x07168d00
80 #define SBCTRL2_SAVEPIN_PERI_VALUE 0x34000009 80 #define SBCTRL2_SAVEPIN_PERI_VALUE 0x34000009
81 #define SBCTRL4_SAVEPIN_PERI_VALUE 0x02110110 81 #define SBCTRL4_SAVEPIN_PERI_VALUE 0x02110110
82 82
83 /* faster but LED does not work */ 83 /* faster but LED does not work */
84 #define SBCTRL0_SAVEPIN_MEM_VALUE 0x55450000 84 #define SBCTRL0_SAVEPIN_MEM_VALUE 0x55450000
85 #define SBCTRL1_SAVEPIN_MEM_VALUE 0x06057700 85 #define SBCTRL1_SAVEPIN_MEM_VALUE 0x06057700
86 /* NOR flash needs more wait counts than SRAM */ 86 /* NOR flash needs more wait counts than SRAM */
87 #define SBCTRL2_SAVEPIN_MEM_VALUE 0x34000009 87 #define SBCTRL2_SAVEPIN_MEM_VALUE 0x34000009
88 #define SBCTRL4_SAVEPIN_MEM_VALUE 0x02110210 88 #define SBCTRL4_SAVEPIN_MEM_VALUE 0x02110210
89 89
90 #define SBCTRL0_ADMULTIPLX_PERI_VALUE 0x33120000 90 #define SBCTRL0_ADMULTIPLX_PERI_VALUE 0x33120000
91 #define SBCTRL1_ADMULTIPLX_PERI_VALUE 0x03005500 91 #define SBCTRL1_ADMULTIPLX_PERI_VALUE 0x03005500
92 #define SBCTRL2_ADMULTIPLX_PERI_VALUE 0x14000020 92 #define SBCTRL2_ADMULTIPLX_PERI_VALUE 0x14000020
93 93
94 #define SBCTRL0_ADMULTIPLX_MEM_VALUE 0x33120000 94 #define SBCTRL0_ADMULTIPLX_MEM_VALUE 0x33120000
95 #define SBCTRL1_ADMULTIPLX_MEM_VALUE 0x03005500 95 #define SBCTRL1_ADMULTIPLX_MEM_VALUE 0x03005500
96 #define SBCTRL2_ADMULTIPLX_MEM_VALUE 0x14000010 96 #define SBCTRL2_ADMULTIPLX_MEM_VALUE 0x14000010
97 97
98 #define PC0CTRL 0x598000c0
98 #define ROM_BOOT_ROMRSV2 0x59801208 99 #define ROM_BOOT_ROMRSV2 0x59801208
99 100
100 #ifndef __ASSEMBLY__ 101 #ifndef __ASSEMBLY__
101 #include <asm/io.h> 102 #include <asm/io.h>
102 static inline int boot_is_swapped(void) 103 static inline int boot_is_swapped(void)
103 { 104 {
104 return !(readl(SBBASE0) & SBBASE_BANK_ENABLE); 105 return !(readl(SBBASE0) & SBBASE_BANK_ENABLE);
105 } 106 }
106 #endif 107 #endif
107 108
108 #endif /* ARCH_SBC_REGS_H */ 109 #endif /* ARCH_SBC_REGS_H */
109 110