Commit 26ad30e9d3ec445f61f94910fb14cc6e7d8efa25
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rockchip: Add basic peripheral and clock definitions
Add header files for the peripherals and clocks supported on Rockchip platforms. The particular implementation (and register set) for each is SoC-specific, but it seems that the naming can be generic. Signed-off-by: Simon Glass <sjg@chromium.org>
Showing 3 changed files with 119 additions and 0 deletions Side-by-side Diff
arch/arm/include/asm/arch-rockchip/clock.h
| 1 | +/* | |
| 2 | + * (C) Copyright 2015 Google, Inc | |
| 3 | + * | |
| 4 | + * SPDX-License-Identifier: GPL-2.0 | |
| 5 | + */ | |
| 6 | + | |
| 7 | +#ifndef _ASM_ARCH_CLOCK_H | |
| 8 | +#define _ASM_ARCH_CLOCK_H | |
| 9 | + | |
| 10 | +/* define pll mode */ | |
| 11 | +#define RKCLK_PLL_MODE_SLOW 0 | |
| 12 | +#define RKCLK_PLL_MODE_NORMAL 1 | |
| 13 | + | |
| 14 | +enum { | |
| 15 | + ROCKCHIP_SYSCON_NOC, | |
| 16 | + ROCKCHIP_SYSCON_GRF, | |
| 17 | + ROCKCHIP_SYSCON_SGRF, | |
| 18 | + ROCKCHIP_SYSCON_PMU, | |
| 19 | +}; | |
| 20 | + | |
| 21 | +/* Standard Rockchip clock numbers */ | |
| 22 | +enum rk_clk_id { | |
| 23 | + CLK_OSC, | |
| 24 | + CLK_ARM, | |
| 25 | + CLK_DDR, | |
| 26 | + CLK_CODEC, | |
| 27 | + CLK_GENERAL, | |
| 28 | + CLK_NEW, | |
| 29 | + | |
| 30 | + CLK_COUNT, | |
| 31 | +}; | |
| 32 | + | |
| 33 | +static inline int rk_pll_id(enum rk_clk_id clk_id) | |
| 34 | +{ | |
| 35 | + return clk_id - 1; | |
| 36 | +} | |
| 37 | + | |
| 38 | +/** | |
| 39 | + * rockchip_get_cru() - get a pointer to the clock/reset unit registers | |
| 40 | + * | |
| 41 | + * @return pointer to registers, or -ve error on error | |
| 42 | + */ | |
| 43 | +void *rockchip_get_cru(void); | |
| 44 | + | |
| 45 | +#endif |
arch/arm/include/asm/arch-rockchip/hardware.h
| 1 | +/* | |
| 2 | + * Copyright 2015 Google, Inc | |
| 3 | + * | |
| 4 | + * SPDX-License-Identifier: GPL-2.0+ | |
| 5 | + */ | |
| 6 | + | |
| 7 | +#ifndef _ASM_ARCH_HARDWARE_H | |
| 8 | +#define _ASM_ARCH_HARDWARE_H | |
| 9 | + | |
| 10 | +#define RK_CLRSETBITS(clr, set) ((((clr) | (set)) << 16) | set) | |
| 11 | +#define RK_SETBITS(set) RK_CLRSETBITS(0, set) | |
| 12 | +#define RK_CLRBITS(clr) RK_CLRSETBITS(clr, 0) | |
| 13 | + | |
| 14 | +#define TIMER7_BASE 0xff810020 | |
| 15 | + | |
| 16 | +#define rk_clrsetreg(addr, clr, set) writel((clr) << 16 | (set), addr) | |
| 17 | +#define rk_clrreg(addr, clr) writel((clr) << 16, addr) | |
| 18 | +#define rk_setreg(addr, set) writel(set, addr) | |
| 19 | + | |
| 20 | +#endif |
arch/arm/include/asm/arch-rockchip/periph.h
| 1 | +/* | |
| 2 | + * (C) Copyright 2015 Google, Inc | |
| 3 | + * | |
| 4 | + * SPDX-License-Identifier: GPL-2.0 | |
| 5 | + */ | |
| 6 | + | |
| 7 | +#ifndef _ASM_ARCH_PERIPH_H | |
| 8 | +#define _ASM_ARCH_PERIPH_H | |
| 9 | + | |
| 10 | +/* | |
| 11 | + * The peripherals supported by the hardware. This is used to specify clocks | |
| 12 | + * and pinctrl settings. Some SoCs will not support all of these, but it | |
| 13 | + * provides a common reference for common drivers to use. | |
| 14 | + */ | |
| 15 | +enum periph_id { | |
| 16 | + PERIPH_ID_PWM0, | |
| 17 | + PERIPH_ID_PWM1, | |
| 18 | + PERIPH_ID_PWM2, | |
| 19 | + PERIPH_ID_PWM3, | |
| 20 | + PERIPH_ID_PWM4, | |
| 21 | + PERIPH_ID_I2C0, | |
| 22 | + PERIPH_ID_I2C1, | |
| 23 | + PERIPH_ID_I2C2, | |
| 24 | + PERIPH_ID_I2C3, | |
| 25 | + PERIPH_ID_I2C4, | |
| 26 | + PERIPH_ID_I2C5, | |
| 27 | + PERIPH_ID_SPI0, | |
| 28 | + PERIPH_ID_SPI1, | |
| 29 | + PERIPH_ID_SPI2, | |
| 30 | + PERIPH_ID_UART0, | |
| 31 | + PERIPH_ID_UART1, | |
| 32 | + PERIPH_ID_UART2, | |
| 33 | + PERIPH_ID_UART3, | |
| 34 | + PERIPH_ID_UART4, | |
| 35 | + PERIPH_ID_LCDC0, | |
| 36 | + PERIPH_ID_LCDC1, | |
| 37 | + PERIPH_ID_SDMMC0, | |
| 38 | + PERIPH_ID_SDMMC1, | |
| 39 | + PERIPH_ID_SDMMC2, | |
| 40 | + PERIPH_ID_HDMI, | |
| 41 | + | |
| 42 | + PERIPH_ID_COUNT, | |
| 43 | + | |
| 44 | + /* Some aliases */ | |
| 45 | + PERIPH_ID_EMMC = PERIPH_ID_SDMMC0, | |
| 46 | + PERIPH_ID_SDCARD = PERIPH_ID_SDMMC1, | |
| 47 | + PERIPH_ID_UART_BT = PERIPH_ID_UART0, | |
| 48 | + PERIPH_ID_UART_BB = PERIPH_ID_UART1, | |
| 49 | + PERIPH_ID_UART_DBG = PERIPH_ID_UART2, | |
| 50 | + PERIPH_ID_UART_GPS = PERIPH_ID_UART3, | |
| 51 | + PERIPH_ID_UART_EXP = PERIPH_ID_UART4, | |
| 52 | +}; | |
| 53 | + | |
| 54 | +#endif |