ppc4xx: Fix FDT EBC mappings on Canyonlands

This patch fixes 2 problems with FDT EBC mappings on Canyonlands. First, NAND EBC mapping was missing, making Linux NAND driver unusable on this board. Second, NOR remapping code assumed that NOR is always on CS0, however when booting from NAND NOR is on CS3. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Stefan Roese <sr@denx.de>

ppc4xx: Fix FDT EBC mappings on Canyonlands
This patch fixes 2 problems with FDT EBC mappings on Canyonlands. First, NAND EBC mapping was missing, making Linux NAND driver unusable on this board. Second, NOR remapping code assumed that NOR is always on CS0, however when booting from NAND NOR is on CS3. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Stefan Roese <sr@denx.de>
Felix Radensky · Stefan Roese
1 parent 59869ca72d
Showing 2 changed files with 6 additions and 2 deletions Side-by-side Diff
board/amcc/canyonlands/canyonlands.c
include/configs/canyonlands.h
@@ -575,15 +575,17 @@
 #endif	/* !defined(CONFIG_ARCHES) */
  
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+extern void __ft_board_setup(void *blob, bd_t *bd);
+
 void ft_board_setup(void *blob, bd_t *bd)
 {
 	u32 val[4];
 	int rc;
  
-	ft_cpu_setup(blob, bd);
+	__ft_board_setup(blob, bd);
  
 	/* Fixup NOR mapping */
-	val[0] = 0;				/* chip select number */
+	val[0] = CONFIG_SYS_NOR_CS;		/* chip select number */
 	val[1] = 0;				/* always 0 */
 	val[2] = CONFIG_SYS_FLASH_BASE_PHYS_L;		/* we fixed up this address */
 	val[3] = gd->bd->bi_flashsize;
@@ -132,9 +132,11 @@
  */
 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define	CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
+#define CONFIG_SYS_NOR_CS		0	/* NOR chip connected to CSx */
 #define CONFIG_SYS_NAND_CS		3	/* NAND chip connected to CSx */
 #else
 #define	CONFIG_ENV_IS_IN_NAND	1	/* use NAND for environment vars  */
+#define CONFIG_SYS_NOR_CS		3	/* NOR chip connected to CSx */
 #define CONFIG_SYS_NAND_CS		0	/* NAND chip connected to CSx */
 #define CONFIG_ENV_IS_EMBEDDED	1	/* use embedded environment */
 #endif
...	...	@@ -575,15 +575,17 @@
575	575	#endif /* !defined(CONFIG_ARCHES) */
576	576
577	577	#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
	578	+extern void __ft_board_setup(void blob, bd_t bd);
	579	+
578	580	void ft_board_setup(void blob, bd_t bd)
579	581	{
580	582	u32 val[4];
581	583	int rc;
582	584
583		- ft_cpu_setup(blob, bd);
	585	+ __ft_board_setup(blob, bd);
584	586
585	587	/* Fixup NOR mapping */
586		- val[0] = 0; /* chip select number */
	588	+ val[0] = CONFIG_SYS_NOR_CS; /* chip select number */
587	589	val[1] = 0; /* always 0 */
588	590	val[2] = CONFIG_SYS_FLASH_BASE_PHYS_L; /* we fixed up this address */
589	591	val[3] = gd->bd->bi_flashsize;
...	...	@@ -132,9 +132,11 @@
132	132	*/
133	133	#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
134	134	#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
	135	+#define CONFIG_SYS_NOR_CS 0 /* NOR chip connected to CSx */
135	136	#define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */
136	137	#else
137	138	#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
	139	+#define CONFIG_SYS_NOR_CS 3 /* NOR chip connected to CSx */
138	140	#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
139	141	#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
140	142	#endif