Eric Lee / smarc-uboot

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Commit 282a82e8a10ce6ef132d7a809101fdaed951001c

Authored by Sonic Zhang
Committed by Pantelis Antoniou
1 parent be9f643ae6
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

mmc: set correct block size value in bfin sdh driver 

Wait data transfer till the data end bit other than the data block end
bit is set.

Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>

Showing 1 changed file with 4 additions and 3 deletions Side-by-side Diff

drivers/mmc/bfin_sdh.c
Diff comments   View file @ 282a82e
... ... @@ -138,9 +138,9 @@
138 138 if (data->flags & MMC_DATA_WRITE)
139 139 return UNUSABLE_ERR;
140 140 #ifndef RSI_BLKSZ
141   - data_ctl |= ((ffs(data_size) - 1) << 4);
  141 + data_ctl |= ((ffs(data->blocksize) - 1) << 4);
142 142 #else
143   - bfin_write_SDH_BLK_SIZE(data_size);
  143 + bfin_write_SDH_BLK_SIZE(data->blocksize);
144 144 #endif
145 145 data_ctl |= DTX_DIR;
146 146 bfin_write_SDH_DATA_CTL(data_ctl);
... ... @@ -189,7 +189,8 @@
189 189 do {
190 190 udelay(1);
191 191 status = bfin_read_SDH_STATUS();
192   - } while (!(status & (DAT_BLK_END | DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN)));
  192 + } while (!(status & (DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL |
  193 + RX_OVERRUN)));
193 194  
194 195 if (status & DAT_TIME_OUT) {
195 196 bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT);