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Commit 2868f8625f0bdd8dda6895b119d09a43d1f10c82

Authored by Masahiro Yamada
Committed by Tom Rini
1 parent 49ad566dfa
Exists in v2017.01-smarct4x and in 40 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

powerpc: kvme080: remove orphan board 

This board has been orphan for a while.
(Emails to its maintainer have been bouncing.)

Because MPC82xx family is old enough, nobody would pick up
the maintainership on it.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denx <wd@denx.de>

Showing 7 changed files with 1 additions and 801 deletions Side-by-side Diff

board/etin/kvme080/Makefile
View file @ 2868f86
1   -#
2   -# (C) Copyright 2000-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -obj-y = kvme080.o multiverse.o
board/etin/kvme080/kvme080.c
View file @ 2868f86
1   -/*
2   - * (C) Copyright 2005
3   - * Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -#include <mpc824x.h>
10   -#include <pci.h>
11   -#include <i2c.h>
12   -#include <netdev.h>
13   -#include <asm/processor.h>
14   -#include <asm/mmu.h>
15   -
16   -int checkboard(void)
17   -{
18   - puts ("Board: KVME080\n");
19   - return 0;
20   -}
21   -
22   -unsigned long setdram(int m, int row, int col, int bank)
23   -{
24   - int i;
25   - unsigned long start, end;
26   - uint32_t mccr1;
27   - uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
28   - uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
29   - uint8_t mber = 0;
30   -
31   - CONFIG_READ_WORD(MCCR1, mccr1);
32   - mccr1 &= 0xffff0000;
33   -
34   - start = CONFIG_SYS_SDRAM_BASE;
35   - end = start + (1 << (col + row + 3) ) * bank - 1;
36   -
37   - for (i = 0; i < m; i++) {
38   - mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
39   - if (i < 4) {
40   - msar1 |= ((start >> 20) & 0xff) << i * 8;
41   - emsar1 |= ((start >> 28) & 0xff) << i * 8;
42   - mear1 |= ((end >> 20) & 0xff) << i * 8;
43   - emear1 |= ((end >> 28) & 0xff) << i * 8;
44   - } else {
45   - msar2 |= ((start >> 20) & 0xff) << (i-4) * 8;
46   - emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
47   - mear2 |= ((end >> 20) & 0xff) << (i-4) * 8;
48   - emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
49   - }
50   - mber |= 1 << i;
51   - start += (1 << (col + row + 3) ) * bank;
52   - end += (1 << (col + row + 3) ) * bank;
53   - }
54   - for (; i < 8; i++) {
55   - if (i < 4) {
56   - msar1 |= 0xff << i * 8;
57   - emsar1 |= 0x30 << i * 8;
58   - mear1 |= 0xff << i * 8;
59   - emear1 |= 0x30 << i * 8;
60   - } else {
61   - msar2 |= 0xff << (i-4) * 8;
62   - emsar2 |= 0x30 << (i-4) * 8;
63   - mear2 |= 0xff << (i-4) * 8;
64   - emear2 |= 0x30 << (i-4) * 8;
65   - }
66   - }
67   -
68   - CONFIG_WRITE_WORD(MCCR1, mccr1);
69   - CONFIG_WRITE_WORD(MSAR1, msar1);
70   - CONFIG_WRITE_WORD(EMSAR1, emsar1);
71   - CONFIG_WRITE_WORD(MEAR1, mear1);
72   - CONFIG_WRITE_WORD(EMEAR1, emear1);
73   - CONFIG_WRITE_WORD(MSAR2, msar2);
74   - CONFIG_WRITE_WORD(EMSAR2, emsar2);
75   - CONFIG_WRITE_WORD(MEAR2, mear2);
76   - CONFIG_WRITE_WORD(EMEAR2, emear2);
77   - CONFIG_WRITE_BYTE(MBER, mber);
78   -
79   - return (1 << (col + row + 3) ) * bank * m;
80   -}
81   -
82   -phys_size_t initdram(int board_type)
83   -{
84   - unsigned int msr;
85   - long int size = 0;
86   -
87   - msr = mfmsr();
88   - mtmsr(msr & ~(MSR_IR | MSR_DR));
89   - mtspr(IBAT2L, CONFIG_SYS_IBAT0L + 0x10000000);
90   - mtspr(IBAT2U, CONFIG_SYS_IBAT0U + 0x10000000);
91   - mtspr(DBAT2L, CONFIG_SYS_DBAT0L + 0x10000000);
92   - mtspr(DBAT2U, CONFIG_SYS_DBAT0U + 0x10000000);
93   - mtmsr(msr);
94   -
95   - if (setdram(2,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x20000000))
96   - size = 0x20000000; /* 512MB */
97   - else if (setdram(1,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000))
98   - size = 0x10000000; /* 256MB */
99   - else if (setdram(2,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000))
100   - size = 0x10000000; /* 256MB */
101   - else if (setdram(1,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000))
102   - size = 0x08000000; /* 128MB */
103   - else if (setdram(2,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000))
104   - size = 0x08000000; /* 128MB */
105   - else if (setdram(1,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x04000000))
106   - size = 0x04000000; /* 64MB */
107   -
108   - msr = mfmsr();
109   - mtmsr(msr & ~(MSR_IR | MSR_DR));
110   - mtspr(IBAT2L, CONFIG_SYS_IBAT2L);
111   - mtspr(IBAT2U, CONFIG_SYS_IBAT2U);
112   - mtspr(DBAT2L, CONFIG_SYS_DBAT2L);
113   - mtspr(DBAT2U, CONFIG_SYS_DBAT2U);
114   - mtmsr(msr);
115   -
116   - return size;
117   -}
118   -
119   -struct pci_controller hose;
120   -
121   -void pci_init_board(void)
122   -{
123   - pci_mpc824x_init(&hose);
124   -}
125   -
126   -int board_early_init_f(void)
127   -{
128   - *(volatile unsigned char *)(0xff080120) = 0xfb;
129   -
130   - return 0;
131   -}
132   -
133   -int board_early_init_r(void)
134   -{
135   - unsigned int msr;
136   -
137   - CONFIG_WRITE_WORD(ERCR1, 0x95ff8000);
138   - CONFIG_WRITE_WORD(ERCR3, 0x0c00000e);
139   - CONFIG_WRITE_WORD(ERCR4, 0x0800000e);
140   -
141   - msr = mfmsr();
142   - mtmsr(msr & ~(MSR_IR | MSR_DR));
143   - mtspr(IBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
144   - mtspr(IBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
145   - mtspr(DBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
146   - mtspr(DBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
147   - mtmsr(msr);
148   -
149   - return 0;
150   -}
151   -
152   -extern int multiverse_init(void);
153   -
154   -int misc_init_r(void)
155   -{
156   - multiverse_init();
157   - return 0;
158   -}
159   -
160   -void *nvram_read(void *dest, const long src, size_t count)
161   -{
162   - volatile uchar *d = (volatile uchar*) dest;
163   - volatile uchar *s = (volatile uchar*) src;
164   - while(count--) {
165   - *d++ = *s++;
166   - asm volatile("sync");
167   - }
168   - return dest;
169   -}
170   -
171   -void nvram_write(long dest, const void *src, size_t count)
172   -{
173   - volatile uchar *d = (volatile uchar*)dest;
174   - volatile uchar *s = (volatile uchar*)src;
175   - while(count--) {
176   - *d++ = *s++;
177   - asm volatile("sync");
178   - }
179   -}
180   -
181   -int board_eth_init(bd_t *bis)
182   -{
183   - return pci_eth_init(bis);
184   -}
board/etin/kvme080/multiverse.c
View file @ 2868f86
1   -/*
2   - * multiverse.c
3   - *
4   - * VME driver for Multiverse
5   - *
6   - * Author : Sangmoon Kim
7   - * dogoil@etinsys.com
8   - *
9   - * Copyright 2005 ETIN SYSTEMS Co.,Ltd.
10   - *
11   - * SPDX-License-Identifier: GPL-2.0+
12   - */
13   -
14   -#include <common.h>
15   -#include <asm/io.h>
16   -#include <pci.h>
17   -#include <linux/compiler.h>
18   -
19   -#include "multiverse.h"
20   -
21   -static unsigned long vme_asi_addr;
22   -static unsigned long vme_iack_addr;
23   -static unsigned long pci_reg_addr;
24   -static unsigned long vme_reg_addr;
25   -
26   -int multiv_reset(unsigned long base)
27   -{
28   - writeb(0x09, base + VME_SLAVE32_AM);
29   - writeb(0x39, base + VME_SLAVE24_AM);
30   - writeb(0x29, base + VME_SLAVE16_AM);
31   - writeb(0x2f, base + VME_SLAVE_REG_AM);
32   - writeb((VME_A32_SLV_BUS >> 24) & 0xff, base + VME_SLAVE32_A);
33   - writeb((VME_A24_SLV_BUS >> 16) & 0xff, base + VME_SLAVE24_A);
34   - writeb((VME_A16_SLV_BUS >> 8 ) & 0xff, base + VME_SLAVE16_A);
35   -#ifdef A32_SLV_WINDOW
36   - if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
37   - writeb(((~(VME_A32_SLV_SIZE-1)) >> 24) & 0xff,
38   - base + VME_SLAVE32_MASK);
39   - writeb(0x01, base + VME_SLAVE32_EN);
40   - } else {
41   - writeb(0xff, base + VME_SLAVE32_MASK);
42   - writeb(0x00, base + VME_SLAVE32_EN);
43   - }
44   -#else
45   - writeb(0xff, base + VME_SLAVE32_MASK);
46   - writeb(0x00, base + VME_SLAVE32_EN);
47   -#endif
48   -#ifdef A24_SLV_WINDOW
49   - if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
50   - writeb(((~(VME_A24_SLV_SIZE-1)) >> 16) & 0xff,
51   - base + VME_SLAVE24_MASK);
52   - writeb(0x01, base + VME_SLAVE24_EN);
53   - } else {
54   - writeb(0xff, base + VME_SLAVE24_MASK);
55   - writeb(0x00, base + VME_SLAVE24_EN);
56   - }
57   -#else
58   - writeb(0xff, base + VME_SLAVE24_MASK);
59   - writeb(0x00, base + VME_SLAVE24_EN);
60   -#endif
61   -#ifdef A16_SLV_WINDOW
62   - if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
63   - writeb(((~(VME_A16_SLV_SIZE-1)) >> 8) & 0xff,
64   - base + VME_SLAVE16_MASK);
65   - writeb(0x01, base + VME_SLAVE16_EN);
66   - } else {
67   - writeb(0xff, base + VME_SLAVE16_MASK);
68   - writeb(0x00, base + VME_SLAVE16_EN);
69   - }
70   -#else
71   - writeb(0xff, base + VME_SLAVE16_MASK);
72   - writeb(0x00, base + VME_SLAVE16_EN);
73   -#endif
74   -#ifdef REG_SLV_WINDOW
75   - if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
76   - writeb(((~(VME_REG_SLV_SIZE-1)) >> 16) & 0xff,
77   - base + VME_SLAVE_REG_MASK);
78   - writeb(0x01, base + VME_SLAVE_REG_EN);
79   - } else {
80   - writeb(0xf8, base + VME_SLAVE_REG_MASK);
81   - }
82   -#else
83   - writeb(0xf8, base + VME_SLAVE_REG_MASK);
84   -#endif
85   - writeb(0x09, base + VME_MASTER32_AM);
86   - writeb(0x39, base + VME_MASTER24_AM);
87   - writeb(0x29, base + VME_MASTER16_AM);
88   - writeb(0x2f, base + VME_MASTER_REG_AM);
89   - writel(0x00000000, base + VME_RMW_ADRS);
90   - writeb(0x00, base + VME_IRQ);
91   - writeb(0x00, base + VME_INT_EN);
92   - writel(0x00000000, base + VME_IRQ1_REG);
93   - writel(0x00000000, base + VME_IRQ2_REG);
94   - writel(0x00000000, base + VME_IRQ3_REG);
95   - writel(0x00000000, base + VME_IRQ4_REG);
96   - writel(0x00000000, base + VME_IRQ5_REG);
97   - writel(0x00000000, base + VME_IRQ6_REG);
98   - writel(0x00000000, base + VME_IRQ7_REG);
99   - return 0;
100   -}
101   -
102   -void multiv_auto_slot_id(unsigned long base)
103   -{
104   - __maybe_unused unsigned int vector;
105   - int slot_id = 1;
106   - if (readb(base + VME_CTRL) & VME_CTRL_SYSFAIL) {
107   - *(volatile unsigned int*)(base + VME_IRQ2_REG) = 0xfe;
108   - writeb(readb(base + VME_IRQ) | 0x04, base + VME_IRQ);
109   - writeb(readb(base + VME_CTRL) & ~VME_CTRL_SYSFAIL,
110   - base + VME_CTRL);
111   - while (readb(base + VME_STATUS) & VME_STATUS_SYSFAIL);
112   - if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
113   - while (readb(base + VME_INT) & 0x04) {
114   - vector = *(volatile unsigned int*)
115   - (vme_iack_addr + VME_IACK2);
116   - *(unsigned char*)(vme_asi_addr + 0x7ffff)
117   - = (slot_id << 3) & 0xff;
118   - slot_id ++;
119   - if (slot_id > 31)
120   - break;
121   - }
122   - }
123   - }
124   -}
125   -
126   -int multiverse_init(void)
127   -{
128   - int i;
129   - pci_dev_t pdev;
130   - unsigned int bar[6];
131   -
132   - pdev = pci_find_device(0x1895, 0x0001, 0);
133   -
134   - if (pdev == 0)
135   - return -1;
136   -
137   - for (i = 0; i < 6; i++)
138   - pci_read_config_dword (pdev,
139   - PCI_BASE_ADDRESS_0 + i * 4, &bar[i]);
140   -
141   - pci_reg_addr = bar[0];
142   - vme_reg_addr = bar[1] + 0x00F00000;
143   - vme_iack_addr = bar[1] + 0x00200000;
144   - vme_asi_addr = bar[3];
145   -
146   - pci_write_config_dword (pdev, PCI_COMMAND,
147   - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
148   -
149   - writel(0xFF000000, pci_reg_addr + P_TA1);
150   - writel(0x04, pci_reg_addr + P_IMG_CTRL1);
151   - writel(0xf0000000, pci_reg_addr + P_TA2);
152   - writel(0x04, pci_reg_addr + P_IMG_CTRL2);
153   - writel(0xF1000000, pci_reg_addr + P_TA3);
154   - writel(0x04, pci_reg_addr + P_IMG_CTRL3);
155   - writel(VME_A32_MSTR_BUS, pci_reg_addr + P_TA5);
156   - writel(~(VME_A32_MSTR_SIZE-1), pci_reg_addr + P_AM5);
157   - writel(0x04, pci_reg_addr + P_IMG_CTRL5);
158   -
159   - writel(VME_A32_SLV_BUS, pci_reg_addr + W_BA1);
160   - writel(~(VME_A32_SLV_SIZE-1), pci_reg_addr + W_AM1);
161   - writel(VME_A32_SLV_LOCAL, pci_reg_addr + W_TA1);
162   - writel(0x04, pci_reg_addr + W_IMG_CTRL1);
163   -
164   - writel(0xF0000000, pci_reg_addr + W_BA2);
165   - writel(0xFF000000, pci_reg_addr + W_AM2);
166   - writel(VME_A24_SLV_LOCAL, pci_reg_addr + W_TA2);
167   - writel(0x04, pci_reg_addr + W_IMG_CTRL2);
168   -
169   - writel(0xFF000000, pci_reg_addr + W_BA3);
170   - writel(0xFF000000, pci_reg_addr + W_AM3);
171   - writel(VME_A16_SLV_LOCAL, pci_reg_addr + W_TA3);
172   - writel(0x04, pci_reg_addr + W_IMG_CTRL3);
173   -
174   - writel(0x00000001, pci_reg_addr + W_ERR_CS);
175   - writel(0x00000001, pci_reg_addr + P_ERR_CS);
176   -
177   - multiv_reset(vme_reg_addr);
178   - writeb(readb(vme_reg_addr + VME_CTRL) | VME_CTRL_SHORT_D,
179   - vme_reg_addr + VME_CTRL);
180   -
181   - multiv_auto_slot_id(vme_reg_addr);
182   -
183   - return 0;
184   -}
board/etin/kvme080/multiverse.h
View file @ 2868f86
1   -/*
2   - * multiverse.h
3   - *
4   - * VME driver for Multiverse
5   - *
6   - * Author : Sangmoon Kim
7   - * dogoil@etinsys.com
8   - *
9   - * Copyright 2005 ETIN SYSTEMS Co.,Ltd.
10   - *
11   - * SPDX-License-Identifier: GPL-2.0+
12   - */
13   -
14   -#ifndef __MULTIVERSE_H__
15   -#define __MULTIVERSE_H__
16   -
17   -#define VME_A32_MSTR_BUS 0x90000000
18   -#define VME_A32_MSTR_SIZE 0x01000000
19   -
20   -#define VME_A32_SLV_SIZE 0x01000000
21   -
22   -#define VME_A32_SLV_BUS 0x90000000
23   -#define VME_A24_SLV_BUS 0x00000000
24   -#define VME_A16_SLV_BUS 0x00000000
25   -
26   -#define VME_A32_SLV_LOCAL 0x00000000
27   -#define VME_A24_SLV_LOCAL 0x00000000
28   -#define VME_A16_SLV_LOCAL 0x00000000
29   -
30   -#define A32_SLV_WINDOW
31   -#undef A24_SLV_WINDOW
32   -#undef A16_SLV_WINDOW
33   -#undef REG_SLV_WINDOW
34   -
35   -/* PCI Registers */
36   -
37   -#define P_IMG_CTRL0 0x100
38   -#define P_BA0 0x104
39   -#define P_AM0 0x108
40   -#define P_TA0 0x10C
41   -#define P_IMG_CTRL1 0x110
42   -#define P_BA1 0x114
43   -#define P_AM1 0x118
44   -#define P_TA1 0x11C
45   -#define P_IMG_CTRL2 0x120
46   -#define P_BA2 0x124
47   -#define P_AM2 0x128
48   -#define P_TA2 0x12C
49   -#define P_IMG_CTRL3 0x130
50   -#define P_BA3 0x134
51   -#define P_AM3 0x138
52   -#define P_TA3 0x13C
53   -#define P_IMG_CTRL4 0x140
54   -#define P_BA4 0x144
55   -#define P_AM4 0x148
56   -#define P_TA4 0x14C
57   -#define P_IMG_CTRL5 0x150
58   -#define P_BA5 0x154
59   -#define P_AM5 0x158
60   -#define P_TA5 0x15C
61   -#define P_ERR_CS 0x160
62   -#define P_ERR_ADDR 0x164
63   -#define P_ERR_DATA 0x168
64   -
65   -#define WB_CONF_SPC_BAR 0x180
66   -#define W_IMG_CTRL1 0x184
67   -#define W_BA1 0x188
68   -#define W_AM1 0x18C
69   -#define W_TA1 0x190
70   -#define W_IMG_CTRL2 0x194
71   -#define W_BA2 0x198
72   -#define W_AM2 0x19C
73   -#define W_TA2 0x1A0
74   -#define W_IMG_CTRL3 0x1A4
75   -#define W_BA3 0x1A8
76   -#define W_AM3 0x1AC
77   -#define W_TA3 0x1B0
78   -#define W_IMG_CTRL4 0x1B4
79   -#define W_BA4 0x1B8
80   -#define W_AM4 0x1BC
81   -#define W_TA4 0x1C0
82   -#define W_IMG_CTRL5 0x1C4
83   -#define W_BA5 0x1C8
84   -#define W_AM5 0x1CC
85   -#define W_TA5 0x1D0
86   -#define W_ERR_CS 0x1D4
87   -#define W_ERR_ADDR 0x1D8
88   -#define W_ERR_DATA 0x1DC
89   -#define CNF_ADDR 0x1E0
90   -#define CNF_DATA 0x1E4
91   -#define INT_ACK 0x1E8
92   -#define ICR 0x1EC
93   -#define ISR 0x1F0
94   -
95   -/* VME registers */
96   -
97   -#define VME_SLAVE32_AM 0x03
98   -#define VME_SLAVE24_AM 0x02
99   -#define VME_SLAVE16_AM 0x01
100   -#define VME_SLAVE_REG_AM 0x00
101   -#define VME_SLAVE32_A 0x07
102   -#define VME_SLAVE24_A 0x06
103   -#define VME_SLAVE16_A 0x05
104   -#define VME_SLAVE_REG_A 0x04
105   -#define VME_SLAVE32_MASK 0x0B
106   -#define VME_SLAVE24_MASK 0x0A
107   -#define VME_SLAVE16_MASK 0x09
108   -#define VME_SLAVE_REG_MASK 0x08
109   -#define VME_SLAVE32_EN 0x0F
110   -#define VME_SLAVE24_EN 0x0E
111   -#define VME_SLAVE16_EN 0x0D
112   -#define VME_SLAVE_REG_EN 0x0C
113   -#define VME_MASTER32_AM 0x13
114   -#define VME_MASTER24_AM 0x12
115   -#define VME_MASTER16_AM 0x11
116   -#define VME_MASTER_REG_AM 0x10
117   -#define VME_RMW_ADRS 0x14
118   -#define VME_MBOX 0x18
119   -#define VME_STATUS 0x1E
120   -#define VME_CTRL 0x1C
121   -#define VME_IRQ 0x20
122   -#define VME_INT_EN 0x21
123   -#define VME_INT 0x22
124   -#define VME_IRQ1_REG 0x24
125   -#define VME_IRQ2_REG 0x28
126   -#define VME_IRQ3_REG 0x2C
127   -#define VME_IRQ4_REG 0x30
128   -#define VME_IRQ5_REG 0x34
129   -#define VME_IRQ6_REG 0x38
130   -#define VME_IRQ7_REG 0x3C
131   -
132   -/* VME control register */
133   -
134   -#define VME_CTRL_BRDRST 0x01
135   -#define VME_CTRL_SYSRST 0x02
136   -#define VME_CTRL_RMW 0x04
137   -#define VME_CTRL_SHORT_D 0x08
138   -#define VME_CTRL_SYSFAIL 0x10
139   -#define VME_CTRL_VOWN 0x20
140   -#define VME_CTRL_A16_REG_MODE 0x40
141   -
142   -/* VME status register */
143   -
144   -#define VME_STATUS_SYSCON 0x01
145   -#define VME_STATUS_SYSFAIL 0x02
146   -#define VME_STATUS_ACFAIL 0x04
147   -#define VME_STATUS_SYSRST 0x08
148   -#define VME_STATUS_VOWN 0x10
149   -
150   -/* Interrupt types */
151   -
152   -#define LVL1 0x0002
153   -#define LVL2 0x0004
154   -#define LVL3 0x0008
155   -#define LVL4 0x0010
156   -#define LVL5 0x0020
157   -#define LVL6 0x0040
158   -#define LVL7 0x0080
159   -#define MULTIVERSE_INTI_INT 0x0100
160   -#define MULTIVERSE_WB_INT 0x0200
161   -#define MULTIVERSE_PCI_INT 0x0400
162   -
163   -/* interrupt acknowledge */
164   -
165   -#define VME_IACK1 0x04
166   -#define VME_IACK2 0x08
167   -#define VME_IACK3 0x0c
168   -#define VME_IACK4 0x10
169   -#define VME_IACK5 0x14
170   -#define VME_IACK6 0x18
171   -#define VME_IACK7 0x1c
172   -
173   -#endif /* __MULTIVERSE_H__ */
... ... @@ -1241,7 +1241,6 @@
1241 1241 Orphan powerpc mpc5xxx - matrix_vision mvsmr MVSMR - Andre Schwarz <andre.schwarz@matrix-vision.de>
1242 1242 Orphan powerpc mpc824x - - hidden_dragon HIDDEN_DRAGON - Yusdi Santoso <yusdi_santoso@adaptec.com>
1243 1243 Orphan powerpc mpc824x - etin - debris - Sangmoon Kim <dogoil@etinsys.com>
1244   -Orphan powerpc mpc824x - etin - kvme080 - Sangmoon Kim <dogoil@etinsys.com>
1245 1244 Orphan powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK - Anton Vorontsov <avorontsov@ru.mvista.com>
1246 1245 Orphan powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_33 MPC8360ERDK:CLKIN_33MHZ Anton Vorontsov <avorontsov@ru.mvista.com>
1247 1246 Orphan powerpc mpc83xx - matrix_vision mergerbox MERGERBOX - Andre Schwarz <andre.schwarz@matrix-vision.de>
doc/README.scrapyard
Diff comments   View file @ 2868f86
... ... @@ -11,6 +11,7 @@
11 11  
12 12 Board Arch CPU Commit Removed Last known maintainer/contact
13 13 =================================================================================================
  14 +kvme080 powerpc mpc824x - - Sangmoon Kim <dogoil@etinsys.com>
14 15 ep8248 powerpc mpc8260 - - Yuli Barcohen <yuli@arabellasw.com>
15 16 ispan powerpc mpc8260 - - Yuli Barcohen <yuli@arabellasw.com>
16 17 rattler powerpc mpc8260 - - Yuli Barcohen <yuli@arabellasw.com>
include/configs/kvme080.h
View file @ 2868f86
1   -/*
2   - * (C) Copyright 2005
3   - * Sangmoon Kim, dogoil@etinsys.com.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#ifndef __CONFIG_H
9   -#define __CONFIG_H
10   -
11   -#define CONFIG_MPC8245 1
12   -#define CONFIG_KVME080 1
13   -
14   -#define CONFIG_SYS_TEXT_BASE 0xFFF00000
15   -
16   -#define CONFIG_CONS_INDEX 1
17   -
18   -#define CONFIG_BAUDRATE 115200
19   -
20   -#define CONFIG_BOOTDELAY 5
21   -
22   -#define CONFIG_IPADDR 192.168.0.2
23   -#define CONFIG_NETMASK 255.255.255.0
24   -#define CONFIG_SERVERIP 192.168.0.1
25   -
26   -#define CONFIG_BOOTARGS \
27   - "console=ttyS0,115200 " \
28   - "root=/dev/nfs rw nfsroot=192.168.0.1:/opt/eldk/ppc_82xx " \
29   - "ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:" \
30   - "kvme080:eth0:none " \
31   - "mtdparts=phys_mapped_flash:12m(root),-(kernel)"
32   -
33   -#define CONFIG_BOOTCOMMAND \
34   - "tftp 800000 kvme080/uImage; " \
35   - "bootm 800000"
36   -
37   -#define CONFIG_LOADADDR 800000
38   -
39   -#define CONFIG_BOARD_EARLY_INIT_F
40   -#define CONFIG_BOARD_EARLY_INIT_R
41   -#define CONFIG_MISC_INIT_R
42   -
43   -#define CONFIG_LOADS_ECHO 1
44   -#undef CONFIG_SYS_LOADS_BAUD_CHANGE
45   -
46   -#undef CONFIG_WATCHDOG
47   -
48   -/*
49   - * BOOTP options
50   - */
51   -#define CONFIG_BOOTP_SUBNETMASK
52   -#define CONFIG_BOOTP_GATEWAY
53   -#define CONFIG_BOOTP_HOSTNAME
54   -#define CONFIG_BOOTP_BOOTPATH
55   -#define CONFIG_BOOTP_BOOTFILESIZE
56   -
57   -
58   -#define CONFIG_MAC_PARTITION
59   -#define CONFIG_DOS_PARTITION
60   -
61   -#define CONFIG_RTC_DS164x
62   -
63   -
64   -/*
65   - * Command line configuration.
66   - */
67   -#include <config_cmd_default.h>
68   -
69   -#define CONFIG_CMD_ASKENV
70   -#define CONFIG_CMD_CACHE
71   -#define CONFIG_CMD_DATE
72   -#define CONFIG_CMD_DHCP
73   -#define CONFIG_CMD_DIAG
74   -#define CONFIG_CMD_EEPROM
75   -#define CONFIG_CMD_ELF
76   -#define CONFIG_CMD_I2C
77   -#define CONFIG_CMD_JFFS2
78   -#define CONFIG_CMD_NFS
79   -#define CONFIG_CMD_PCI
80   -#define CONFIG_CMD_PING
81   -#define CONFIG_CMD_SDRAM
82   -#define CONFIG_CMD_SNTP
83   -
84   -
85   -#define CONFIG_NETCONSOLE
86   -
87   -#define CONFIG_SYS_LONGHELP
88   -#define CONFIG_SYS_CBSIZE 256
89   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
90   -#define CONFIG_SYS_MAXARGS 16
91   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
92   -
93   -#define CONFIG_SYS_MEMTEST_START 0x00400000
94   -#define CONFIG_SYS_MEMTEST_END 0x07C00000
95   -
96   -#define CONFIG_SYS_LOAD_ADDR 0x00100000
97   -
98   -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
99   -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
100   -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
101   -
102   -#define CONFIG_SYS_SDRAM_BASE 0x00000000
103   -#define CONFIG_SYS_FLASH_BASE 0x7C000000
104   -#define CONFIG_SYS_EUMB_ADDR 0xFC000000
105   -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xFF000000
106   -#define CONFIG_SYS_NS16550_COM1 0xFF080000
107   -#define CONFIG_SYS_NS16550_COM2 0xFF080010
108   -#define CONFIG_SYS_NS16550_COM3 0xFF080020
109   -#define CONFIG_SYS_NS16550_COM4 0xFF080030
110   -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
111   -
112   -#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
113   -#define CONFIG_SYS_FLASH_SIZE (16 * 1024 * 1024)
114   -#define CONFIG_SYS_NVRAM_SIZE 0x7FFF8
115   -
116   -#define CONFIG_VERY_BIG_RAM
117   -
118   -#define CONFIG_SYS_MONITOR_LEN 0x00040000
119   -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
120   -#define CONFIG_SYS_MALLOC_LEN (512 << 10)
121   -
122   -#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
123   -
124   -#define CONFIG_SYS_FLASH_CFI
125   -#define CONFIG_FLASH_CFI_DRIVER
126   -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
127   -#define CONFIG_SYS_FLASH_PROTECTION
128   -#define CONFIG_SYS_FLASH_EMPTY_INFO
129   -#define CONFIG_SYS_FLASH_PROTECT_CLEAR
130   -
131   -#define CONFIG_SYS_MAX_FLASH_BANKS 1
132   -#define CONFIG_SYS_MAX_FLASH_SECT 256
133   -
134   -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
135   -#define CONFIG_SYS_FLASH_WRITE_TOUT 500
136   -
137   -#define CONFIG_SYS_JFFS2_FIRST_BANK 0
138   -#define CONFIG_SYS_JFFS2_NUM_BANKS 1
139   -
140   -#define CONFIG_ENV_IS_IN_NVRAM 1
141   -#define CONFIG_ENV_OVERWRITE 1
142   -#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE
143   -#define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE_ADDR
144   -#define CONFIG_ENV_SIZE 0x400
145   -#define CONFIG_ENV_OFFSET 0
146   -
147   -#define CONFIG_SYS_NS16550
148   -#define CONFIG_SYS_NS16550_SERIAL
149   -#define CONFIG_SYS_NS16550_REG_SIZE 1
150   -#define CONFIG_SYS_NS16550_CLK 14745600
151   -
152   -#define CONFIG_PCI
153   -#define CONFIG_PCI_INDIRECT_BRIDGE
154   -#define CONFIG_PCI_PNP
155   -
156   -#define CONFIG_EEPRO100
157   -#define CONFIG_EEPRO100_SROM_WRITE
158   -
159   -#define CONFIG_SYS_RX_ETH_BUFFER 8
160   -
161   -#define CONFIG_HARD_I2C 1
162   -#define CONFIG_SYS_I2C_SPEED 400000
163   -#define CONFIG_SYS_I2C_SLAVE 0x7F
164   -
165   -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
166   -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
167   -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
168   -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
169   -
170   -#define CONFIG_SYS_CLK_FREQ 33333333
171   -
172   -#define CONFIG_SYS_CACHELINE_SIZE 32
173   -#if defined(CONFIG_CMD_KGDB)
174   -# define CONFIG_SYS_CACHELINE_SHIFT 5
175   -#endif
176   -
177   -#define CONFIG_SYS_DLL_EXTEND 0x00
178   -#define CONFIG_SYS_PCI_HOLD_DEL 0x20
179   -
180   -#define CONFIG_SYS_ROMNAL 15
181   -#define CONFIG_SYS_ROMFAL 31
182   -
183   -#define CONFIG_SYS_REFINT 430
184   -
185   -#define CONFIG_SYS_DBUS_SIZE2 1
186   -
187   -#define CONFIG_SYS_BSTOPRE 121
188   -#define CONFIG_SYS_REFREC 8
189   -#define CONFIG_SYS_RDLAT 4
190   -#define CONFIG_SYS_PRETOACT 3
191   -#define CONFIG_SYS_ACTTOPRE 5
192   -#define CONFIG_SYS_ACTORW 3
193   -#define CONFIG_SYS_SDMODE_CAS_LAT 3
194   -#define CONFIG_SYS_SDMODE_WRAP 0
195   -
196   -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
197   -#define CONFIG_SYS_EXTROM 1
198   -#define CONFIG_SYS_REGDIMM 0
199   -
200   -#define CONFIG_SYS_BANK0_START 0x00000000
201   -#define CONFIG_SYS_BANK0_END (0x4000000 - 1)
202   -#define CONFIG_SYS_BANK0_ENABLE 1
203   -#define CONFIG_SYS_BANK1_START 0x04000000
204   -#define CONFIG_SYS_BANK1_END (0x8000000 - 1)
205   -#define CONFIG_SYS_BANK1_ENABLE 1
206   -#define CONFIG_SYS_BANK2_START 0x3ff00000
207   -#define CONFIG_SYS_BANK2_END 0x3fffffff
208   -#define CONFIG_SYS_BANK2_ENABLE 0
209   -#define CONFIG_SYS_BANK3_START 0x3ff00000
210   -#define CONFIG_SYS_BANK3_END 0x3fffffff
211   -#define CONFIG_SYS_BANK3_ENABLE 0
212   -#define CONFIG_SYS_BANK4_START 0x00000000
213   -#define CONFIG_SYS_BANK4_END 0x00000000
214   -#define CONFIG_SYS_BANK4_ENABLE 0
215   -#define CONFIG_SYS_BANK5_START 0x00000000
216   -#define CONFIG_SYS_BANK5_END 0x00000000
217   -#define CONFIG_SYS_BANK5_ENABLE 0
218   -#define CONFIG_SYS_BANK6_START 0x00000000
219   -#define CONFIG_SYS_BANK6_END 0x00000000
220   -#define CONFIG_SYS_BANK6_ENABLE 0
221   -#define CONFIG_SYS_BANK7_START 0x00000000
222   -#define CONFIG_SYS_BANK7_END 0x00000000
223   -#define CONFIG_SYS_BANK7_ENABLE 0
224   -
225   -#define CONFIG_SYS_BANK_ENABLE 0x03
226   -
227   -#define CONFIG_SYS_ODCR 0x75
228   -#define CONFIG_SYS_PGMAX 0x32
229   -
230   -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
231   -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
232   -
233   -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
234   -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
235   -
236   -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
237   -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
238   -
239   -#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
240   -#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
241   -
242   -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
243   -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
244   -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
245   -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
246   -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
247   -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
248   -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
249   -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
250   -
251   -#endif /* __CONFIG_H */