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Commit 290097fe2736dd23bfb926658d188db533b59779

Authored by Adam Ford
Committed by Tom Rini
1 parent e18333e501
Exists in smarc_8mq_lf_v2020.04 and in 11 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

ARM: omap3_logic: Add NOR Flash Support for SOM-LV 

The DM37 and OMAP35 SOM-LV SOM-LV products both support a NOR
flash part connected to CS2 in addition to the NAND part on CS0.
This patch setups the GPMC timings for the MT28 NOR Flash and
enables the CFI-Flash driver now that the CFI stuff is in Kconfig

Signed-off-by: Adam Ford <aford173@gmail.com>

Showing 4 changed files with 70 additions and 7 deletions Side-by-side Diff

board/logicpd/omap3som/omap3logic.c
Diff comments   View file @ 290097f
... ... @@ -40,6 +40,22 @@
40 40  
41 41 DECLARE_GLOBAL_DATA_PTR;
42 42  
  43 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1 0x00011203
  44 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2 0x000A1302
  45 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3 0x000F1302
  46 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4 0x0A021303
  47 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5 0x00120F18
  48 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6 0x0A030000
  49 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7 0x00000C50
  50 +
  51 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1 0x00011203
  52 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2 0x00091102
  53 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3 0x000D1102
  54 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4 0x09021103
  55 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5 0x00100D15
  56 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6 0x09030000
  57 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7 0x00000C50
  58 +
43 59 /* This is only needed until SPL gets OF support */
44 60 #ifdef CONFIG_SPL_BUILD
45 61 static const struct ns16550_platdata omap3logic_serial = {
... ... @@ -220,6 +236,28 @@
220 236 return 0;
221 237 }
222 238  
  239 +#if defined(CONFIG_FLASH_CFI_DRIVER)
  240 +static const u32 gpmc_dm37_c2nor_config[] = {
  241 + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1,
  242 + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2,
  243 + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3,
  244 + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4,
  245 + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5,
  246 + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6,
  247 + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7
  248 +};
  249 +
  250 +static const u32 gpmc_omap35_c2nor_config[] = {
  251 + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1,
  252 + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2,
  253 + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3,
  254 + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4,
  255 + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5,
  256 + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6,
  257 + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7
  258 +};
  259 +#endif
  260 +
223 261 /*
224 262 * Routine: board_init
225 263 * Description: Early hardware init.
... ... @@ -230,7 +268,16 @@
230 268  
231 269 /* boot param addr */
232 270 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
233   -
  271 +#if defined(CONFIG_FLASH_CFI_DRIVER)
  272 + if (get_cpu_family() == CPU_OMAP36XX) {
  273 + /* Enable CS2 for NOR Flash */
  274 + enable_gpmc_cs_config(gpmc_dm37_c2nor_config, &gpmc_cfg->cs[2],
  275 + 0x10000000, GPMC_SIZE_64M);
  276 + } else {
  277 + enable_gpmc_cs_config(gpmc_omap35_c2nor_config, &gpmc_cfg->cs[2],
  278 + 0x10000000, GPMC_SIZE_64M);
  279 + }
  280 +#endif
234 281 return 0;
235 282 }
236 283  
configs/omap35_logic_somlv_defconfig
Diff comments   View file @ 290097f
... ... @@ -24,8 +24,8 @@
24 24 CONFIG_CMD_NAND=y
25 25 CONFIG_CMD_NAND_LOCK_UNLOCK=y
26 26 CONFIG_CMD_CACHE=y
27   -CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
28   -CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs)"
  27 +CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0,nor0=physmap-flash.0"
  28 +CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs);physmap-flash.0:-(nor)"
29 29 CONFIG_CMD_UBI=y
30 30 CONFIG_OF_CONTROL=y
31 31 CONFIG_SPL_OF_CONTROL=y
... ... @@ -39,6 +39,12 @@
39 39 CONFIG_DM_I2C=y
40 40 CONFIG_DM_MMC=y
41 41 CONFIG_MMC_OMAP_HS=y
  42 +CONFIG_MTD_NOR_FLASH=y
  43 +CONFIG_FLASH_CFI_DRIVER=y
  44 +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
  45 +CONFIG_FLASH_CFI_MTD=y
  46 +CONFIG_SYS_FLASH_PROTECTION=y
  47 +CONFIG_SYS_FLASH_CFI=y
42 48 CONFIG_NAND=y
43 49 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
44 50 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
configs/omap3_logic_somlv_defconfig
Diff comments   View file @ 290097f
... ... @@ -20,12 +20,11 @@
20 20 CONFIG_CMD_SPL_NAND_OFS=0x240000
21 21 CONFIG_CMD_SPL_WRITE_SIZE=0x20000
22 22 # CONFIG_CMD_EEPROM is not set
23   -# CONFIG_CMD_FLASH is not set
24 23 CONFIG_CMD_NAND=y
25 24 CONFIG_CMD_NAND_LOCK_UNLOCK=y
26 25 CONFIG_CMD_CACHE=y
27   -CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
28   -CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs)"
  26 +CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0,nor0=physmap-flash.0"
  27 +CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs);physmap-flash.0:-(nor)"
29 28 CONFIG_CMD_UBI=y
30 29 CONFIG_OF_CONTROL=y
31 30 CONFIG_SPL_OF_CONTROL=y
... ... @@ -40,6 +39,12 @@
40 39 CONFIG_DM_MMC=y
41 40 CONFIG_MMC_OMAP_HS=y
42 41 CONFIG_MMC_OMAP36XX_PINS=y
  42 +CONFIG_MTD_NOR_FLASH=y
  43 +CONFIG_FLASH_CFI_DRIVER=y
  44 +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
  45 +CONFIG_FLASH_CFI_MTD=y
  46 +CONFIG_SYS_FLASH_PROTECTION=y
  47 +CONFIG_SYS_FLASH_CFI=y
43 48 CONFIG_NAND=y
44 49 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
45 50 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
include/configs/omap3_logic.h
Diff comments   View file @ 290097f
... ... @@ -183,8 +183,13 @@
183 183  
184 184 /* **** PISMO SUPPORT *** */
185 185 #if defined(CONFIG_CMD_NAND)
186   -#define CONFIG_SYS_FLASH_BASE NAND_BASE
  186 +#define CONFIG_SYS_FLASH_BASE 0x10000000
187 187 #endif
  188 +
  189 +#define CONFIG_SYS_MAX_FLASH_SECT 256
  190 +#define CONFIG_SYS_MAX_FLASH_BANKS 1
  191 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  192 +#define CONFIG_SYS_FLASH_SIZE 0x4000000
188 193  
189 194 /* Monitor at start of flash */
190 195 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE