Eric Lee / smarc-uboot | Embedian Git Server

Commit 290e7cfdbfa288d26598c073186ab45e3fa711b3

Authored by Fabio Estevam 2018-01-03 22:33:05 +0800

Committed by Stefano Babic 2018-01-04 23:29:04 +0800

Exists in smarc_8mq_lf_v2020.04 and in 17 other branches

mx6ull: Handle the CONFIG_MX6ULL cases correctly

Since commit 051ba9e082f7 ("Kconfig: mx6ull: Deselect MX6UL from
CONFIG_MX6ULL") CONFIG_MX6ULL does not select CONFIG_MX6UL anymore, so
take this into consideration in all the checks for CONFIG_MX6UL.

This fixes a boot regression.

Reported-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Tested-by: Breno Lima <breno.lima@nxp.com>
Tested-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Tested-by: Jörg Krause <joerg.krause@embedded.rocks>

Showing 10 changed files with 40 additions and 28 deletions Inline Diff

arch/arm/include/asm/arch-mx6/imx-regs.h
arch/arm/include/asm/arch-mx6/mx6-ddr.h
arch/arm/include/asm/arch-mx6/mx6ul-ddr.h
arch/arm/include/asm/mach-imx/iomux-v3.h
arch/arm/include/asm/mach-imx/regs-lcdif.h
arch/arm/mach-imx/mx6/Kconfig
arch/arm/mach-imx/mx6/ddr.c
drivers/gpio/mxc_gpio.c
include/configs/imx6_spl.h
include/configs/mx6_common.h

arch/arm/include/asm/arch-mx6/imx-regs.h

Diff comments View file @ 290e7cf

 /*
  * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __ASM_ARCH_MX6_IMX_REGS_H__
 #define __ASM_ARCH_MX6_IMX_REGS_H__
 #define ARCH_MXC
 #define ROMCP_ARB_BASE_ADDR             0x00000000
 #define ROMCP_ARB_END_ADDR              0x000FFFFF
 #ifdef CONFIG_MX6SL
 #define GPU_2D_ARB_BASE_ADDR            0x02200000
 #define GPU_2D_ARB_END_ADDR             0x02203FFF
 #define OPENVG_ARB_BASE_ADDR            0x02204000
 #define OPENVG_ARB_END_ADDR             0x02207FFF
-#elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
+#elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
 #define CAAM_ARB_BASE_ADDR              0x00100000
 #define CAAM_ARB_END_ADDR               0x00107FFF
 #define GPU_ARB_BASE_ADDR               0x01800000
 #define GPU_ARB_END_ADDR                0x01803FFF
 #define APBH_DMA_ARB_BASE_ADDR          0x01804000
 #define APBH_DMA_ARB_END_ADDR           0x0180BFFF
 #define M4_BOOTROM_BASE_ADDR			0x007F8000
 #elif !defined(CONFIG_MX6SLL)
 #define CAAM_ARB_BASE_ADDR              0x00100000
 #define CAAM_ARB_END_ADDR               0x00103FFF
 #define APBH_DMA_ARB_BASE_ADDR          0x00110000
 #define APBH_DMA_ARB_END_ADDR           0x00117FFF
 #define HDMI_ARB_BASE_ADDR              0x00120000
 #define HDMI_ARB_END_ADDR               0x00128FFF
 #define GPU_3D_ARB_BASE_ADDR            0x00130000
 #define GPU_3D_ARB_END_ADDR             0x00133FFF
 #define GPU_2D_ARB_BASE_ADDR            0x00134000
 #define GPU_2D_ARB_END_ADDR             0x00137FFF
 #define DTCP_ARB_BASE_ADDR              0x00138000
 #define DTCP_ARB_END_ADDR               0x0013BFFF
 #endif	/* CONFIG_MX6SL */
 #define MXS_APBH_BASE			APBH_DMA_ARB_BASE_ADDR
 #define MXS_GPMI_BASE			(APBH_DMA_ARB_BASE_ADDR + 0x02000)
 #define MXS_BCH_BASE			(APBH_DMA_ARB_BASE_ADDR + 0x04000)
 /* GPV - PL301 configuration ports */
-#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
+#if (defined(CONFIG_MX6SX) || \
+	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
 	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL))
 #define GPV2_BASE_ADDR                  0x00D00000
 #define GPV3_BASE_ADDR			0x00E00000
 #define GPV4_BASE_ADDR			0x00F00000
 #define GPV5_BASE_ADDR			0x01000000
 #define GPV6_BASE_ADDR			0x01100000
 #define PCIE_ARB_BASE_ADDR              0x08000000
 #define PCIE_ARB_END_ADDR               0x08FFFFFF
 #else
 #define GPV2_BASE_ADDR			0x00200000
 #define GPV3_BASE_ADDR			0x00300000
 #define GPV4_BASE_ADDR			0x00800000
 #define PCIE_ARB_BASE_ADDR              0x01000000
 #define PCIE_ARB_END_ADDR               0x01FFFFFF
 #endif
 #define IRAM_BASE_ADDR			0x00900000
 #define SCU_BASE_ADDR                   0x00A00000
 #define IC_INTERFACES_BASE_ADDR         0x00A00100
 #define GLOBAL_TIMER_BASE_ADDR          0x00A00200
 #define PRIVATE_TIMERS_WD_BASE_ADDR     0x00A00600
 #define IC_DISTRIBUTOR_BASE_ADDR        0x00A01000
 #define L2_PL310_BASE			0x00A02000
 #define GPV0_BASE_ADDR                  0x00B00000
 #define GPV1_BASE_ADDR                  0x00C00000
 #define AIPS1_ARB_BASE_ADDR             0x02000000
 #define AIPS1_ARB_END_ADDR              0x020FFFFF
 #define AIPS2_ARB_BASE_ADDR             0x02100000
 #define AIPS2_ARB_END_ADDR              0x021FFFFF
 /* AIPS3 only on i.MX6SX */
 #define AIPS3_ARB_BASE_ADDR             0x02200000
 #define AIPS3_ARB_END_ADDR              0x022FFFFF
 #ifdef CONFIG_MX6SX
 #define WEIM_ARB_BASE_ADDR              0x50000000
 #define WEIM_ARB_END_ADDR               0x57FFFFFF
 #define QSPI0_AMBA_BASE                0x60000000
 #define QSPI0_AMBA_END                 0x6FFFFFFF
 #define QSPI1_AMBA_BASE                0x70000000
 #define QSPI1_AMBA_END                 0x7FFFFFFF
-#elif defined(CONFIG_MX6UL)
+#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
 #define WEIM_ARB_BASE_ADDR              0x50000000
 #define WEIM_ARB_END_ADDR               0x57FFFFFF
 #define QSPI0_AMBA_BASE                 0x60000000
 #define QSPI0_AMBA_END                  0x6FFFFFFF
 #elif !defined(CONFIG_MX6SLL)
 #define SATA_ARB_BASE_ADDR              0x02200000
 #define SATA_ARB_END_ADDR               0x02203FFF
 #define OPENVG_ARB_BASE_ADDR            0x02204000
 #define OPENVG_ARB_END_ADDR             0x02207FFF
 #define HSI_ARB_BASE_ADDR               0x02208000
 #define HSI_ARB_END_ADDR                0x0220BFFF
 #define IPU1_ARB_BASE_ADDR              0x02400000
 #define IPU1_ARB_END_ADDR               0x027FFFFF
 #define IPU2_ARB_BASE_ADDR              0x02800000
 #define IPU2_ARB_END_ADDR               0x02BFFFFF
 #define WEIM_ARB_BASE_ADDR              0x08000000
 #define WEIM_ARB_END_ADDR               0x0FFFFFFF
 #endif
 #if (defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
-	defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
+	defined(CONFIG_MX6SX) || \
+	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
 #define MMDC0_ARB_BASE_ADDR             0x80000000
 #define MMDC0_ARB_END_ADDR              0xFFFFFFFF
 #define MMDC1_ARB_BASE_ADDR             0xC0000000
 #define MMDC1_ARB_END_ADDR              0xFFFFFFFF
 #else
 #define MMDC0_ARB_BASE_ADDR             0x10000000
 #define MMDC0_ARB_END_ADDR              0x7FFFFFFF
 #define MMDC1_ARB_BASE_ADDR             0x80000000
 #define MMDC1_ARB_END_ADDR              0xFFFFFFFF
 #endif
 #ifndef CONFIG_MX6SX
 #define IPU_SOC_BASE_ADDR		IPU1_ARB_BASE_ADDR
 #define IPU_SOC_OFFSET			0x00200000
 #endif
 /* Defines for Blocks connected via AIPS (SkyBlue) */
 #define ATZ1_BASE_ADDR              AIPS1_ARB_BASE_ADDR
 #define ATZ2_BASE_ADDR              AIPS2_ARB_BASE_ADDR
 #define ATZ3_BASE_ADDR              AIPS3_ARB_BASE_ADDR
 #define AIPS1_BASE_ADDR             AIPS1_ON_BASE_ADDR
 #define AIPS2_BASE_ADDR             AIPS2_ON_BASE_ADDR
 #define AIPS3_BASE_ADDR             AIPS3_ON_BASE_ADDR
 #define SPDIF_BASE_ADDR             (ATZ1_BASE_ADDR + 0x04000)
 #define ECSPI1_BASE_ADDR            (ATZ1_BASE_ADDR + 0x08000)
 #define ECSPI2_BASE_ADDR            (ATZ1_BASE_ADDR + 0x0C000)
 #define ECSPI3_BASE_ADDR            (ATZ1_BASE_ADDR + 0x10000)
 #define ECSPI4_BASE_ADDR            (ATZ1_BASE_ADDR + 0x14000)
 #define MX6SL_UART5_BASE_ADDR       (ATZ1_BASE_ADDR + 0x18000)
 #define MX6SLL_UART4_BASE_ADDR      (ATZ1_BASE_ADDR + 0x18000)
 #define MX6UL_UART7_BASE_ADDR       (ATZ1_BASE_ADDR + 0x18000)
 #define MX6SL_UART2_BASE_ADDR       (ATZ1_BASE_ADDR + 0x24000)
 #define MX6SLL_UART2_BASE_ADDR      (ATZ1_BASE_ADDR + 0x24000)
 #define MX6UL_UART8_BASE_ADDR       (ATZ1_BASE_ADDR + 0x24000)
 #define MX6SL_UART3_BASE_ADDR       (ATZ1_BASE_ADDR + 0x34000)
 #define MX6SLL_UART3_BASE_ADDR      (ATZ1_BASE_ADDR + 0x34000)
 #define MX6SL_UART4_BASE_ADDR       (ATZ1_BASE_ADDR + 0x38000)
 #ifndef CONFIG_MX6SX
 #define ECSPI5_BASE_ADDR            (ATZ1_BASE_ADDR + 0x18000)
 #endif
 #define UART1_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x20000)
 #define UART1_BASE                  (ATZ1_BASE_ADDR + 0x20000)
 #define ESAI1_BASE_ADDR             (ATZ1_BASE_ADDR + 0x24000)
 #define UART8_BASE                  (ATZ1_BASE_ADDR + 0x24000)
 #define SSI1_BASE_ADDR              (ATZ1_BASE_ADDR + 0x28000)
 #define SSI2_BASE_ADDR              (ATZ1_BASE_ADDR + 0x2C000)
 #define SSI3_BASE_ADDR              (ATZ1_BASE_ADDR + 0x30000)
 #define ASRC_BASE_ADDR              (ATZ1_BASE_ADDR + 0x34000)
 #ifndef CONFIG_MX6SX
 #define SPBA_BASE_ADDR              (ATZ1_BASE_ADDR + 0x3C000)
 #define VPU_BASE_ADDR               (ATZ1_BASE_ADDR + 0x40000)
 #endif
 #define AIPS1_ON_BASE_ADDR          (ATZ1_BASE_ADDR + 0x7C000)
 #define AIPS1_OFF_BASE_ADDR         (ATZ1_BASE_ADDR + 0x80000)
 #define PWM1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x0000)
 #define PWM2_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x4000)
 #define PWM3_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x8000)
 #define PWM4_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0xC000)
 #define CAN1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x10000)
 #define CAN2_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x14000)
 /* QOSC on i.MX6SLL */
 #define QOSC_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x14000)
 #define GPT1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x18000)
 #define GPIO1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x1C000)
 #define GPIO2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x20000)
 #define GPIO3_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x24000)
 #define GPIO4_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x28000)
 #define GPIO5_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x2C000)
 #define MX6UL_SNVS_LP_BASE_ADDR     (AIPS1_OFF_BASE_ADDR + 0x30000)
 #define GPIO6_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x30000)
 #define GPIO7_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x34000)
 #define KPP_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x38000)
 #define WDOG1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x3C000)
 #define WDOG2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x40000)
 #define ANATOP_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x48000)
 #define USB_PHY0_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x49000)
 #define USB_PHY1_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x4a000)
 #define CCM_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x44000)
 #define SNVS_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x4C000)
 #define EPIT1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x50000)
 #define EPIT2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x54000)
 #define SRC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x58000)
 #define GPC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x5C000)
 #define IOMUXC_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x60000)
 #define IOMUXC_GPR_BASE_ADDR        (AIPS1_OFF_BASE_ADDR + 0x64000)
 #ifdef CONFIG_MX6SLL
 #define CSI_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x68000)
 #define SDMA_PORT_HOST_BASE_ADDR    (AIPS1_OFF_BASE_ADDR + 0x6C000)
 #define PXP_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x70000)
 #define EPDC_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x74000)
 #define DCP_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x7C000)
 #elif defined(CONFIG_MX6SL)
 #define CSI_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x64000)
 #define SIPIX_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x68000)
 #define SDMA_PORT_HOST_BASE_ADDR    (AIPS1_OFF_BASE_ADDR + 0x6C000)
 #elif defined(CONFIG_MX6SX)
 #define CANFD1_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x68000)
 #define SDMA_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x6C000)
 #define CANFD2_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x70000)
 #define SEMAPHORE1_BASE_ADDR        (AIPS1_OFF_BASE_ADDR + 0x74000)
 #define SEMAPHORE2_BASE_ADDR        (AIPS1_OFF_BASE_ADDR + 0x78000)
 #define RDC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x7C000)
 #else
 #define DCIC1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x64000)
 #define DCIC2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x68000)
 #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
 #endif
 #define MX6SL_LCDIF_BASE_ADDR      (AIPS1_OFF_BASE_ADDR + 0x78000)
 #define MX6SLL_LCDIF_BASE_ADDR      (AIPS1_OFF_BASE_ADDR + 0x78000)
 #define AIPS2_ON_BASE_ADDR          (ATZ2_BASE_ADDR + 0x7C000)
 #define AIPS2_OFF_BASE_ADDR         (ATZ2_BASE_ADDR + 0x80000)
 #define AIPS3_ON_BASE_ADDR          (ATZ3_BASE_ADDR + 0x7C000)
 #define AIPS3_OFF_BASE_ADDR         (ATZ3_BASE_ADDR + 0x80000)
 #define CAAM_BASE_ADDR              (ATZ2_BASE_ADDR)
 #define ARM_BASE_ADDR		    (ATZ2_BASE_ADDR + 0x40000)
 #define CONFIG_SYS_FSL_SEC_OFFSET   0
 #define CONFIG_SYS_FSL_SEC_ADDR     (CAAM_BASE_ADDR + \
 				     CONFIG_SYS_FSL_SEC_OFFSET)
 #define CONFIG_SYS_FSL_JR0_OFFSET   0x1000
 #define CONFIG_SYS_FSL_JR0_ADDR     (CAAM_BASE_ADDR + \
 				     CONFIG_SYS_FSL_JR0_OFFSET)
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC	1
 #define USB_PL301_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x0000)
 #define USB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x4000)
 #define ENET_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x8000)
 #ifdef CONFIG_MX6SL
 #define MSHC_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0xC000)
 #else
 #define MLB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0xC000)
 #endif
 #define USDHC1_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x10000)
 #define USDHC2_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x14000)
 #define USDHC3_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x18000)
 #define USDHC4_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x1C000)
 #define I2C1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x20000)
 #define I2C2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x24000)
 #define I2C3_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x28000)
 #define ROMCP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x2C000)
 #define MMDC_P0_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x30000)
 /* i.MX6SL/SLL */
 #define RNGB_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x34000)
-#ifdef CONFIG_MX6UL
+#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
 #define ENET2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x34000)
 #else
 /* i.MX6SX */
 #define ENET2_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x34000)
 #endif
 /* i.MX6DQ/SDL */
 #define MMDC_P1_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x34000)
 #define WEIM_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x38000)
 #define OCOTP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x3C000)
 #define CSU_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x40000)
 #ifdef CONFIG_MX6SLL
 #define IOMUXC_GPR_SNVS_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x44000)
 #define IOMUXC_SNVS_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x48000)
 #endif
 #define IP2APB_PERFMON1_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x44000)
 #define IP2APB_PERFMON2_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x48000)
 #define MX6UL_LCDIF1_BASE_ADDR      (AIPS2_OFF_BASE_ADDR + 0x48000)
 #define MX6ULL_LCDIF1_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x48000)
 #ifdef CONFIG_MX6SX
 #define DEBUG_MONITOR_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x4C000)
 #else
 #define IP2APB_PERFMON3_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x4C000)
 #endif
 #define IP2APB_TZASC1_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x50000)
-#ifdef CONFIG_MX6UL
+#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
 #define QSPI0_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
 #define UART6_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x7C000)
 #elif defined(CONFIG_MX6SX)
 #define SAI1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x54000)
 #define AUDMUX_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x58000)
 #define SAI2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x5C000)
 #define QSPI0_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
 #define QSPI1_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x64000)
 #else
 #define IP2APB_TZASC2_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x54000)
 #define MIPI_CSI2_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x5C000)
 #define MIPI_DSI_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x60000)
 #define VDOA_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x64000)
 #endif
 #define MX6UL_WDOG3_BASE_ADDR       (AIPS2_OFF_BASE_ADDR + 0x64000)
 #define UART2_BASE                  (AIPS2_OFF_BASE_ADDR + 0x68000)
 #define UART3_BASE                  (AIPS2_OFF_BASE_ADDR + 0x6C000)
 #define UART4_BASE                  (AIPS2_OFF_BASE_ADDR + 0x70000)
 #define UART5_BASE                  (AIPS2_OFF_BASE_ADDR + 0x74000)
 #define I2C4_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x78000)
 #define IP2APB_USBPHY1_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x78000)
 #define IP2APB_USBPHY2_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x7C000)
 /* i.MX6SLL */
 #define MTR_MASTER_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x7C000)
 #ifdef CONFIG_MX6SX
 #define GIS_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x04000)
 #define DCIC1_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x0C000)
 #define DCIC2_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x10000)
 #define CSI1_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x14000)
 #define PXP_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x18000)
 #define CSI2_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x1C000)
 #define VADC_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x28000)
 #define VDEC_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x2C000)
 #define SPBA_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x3C000)
 #define AIPS3_CONFIG_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x7C000)
 #define ADC1_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x80000)
 #define ADC2_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x84000)
 #define ECSPI5_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x8C000)
 #define HS_BASE_ADDR                (AIPS3_ARB_BASE_ADDR + 0x90000)
 #define MU_MCU_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x94000)
 #define CANFD_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x98000)
 #define MU_DSP_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x9C000)
 #define UART6_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0xA0000)
 #define PWM5_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xA4000)
 #define PWM6_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xA8000)
 #define PWM7_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xAC000)
 #define PWM8_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xB0000)
-#elif defined(CONFIG_MX6ULL)
+#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
 #define AIPS3_CONFIG_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x7C000)
 #define DCP_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x80000)
 #define RNGB_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x84000)
 #define UART8_IPS_BASE_ADDR         (AIPS3_ARB_BASE_ADDR + 0x88000)
 #define EPDC_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x8C000)
 #define IOMUXC_SNVS_BASE_ADDR       (AIPS3_ARB_BASE_ADDR + 0x90000)
 #define SNVS_GPR_BASE_ADDR          (AIPS3_ARB_BASE_ADDR + 0x94000)
 #endif
 #define NOC_DDR_BASE_ADDR           (GPV0_BASE_ADDR + 0xB0000)
 /* Only for i.MX6SX */
 #define LCDIF2_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x24000)
 #define MX6SX_LCDIF1_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x20000)
 #define MX6SX_WDOG3_BASE_ADDR       (AIPS3_ARB_BASE_ADDR + 0x88000)
-#if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
+#if !(defined(CONFIG_MX6SX) || \
+	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
 	defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL))
 #define IRAM_SIZE                    0x00040000
 #else
 #define IRAM_SIZE                    0x00020000
 #endif
 #define FEC_QUIRK_ENET_MAC
 #include <asm/mach-imx/regs-lcdif.h>
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 #include <asm/types.h>
 /* only for i.MX6SX/UL */
 #define WDOG3_BASE_ADDR (((is_mx6ul() || is_mx6ull()) ?	\
 			 MX6UL_WDOG3_BASE_ADDR :  MX6SX_WDOG3_BASE_ADDR))
 #define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6SLL)) ?	\
 			  MX6SLL_LCDIF_BASE_ADDR :		\
 			  (is_cpu_type(MXC_CPU_MX6SL)) ?	\
 			  MX6SL_LCDIF_BASE_ADDR :		\
 			  ((is_cpu_type(MXC_CPU_MX6UL)) ?	\
 			  MX6UL_LCDIF1_BASE_ADDR :		\
 			  ((is_mx6ull()) ?	\
 			  MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)))
 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
 #define SRC_SCR_CORE_1_RESET_OFFSET     14
 #define SRC_SCR_CORE_1_RESET_MASK       (1<<SRC_SCR_CORE_1_RESET_OFFSET)
 #define SRC_SCR_CORE_2_RESET_OFFSET     15
 #define SRC_SCR_CORE_2_RESET_MASK       (1<<SRC_SCR_CORE_2_RESET_OFFSET)
 #define SRC_SCR_CORE_3_RESET_OFFSET     16
 #define SRC_SCR_CORE_3_RESET_MASK       (1<<SRC_SCR_CORE_3_RESET_OFFSET)
 #define SRC_SCR_CORE_1_ENABLE_OFFSET    22
 #define SRC_SCR_CORE_1_ENABLE_MASK      (1<<SRC_SCR_CORE_1_ENABLE_OFFSET)
 #define SRC_SCR_CORE_2_ENABLE_OFFSET    23
 #define SRC_SCR_CORE_2_ENABLE_MASK      (1<<SRC_SCR_CORE_2_ENABLE_OFFSET)
 #define SRC_SCR_CORE_3_ENABLE_OFFSET    24
 #define SRC_SCR_CORE_3_ENABLE_MASK      (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
 struct rdc_regs {
 	u32	vir;		/* Version information */
 	u32	reserved1[8];
 	u32	stat;		/* Status */
 	u32	intctrl;	/* Interrupt and Control */
 	u32	intstat;	/* Interrupt Status */
 	u32	reserved2[116];
 	u32	mda[32];	/* Master Domain Assignment */
 	u32	reserved3[96];
 	u32	pdap[104];	/* Peripheral Domain Access Permissions */
 	u32	reserved4[88];
 	struct {
 		u32 mrsa;	/* Memory Region Start Address */
 		u32 mrea;	/* Memory Region End Address */
 		u32 mrc;	/* Memory Region Control */
 		u32 mrvs;	/* Memory Region Violation Status */
 	} mem_region[55];
 };
 struct rdc_sema_regs {
 	u8	gate[64];	/* Gate */
 	u16	rstgt;		/* Reset Gate */
 };
 /* WEIM registers */
 struct weim {
 	u32 cs0gcr1;
 	u32 cs0gcr2;
 	u32 cs0rcr1;
 	u32 cs0rcr2;
 	u32 cs0wcr1;
 	u32 cs0wcr2;
 	u32 cs1gcr1;
 	u32 cs1gcr2;
 	u32 cs1rcr1;
 	u32 cs1rcr2;
 	u32 cs1wcr1;
 	u32 cs1wcr2;
 	u32 cs2gcr1;
 	u32 cs2gcr2;
 	u32 cs2rcr1;
 	u32 cs2rcr2;
 	u32 cs2wcr1;
 	u32 cs2wcr2;
 	u32 cs3gcr1;
 	u32 cs3gcr2;
 	u32 cs3rcr1;
 	u32 cs3rcr2;
 	u32 cs3wcr1;
 	u32 cs3wcr2;
 	u32 unused[12];
 	u32 wcr;
 	u32 wiar;
 	u32 ear;
 };
 /* System Reset Controller (SRC) */
 struct src {
 	u32	scr;
 	u32	sbmr1;
 	u32	srsr;
 	u32	reserved1[2];
 	u32	sisr;
 	u32	simr;
 	u32     sbmr2;
 	u32     gpr1;
 	u32     gpr2;
 	u32     gpr3;
 	u32     gpr4;
 	u32     gpr5;
 	u32     gpr6;
 	u32     gpr7;
 	u32     gpr8;
 	u32     gpr9;
 	u32     gpr10;
 };
 #define src_base ((struct src *)SRC_BASE_ADDR)
 #define SRC_SCR_M4_ENABLE_OFFSET                22
 #define SRC_SCR_M4_ENABLE_MASK                  (1 << 22)
 #define SRC_SCR_M4C_NON_SCLR_RST_OFFSET         4
 #define SRC_SCR_M4C_NON_SCLR_RST_MASK           (1 << 4)
 /* GPR1 bitfields */
 #define IOMUXC_GPR1_APP_CLK_REQ_N		BIT(30)
 #define IOMUXC_GPR1_PCIE_EXIT_L1		BIT(28)
 #define IOMUXC_GPR1_PCIE_RDY_L23		BIT(27)
 #define IOMUXC_GPR1_PCIE_ENTER_L1		BIT(26)
 #define IOMUXC_GPR1_MIPI_COLOR_SW		BIT(25)
 #define IOMUXC_GPR1_DPI_OFF			BIT(24)
 #define IOMUXC_GPR1_EXC_MON_SLVE		BIT(22)
 #define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET		21
 #define IOMUXC_GPR1_ENET_CLK_SEL_MASK		(1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
 #define IOMUXC_GPR1_MIPI_IPU2_MUX_IOMUX		BIT(20)
 #define IOMUXC_GPR1_MIPI_IPU1_MUX_IOMUX		BIT(19)
 #define IOMUXC_GPR1_PCIE_TEST_PD			BIT(18)
 #define IOMUXC_GPR1_IPU_VPU_MUX_IPU2		BIT(17)
 #define IOMUXC_GPR1_PCIE_REF_CLK_EN		BIT(16)
 #define IOMUXC_GPR1_USB_EXP_MODE			BIT(15)
 #define IOMUXC_GPR1_PCIE_INT			BIT(14)
 #define IOMUXC_GPR1_USB_OTG_ID_OFFSET		13
 #define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK		(1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET)
 #define IOMUXC_GPR1_GINT				BIT(12)
 #define IOMUXC_GPR1_ADDRS3_MASK			(0x3 << 10)
 #define IOMUXC_GPR1_ADDRS3_32MB			(0x0 << 10)
 #define IOMUXC_GPR1_ADDRS3_64MB			(0x1 << 10)
 #define IOMUXC_GPR1_ADDRS3_128MB			(0x2 << 10)
 #define IOMUXC_GPR1_ACT_CS3			BIT(9)
 #define IOMUXC_GPR1_ADDRS2_MASK			(0x3 << 7)
 #define IOMUXC_GPR1_ACT_CS2			BIT(6)
 #define IOMUXC_GPR1_ADDRS1_MASK			(0x3 << 4)
 #define IOMUXC_GPR1_ACT_CS1			BIT(3)
 #define IOMUXC_GPR1_ADDRS0_OFFSET		(1)
 #define IOMUXC_GPR1_ADDRS0_MASK			(0x3 << 1)
 #define IOMUXC_GPR1_ACT_CS0			BIT(0)
 /* GPR3 bitfields */
 #define IOMUXC_GPR3_GPU_DBG_OFFSET		29
 #define IOMUXC_GPR3_GPU_DBG_MASK		(3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET	28
 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK	(1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET	27
 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK	(1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET	26
 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK	(1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET	25
 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK	(1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
 #define IOMUXC_GPR3_OCRAM_CTL_OFFSET		21
 #define IOMUXC_GPR3_OCRAM_CTL_MASK		(0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
 #define IOMUXC_GPR3_OCRAM_STATUS_OFFSET		17
 #define IOMUXC_GPR3_OCRAM_STATUS_MASK		(0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET	16
 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK	(1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET	15
 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK	(1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET	14
 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK	(1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET	13
 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK	(1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET	12
 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK	(1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET	11
 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK	(1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
 #define IOMUXC_GPR3_IPU_DIAG_OFFSET		10
 #define IOMUXC_GPR3_IPU_DIAG_MASK		(1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI0	0
 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI1	1
 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI0	2
 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI1	3
 #define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET	8
 #define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK		(3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
 #define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET	6
 #define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK		(3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
 #define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET		4
 #define IOMUXC_GPR3_MIPI_MUX_CTL_MASK		(3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
 #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET		2
 #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK		(3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
 /* gpr12 bitfields */
 #define IOMUXC_GPR12_ARMP_IPG_CLK_EN		BIT(27)
 #define IOMUXC_GPR12_ARMP_AHB_CLK_EN		BIT(26)
 #define IOMUXC_GPR12_ARMP_ATB_CLK_EN		BIT(25)
 #define IOMUXC_GPR12_ARMP_APB_CLK_EN		BIT(24)
 #define IOMUXC_GPR12_DEVICE_TYPE		(0xf << 12)
 #define IOMUXC_GPR12_PCIE_CTL_2			BIT(10)
 #define IOMUXC_GPR12_LOS_LEVEL			(0x1f << 4)
 struct iomuxc {
-#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
+#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
 	u8 reserved[0x4000];
 #endif
 	u32 gpr[14];
 };
 struct gpc {
 	u32	cntr;
 	u32	pgr;
 	u32	imr1;
 	u32	imr2;
 	u32	imr3;
 	u32	imr4;
 	u32	isr1;
 	u32	isr2;
 	u32	isr3;
 	u32	isr4;
 };
 #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET		20
 #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK		(3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET		16
 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK			(7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
 #define IOMUXC_GPR2_BGREF_RRMODE_OFFSET			15
 #define IOMUXC_GPR2_BGREF_RRMODE_MASK			(1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
 #define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES		(1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
 #define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES		(0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
 #define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH	0
 #define IOMUXC_GPR2_VSYNC_ACTIVE_LOW	1
 #define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET		10
 #define IOMUXC_GPR2_DI1_VS_POLARITY_MASK		(1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH		(IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW		(IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
 #define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET		9
 #define IOMUXC_GPR2_DI0_VS_POLARITY_MASK		(1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH		(IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW		(IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
 #define IOMUXC_GPR2_BITMAP_SPWG	0
 #define IOMUXC_GPR2_BITMAP_JEIDA	1
 #define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET		8
 #define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK		(1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
 #define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA		(IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
 #define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG		(IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
 #define IOMUXC_GPR2_DATA_WIDTH_18	0
 #define IOMUXC_GPR2_DATA_WIDTH_24	1
 #define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET		7
 #define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK			(1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
 #define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT		(IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
 #define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT		(IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
 #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET		6
 #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK		(1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
 #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA		(IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
 #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG		(IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
 #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET		5
 #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK			(1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
 #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT		(IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
 #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT		(IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
 #define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET		4
 #define IOMUXC_GPR2_SPLIT_MODE_EN_MASK			(1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
 #define IOMUXC_GPR2_MODE_DISABLED	0
 #define IOMUXC_GPR2_MODE_ENABLED_DI0	1
 #define IOMUXC_GPR2_MODE_ENABLED_DI1	3
 #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET		2
 #define IOMUXC_GPR2_LVDS_CH1_MODE_MASK			(3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
 #define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED		(IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0		(IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1		(IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
 #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET		0
 #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK			(3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
 #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED		(IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0		(IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1		(IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
 /* ECSPI registers */
 struct cspi_regs {
 	u32 rxdata;
 	u32 txdata;
 	u32 ctrl;
 	u32 cfg;
 	u32 intr;
 	u32 dma;
 	u32 stat;
 	u32 period;
 };
 /*
  * CSPI register definitions
  */
 #define MXC_ECSPI
 #define MXC_CSPICTRL_EN		(1 << 0)
 #define MXC_CSPICTRL_MODE	(1 << 1)
 #define MXC_CSPICTRL_XCH	(1 << 2)
 #define MXC_CSPICTRL_MODE_MASK (0xf << 4)
 #define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
 #define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
 #define MXC_CSPICTRL_PREDIV(x)	(((x) & 0xF) << 12)
 #define MXC_CSPICTRL_POSTDIV(x)	(((x) & 0xF) << 8)
 #define MXC_CSPICTRL_SELCHAN(x)	(((x) & 0x3) << 18)
 #define MXC_CSPICTRL_MAXBITS	0xfff
 #define MXC_CSPICTRL_TC		(1 << 7)
 #define MXC_CSPICTRL_RXOVF	(1 << 6)
 #define MXC_CSPIPERIOD_32KHZ	(1 << 15)
 #define MAX_SPI_BYTES	32
 #define SPI_MAX_NUM	4
 /* Bit position inside CTRL register to be associated with SS */
 #define MXC_CSPICTRL_CHAN	18
 /* Bit position inside CON register to be associated with SS */
 #define MXC_CSPICON_PHA		0  /* SCLK phase control */
 #define MXC_CSPICON_POL		4  /* SCLK polarity */
 #define MXC_CSPICON_SSPOL	12 /* SS polarity */
 #define MXC_CSPICON_CTL		20 /* inactive state of SCLK */
 #if defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
-	defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL)
+	defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
 #define MXC_SPI_BASE_ADDRESSES \
 	ECSPI1_BASE_ADDR, \
 	ECSPI2_BASE_ADDR, \
 	ECSPI3_BASE_ADDR, \
 	ECSPI4_BASE_ADDR
 #else
 #define MXC_SPI_BASE_ADDRESSES \
 	ECSPI1_BASE_ADDR, \
 	ECSPI2_BASE_ADDR, \
 	ECSPI3_BASE_ADDR, \
 	ECSPI4_BASE_ADDR, \
 	ECSPI5_BASE_ADDR
 #endif
 struct ocotp_regs {
 	u32	ctrl;
 	u32	ctrl_set;
 	u32     ctrl_clr;
 	u32	ctrl_tog;
 	u32	timing;
 	u32     rsvd0[3];
 	u32     data;
 	u32     rsvd1[3];
 	u32     read_ctrl;
 	u32     rsvd2[3];
 	u32	read_fuse_data;
 	u32     rsvd3[3];
 	u32	sw_sticky;
 	u32     rsvd4[3];
 	u32     scs;
 	u32     scs_set;
 	u32     scs_clr;
 	u32     scs_tog;
 	u32     crc_addr;
 	u32     rsvd5[3];
 	u32     crc_value;
 	u32     rsvd6[3];
 	u32     version;
 	u32     rsvd7[0xdb];
 	/* fuse banks */
 	struct fuse_bank {
 		u32	fuse_regs[0x20];
 	} bank[0];
 };
 struct fuse_bank0_regs {
 	u32	lock;
 	u32	rsvd0[3];
 	u32	uid_low;
 	u32	rsvd1[3];
 	u32	uid_high;
 	u32	rsvd2[3];
 	u32	cfg2;
 	u32	rsvd3[3];
 	u32	cfg3;
 	u32	rsvd4[3];
 	u32	cfg4;
 	u32	rsvd5[3];
 	u32	cfg5;
 	u32	rsvd6[3];
 	u32	cfg6;
 	u32	rsvd7[3];
 };
 struct fuse_bank1_regs {
 	u32	mem0;
 	u32	rsvd0[3];
 	u32	mem1;
 	u32	rsvd1[3];
 	u32	mem2;
 	u32	rsvd2[3];
 	u32	mem3;
 	u32	rsvd3[3];
 	u32	mem4;
 	u32	rsvd4[3];
 	u32	ana0;
 	u32	rsvd5[3];
 	u32	ana1;
 	u32	rsvd6[3];
 	u32	ana2;
 	u32	rsvd7[3];
 };
 struct fuse_bank4_regs {
 	u32 sjc_resp_low;
 	u32 rsvd0[3];
 	u32 sjc_resp_high;
 	u32 rsvd1[3];
 	u32 mac_addr0;
 	u32 rsvd2[3];
 	u32 mac_addr1;
 	u32 rsvd3[3];
 	u32 mac_addr2; /*For i.MX6SX and i.MX6UL*/
 	u32 rsvd4[7];
 	u32 gp1;
 	u32 rsvd5[3];
 	u32 gp2;
 	u32 rsvd6[3];
 };
 struct aipstz_regs {
 	u32	mprot0;
 	u32	mprot1;
 	u32	rsvd[0xe];
 	u32	opacr0;
 	u32	opacr1;
 	u32	opacr2;
 	u32	opacr3;
 	u32	opacr4;
 };
 struct anatop_regs {
 	u32	pll_sys;		/* 0x000 */
 	u32	pll_sys_set;		/* 0x004 */
 	u32	pll_sys_clr;		/* 0x008 */
 	u32	pll_sys_tog;		/* 0x00c */
 	u32	usb1_pll_480_ctrl;	/* 0x010 */
 	u32	usb1_pll_480_ctrl_set;	/* 0x014 */
 	u32	usb1_pll_480_ctrl_clr;	/* 0x018 */
 	u32	usb1_pll_480_ctrl_tog;	/* 0x01c */
 	u32	usb2_pll_480_ctrl;	/* 0x020 */
 	u32	usb2_pll_480_ctrl_set;	/* 0x024 */
 	u32	usb2_pll_480_ctrl_clr;	/* 0x028 */
 	u32	usb2_pll_480_ctrl_tog;	/* 0x02c */
 	u32	pll_528;		/* 0x030 */
 	u32	pll_528_set;		/* 0x034 */
 	u32	pll_528_clr;		/* 0x038 */
 	u32	pll_528_tog;		/* 0x03c */
 	u32	pll_528_ss;		/* 0x040 */
 	u32	rsvd0[3];
 	u32	pll_528_num;		/* 0x050 */
 	u32	rsvd1[3];
 	u32	pll_528_denom;		/* 0x060 */
 	u32	rsvd2[3];
 	u32	pll_audio;		/* 0x070 */
 	u32	pll_audio_set;		/* 0x074 */
 	u32	pll_audio_clr;		/* 0x078 */
 	u32	pll_audio_tog;		/* 0x07c */
 	u32	pll_audio_num;		/* 0x080 */
 	u32	rsvd3[3];
 	u32	pll_audio_denom;	/* 0x090 */
 	u32	rsvd4[3];
 	u32	pll_video;		/* 0x0a0 */
 	u32	pll_video_set;		/* 0x0a4 */
 	u32	pll_video_clr;		/* 0x0a8 */
 	u32	pll_video_tog;		/* 0x0ac */
 	u32	pll_video_num;		/* 0x0b0 */
 	u32	rsvd5[3];
 	u32	pll_video_denom;	/* 0x0c0 */
 	u32	rsvd6[3];
 	u32	pll_mlb;		/* 0x0d0 */
 	u32	pll_mlb_set;		/* 0x0d4 */
 	u32	pll_mlb_clr;		/* 0x0d8 */
 	u32	pll_mlb_tog;		/* 0x0dc */
 	u32	pll_enet;		/* 0x0e0 */
 	u32	pll_enet_set;		/* 0x0e4 */
 	u32	pll_enet_clr;		/* 0x0e8 */
 	u32	pll_enet_tog;		/* 0x0ec */
 	u32	pfd_480;		/* 0x0f0 */
 	u32	pfd_480_set;		/* 0x0f4 */
 	u32	pfd_480_clr;		/* 0x0f8 */
 	u32	pfd_480_tog;		/* 0x0fc */
 	u32	pfd_528;		/* 0x100 */
 	u32	pfd_528_set;		/* 0x104 */
 	u32	pfd_528_clr;		/* 0x108 */
 	u32	pfd_528_tog;		/* 0x10c */
 	u32	reg_1p1;		/* 0x110 */
 	u32	reg_1p1_set;		/* 0x114 */
 	u32	reg_1p1_clr;		/* 0x118 */
 	u32	reg_1p1_tog;		/* 0x11c */
 	u32	reg_3p0;		/* 0x120 */
 	u32	reg_3p0_set;		/* 0x124 */
 	u32	reg_3p0_clr;		/* 0x128 */
 	u32	reg_3p0_tog;		/* 0x12c */
 	u32	reg_2p5;		/* 0x130 */
 	u32	reg_2p5_set;		/* 0x134 */
 	u32	reg_2p5_clr;		/* 0x138 */
 	u32	reg_2p5_tog;		/* 0x13c */
 	u32	reg_core;		/* 0x140 */
 	u32	reg_core_set;		/* 0x144 */
 	u32	reg_core_clr;		/* 0x148 */
 	u32	reg_core_tog;		/* 0x14c */
 	u32	ana_misc0;		/* 0x150 */
 	u32	ana_misc0_set;		/* 0x154 */
 	u32	ana_misc0_clr;		/* 0x158 */
 	u32	ana_misc0_tog;		/* 0x15c */
 	u32	ana_misc1;		/* 0x160 */
 	u32	ana_misc1_set;		/* 0x164 */
 	u32	ana_misc1_clr;		/* 0x168 */
 	u32	ana_misc1_tog;		/* 0x16c */
 	u32	ana_misc2;		/* 0x170 */
 	u32	ana_misc2_set;		/* 0x174 */
 	u32	ana_misc2_clr;		/* 0x178 */
 	u32	ana_misc2_tog;		/* 0x17c */
 	u32	tempsense0;		/* 0x180 */
 	u32	tempsense0_set;		/* 0x184 */
 	u32	tempsense0_clr;		/* 0x188 */
 	u32	tempsense0_tog;		/* 0x18c */
 	u32	tempsense1;		/* 0x190 */
 	u32	tempsense1_set;		/* 0x194 */
 	u32	tempsense1_clr;		/* 0x198 */
 	u32	tempsense1_tog;		/* 0x19c */
 	u32	usb1_vbus_detect;	/* 0x1a0 */
 	u32	usb1_vbus_detect_set;	/* 0x1a4 */
 	u32	usb1_vbus_detect_clr;	/* 0x1a8 */
 	u32	usb1_vbus_detect_tog;	/* 0x1ac */
 	u32	usb1_chrg_detect;	/* 0x1b0 */
 	u32	usb1_chrg_detect_set;	/* 0x1b4 */
 	u32	usb1_chrg_detect_clr;	/* 0x1b8 */
 	u32	usb1_chrg_detect_tog;	/* 0x1bc */
 	u32	usb1_vbus_det_stat;	/* 0x1c0 */
 	u32	usb1_vbus_det_stat_set;	/* 0x1c4 */
 	u32	usb1_vbus_det_stat_clr;	/* 0x1c8 */
 	u32	usb1_vbus_det_stat_tog;	/* 0x1cc */
 	u32	usb1_chrg_det_stat;	/* 0x1d0 */
 	u32	usb1_chrg_det_stat_set;	/* 0x1d4 */
 	u32	usb1_chrg_det_stat_clr;	/* 0x1d8 */
 	u32	usb1_chrg_det_stat_tog;	/* 0x1dc */
 	u32	usb1_loopback;		/* 0x1e0 */
 	u32	usb1_loopback_set;	/* 0x1e4 */
 	u32	usb1_loopback_clr;	/* 0x1e8 */
 	u32	usb1_loopback_tog;	/* 0x1ec */
 	u32	usb1_misc;		/* 0x1f0 */
 	u32	usb1_misc_set;		/* 0x1f4 */
 	u32	usb1_misc_clr;		/* 0x1f8 */
 	u32	usb1_misc_tog;		/* 0x1fc */
 	u32	usb2_vbus_detect;	/* 0x200 */
 	u32	usb2_vbus_detect_set;	/* 0x204 */
 	u32	usb2_vbus_detect_clr;	/* 0x208 */
 	u32	usb2_vbus_detect_tog;	/* 0x20c */
 	u32	usb2_chrg_detect;	/* 0x210 */
 	u32	usb2_chrg_detect_set;	/* 0x214 */
 	u32	usb2_chrg_detect_clr;	/* 0x218 */
 	u32	usb2_chrg_detect_tog;	/* 0x21c */
 	u32	usb2_vbus_det_stat;	/* 0x220 */
 	u32	usb2_vbus_det_stat_set;	/* 0x224 */
 	u32	usb2_vbus_det_stat_clr;	/* 0x228 */
 	u32	usb2_vbus_det_stat_tog;	/* 0x22c */
 	u32	usb2_chrg_det_stat;	/* 0x230 */
 	u32	usb2_chrg_det_stat_set;	/* 0x234 */
 	u32	usb2_chrg_det_stat_clr;	/* 0x238 */
 	u32	usb2_chrg_det_stat_tog;	/* 0x23c */
 	u32	usb2_loopback;		/* 0x240 */
 	u32	usb2_loopback_set;	/* 0x244 */
 	u32	usb2_loopback_clr;	/* 0x248 */
 	u32	usb2_loopback_tog;	/* 0x24c */
 	u32	usb2_misc;		/* 0x250 */
 	u32	usb2_misc_set;		/* 0x254 */
 	u32	usb2_misc_clr;		/* 0x258 */
 	u32	usb2_misc_tog;		/* 0x25c */
 	u32	digprog;		/* 0x260 */
 	u32	reserved1[7];
 	u32	digprog_sololite;	/* 0x280 */
 };
 #define ANATOP_PFD_FRAC_SHIFT(n)	((n)*8)
 #define ANATOP_PFD_FRAC_MASK(n)	(0x3f<<ANATOP_PFD_FRAC_SHIFT(n))
 #define ANATOP_PFD_STABLE_SHIFT(n)	(6+((n)*8))
 #define ANATOP_PFD_STABLE_MASK(n)	(1<<ANATOP_PFD_STABLE_SHIFT(n))
 #define ANATOP_PFD_CLKGATE_SHIFT(n)	(7+((n)*8))
 #define ANATOP_PFD_CLKGATE_MASK(n)	(1<<ANATOP_PFD_CLKGATE_SHIFT(n))
 struct wdog_regs {
 	u16	wcr;	/* Control */
 	u16	wsr;	/* Service */
 	u16	wrsr;	/* Reset Status */
 	u16	wicr;	/* Interrupt Control */
 	u16	wmcr;	/* Miscellaneous Control */
 };
 #define PWMCR_PRESCALER(x)	(((x - 1) & 0xFFF) << 4)
 #define PWMCR_DOZEEN		(1 << 24)
 #define PWMCR_WAITEN		(1 << 23)
 #define PWMCR_DBGEN		(1 << 22)
 #define PWMCR_CLKSRC_IPG_HIGH	(2 << 16)
 #define PWMCR_CLKSRC_IPG	(1 << 16)
 #define PWMCR_EN		(1 << 0)
 struct pwm_regs {
 	u32	cr;
 	u32	sr;
 	u32	ir;
 	u32	sar;
 	u32	pr;
 	u32	cnr;
 };
 #endif /* __ASSEMBLER__*/
 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */

arch/arm/include/asm/arch-mx6/mx6-ddr.h

Diff comments View file @ 290e7cf

1	/*	1	/*
2	* Copyright (C) 2013 Boundary Devices Inc.	2	* Copyright (C) 2013 Boundary Devices Inc.
3	*	3	*
4	* SPDX-License-Identifier: GPL-2.0+	4	* SPDX-License-Identifier: GPL-2.0+
5	*/	5	*/
6	#ifndef __ASM_ARCH_MX6_DDR_H__	6	#ifndef __ASM_ARCH_MX6_DDR_H__
7	#define __ASM_ARCH_MX6_DDR_H__	7	#define __ASM_ARCH_MX6_DDR_H__
8		8
9	#ifndef CONFIG_SPL_BUILD	9	#ifndef CONFIG_SPL_BUILD
10	#ifdef CONFIG_MX6Q	10	#ifdef CONFIG_MX6Q
11	#include "mx6q-ddr.h"	11	#include "mx6q-ddr.h"
12	#else	12	#else
13	#if defined(CONFIG_MX6DL) \|\| defined(CONFIG_MX6S)	13	#if defined(CONFIG_MX6DL) \|\| defined(CONFIG_MX6S)
14	#include "mx6dl-ddr.h"	14	#include "mx6dl-ddr.h"
15	#else	15	#else
16	#ifdef CONFIG_MX6SX	16	#ifdef CONFIG_MX6SX
17	#include "mx6sx-ddr.h"	17	#include "mx6sx-ddr.h"
18	#else	18	#else
19	#ifdef CONFIG_MX6UL	19	#if defined(CONFIG_MX6UL) \|\| defined(CONFIG_MX6ULL)
20	#include "mx6ul-ddr.h"	20	#include "mx6ul-ddr.h"
21	#else	21	#else
22	#ifdef CONFIG_MX6SL	22	#ifdef CONFIG_MX6SL
23	#include "mx6sl-ddr.h"	23	#include "mx6sl-ddr.h"
24	#else	24	#else
25	#error "Please select cpu"	25	#error "Please select cpu"
26	#endif /* CONFIG_MX6SL */	26	#endif /* CONFIG_MX6SL */
27	#endif /* CONFIG_MX6UL */	27	#endif /* CONFIG_MX6UL */
28	#endif /* CONFIG_MX6SX */	28	#endif /* CONFIG_MX6SX */
29	#endif /* CONFIG_MX6DL or CONFIG_MX6S */	29	#endif /* CONFIG_MX6DL or CONFIG_MX6S */
30	#endif /* CONFIG_MX6Q */	30	#endif /* CONFIG_MX6Q */
31	#else	31	#else
32		32
33	enum {	33	enum {
34	DDR_TYPE_DDR3,	34	DDR_TYPE_DDR3,
35	DDR_TYPE_LPDDR2,	35	DDR_TYPE_LPDDR2,
36	};	36	};
37		37
38	/* MMDC P0/P1 Registers */	38	/* MMDC P0/P1 Registers */
39	struct mmdc_p_regs {	39	struct mmdc_p_regs {
40	u32 mdctl;	40	u32 mdctl;
41	u32 mdpdc;	41	u32 mdpdc;
42	u32 mdotc;	42	u32 mdotc;
43	u32 mdcfg0;	43	u32 mdcfg0;
44	u32 mdcfg1;	44	u32 mdcfg1;
45	u32 mdcfg2;	45	u32 mdcfg2;
46	u32 mdmisc;	46	u32 mdmisc;
47	u32 mdscr;	47	u32 mdscr;
48	u32 mdref;	48	u32 mdref;
49	u32 res1[2];	49	u32 res1[2];
50	u32 mdrwd;	50	u32 mdrwd;
51	u32 mdor;	51	u32 mdor;
52	u32 mdmrr;	52	u32 mdmrr;
53	u32 mdcfg3lp;	53	u32 mdcfg3lp;
54	u32 mdmr4;	54	u32 mdmr4;
55	u32 mdasp;	55	u32 mdasp;
56	u32 res2[239];	56	u32 res2[239];
57	u32 maarcr;	57	u32 maarcr;
58	u32 mapsr;	58	u32 mapsr;
59	u32 maexidr0;	59	u32 maexidr0;
60	u32 maexidr1;	60	u32 maexidr1;
61	u32 madpcr0;	61	u32 madpcr0;
62	u32 madpcr1;	62	u32 madpcr1;
63	u32 madpsr0;	63	u32 madpsr0;
64	u32 madpsr1;	64	u32 madpsr1;
65	u32 madpsr2;	65	u32 madpsr2;
66	u32 madpsr3;	66	u32 madpsr3;
67	u32 madpsr4;	67	u32 madpsr4;
68	u32 madpsr5;	68	u32 madpsr5;
69	u32 masbs0;	69	u32 masbs0;
70	u32 masbs1;	70	u32 masbs1;
71	u32 res3[2];	71	u32 res3[2];
72	u32 magenp;	72	u32 magenp;
73	u32 res4[239];	73	u32 res4[239];
74	u32 mpzqhwctrl;	74	u32 mpzqhwctrl;
75	u32 mpzqswctrl;	75	u32 mpzqswctrl;
76	u32 mpwlgcr;	76	u32 mpwlgcr;
77	u32 mpwldectrl0;	77	u32 mpwldectrl0;
78	u32 mpwldectrl1;	78	u32 mpwldectrl1;
79	u32 mpwldlst;	79	u32 mpwldlst;
80	u32 mpodtctrl;	80	u32 mpodtctrl;
81	u32 mprddqby0dl;	81	u32 mprddqby0dl;
82	u32 mprddqby1dl;	82	u32 mprddqby1dl;
83	u32 mprddqby2dl;	83	u32 mprddqby2dl;
84	u32 mprddqby3dl;	84	u32 mprddqby3dl;
85	u32 mpwrdqby0dl;	85	u32 mpwrdqby0dl;
86	u32 mpwrdqby1dl;	86	u32 mpwrdqby1dl;
87	u32 mpwrdqby2dl;	87	u32 mpwrdqby2dl;
88	u32 mpwrdqby3dl;	88	u32 mpwrdqby3dl;
89	u32 mpdgctrl0;	89	u32 mpdgctrl0;
90	u32 mpdgctrl1;	90	u32 mpdgctrl1;
91	u32 mpdgdlst0;	91	u32 mpdgdlst0;
92	u32 mprddlctl;	92	u32 mprddlctl;
93	u32 mprddlst;	93	u32 mprddlst;
94	u32 mpwrdlctl;	94	u32 mpwrdlctl;
95	u32 mpwrdlst;	95	u32 mpwrdlst;
96	u32 mpsdctrl;	96	u32 mpsdctrl;
97	u32 mpzqlp2ctl;	97	u32 mpzqlp2ctl;
98	u32 mprddlhwctl;	98	u32 mprddlhwctl;
99	u32 mpwrdlhwctl;	99	u32 mpwrdlhwctl;
100	u32 mprddlhwst0;	100	u32 mprddlhwst0;
101	u32 mprddlhwst1;	101	u32 mprddlhwst1;
102	u32 mpwrdlhwst0;	102	u32 mpwrdlhwst0;
103	u32 mpwrdlhwst1;	103	u32 mpwrdlhwst1;
104	u32 mpwlhwerr;	104	u32 mpwlhwerr;
105	u32 mpdghwst0;	105	u32 mpdghwst0;
106	u32 mpdghwst1;	106	u32 mpdghwst1;
107	u32 mpdghwst2;	107	u32 mpdghwst2;
108	u32 mpdghwst3;	108	u32 mpdghwst3;
109	u32 mppdcmpr1;	109	u32 mppdcmpr1;
110	u32 mppdcmpr2;	110	u32 mppdcmpr2;
111	u32 mpswdar0;	111	u32 mpswdar0;
112	u32 mpswdrdr0;	112	u32 mpswdrdr0;
113	u32 mpswdrdr1;	113	u32 mpswdrdr1;
114	u32 mpswdrdr2;	114	u32 mpswdrdr2;
115	u32 mpswdrdr3;	115	u32 mpswdrdr3;
116	u32 mpswdrdr4;	116	u32 mpswdrdr4;
117	u32 mpswdrdr5;	117	u32 mpswdrdr5;
118	u32 mpswdrdr6;	118	u32 mpswdrdr6;
119	u32 mpswdrdr7;	119	u32 mpswdrdr7;
120	u32 mpmur0;	120	u32 mpmur0;
121	u32 mpwrcadl;	121	u32 mpwrcadl;
122	u32 mpdccr;	122	u32 mpdccr;
123	};	123	};
124		124
125	#define MX6SL_IOM_DDR_BASE 0x020e0300	125	#define MX6SL_IOM_DDR_BASE 0x020e0300
126	struct mx6sl_iomux_ddr_regs {	126	struct mx6sl_iomux_ddr_regs {
127	u32 dram_cas;	127	u32 dram_cas;
128	u32 dram_cs0_b;	128	u32 dram_cs0_b;
129	u32 dram_cs1_b;	129	u32 dram_cs1_b;
130	u32 dram_dqm0;	130	u32 dram_dqm0;
131	u32 dram_dqm1;	131	u32 dram_dqm1;
132	u32 dram_dqm2;	132	u32 dram_dqm2;
133	u32 dram_dqm3;	133	u32 dram_dqm3;
134	u32 dram_ras;	134	u32 dram_ras;
135	u32 dram_reset;	135	u32 dram_reset;
136	u32 dram_sdba0;	136	u32 dram_sdba0;
137	u32 dram_sdba1;	137	u32 dram_sdba1;
138	u32 dram_sdba2;	138	u32 dram_sdba2;
139	u32 dram_sdcke0;	139	u32 dram_sdcke0;
140	u32 dram_sdcke1;	140	u32 dram_sdcke1;
141	u32 dram_sdclk_0;	141	u32 dram_sdclk_0;
142	u32 dram_odt0;	142	u32 dram_odt0;
143	u32 dram_odt1;	143	u32 dram_odt1;
144	u32 dram_sdqs0;	144	u32 dram_sdqs0;
145	u32 dram_sdqs1;	145	u32 dram_sdqs1;
146	u32 dram_sdqs2;	146	u32 dram_sdqs2;
147	u32 dram_sdqs3;	147	u32 dram_sdqs3;
148	u32 dram_sdwe_b;	148	u32 dram_sdwe_b;
149	};	149	};
150		150
151	#define MX6SL_IOM_GRP_BASE 0x020e0500	151	#define MX6SL_IOM_GRP_BASE 0x020e0500
152	struct mx6sl_iomux_grp_regs {	152	struct mx6sl_iomux_grp_regs {
153	u32 res1[43];	153	u32 res1[43];
154	u32 grp_addds;	154	u32 grp_addds;
155	u32 grp_ddrmode_ctl;	155	u32 grp_ddrmode_ctl;
156	u32 grp_ddrpke;	156	u32 grp_ddrpke;
157	u32 grp_ddrpk;	157	u32 grp_ddrpk;
158	u32 grp_ddrhys;	158	u32 grp_ddrhys;
159	u32 grp_ddrmode;	159	u32 grp_ddrmode;
160	u32 grp_b0ds;	160	u32 grp_b0ds;
161	u32 grp_ctlds;	161	u32 grp_ctlds;
162	u32 grp_b1ds;	162	u32 grp_b1ds;
163	u32 grp_ddr_type;	163	u32 grp_ddr_type;
164	u32 grp_b2ds;	164	u32 grp_b2ds;
165	u32 grp_b3ds;	165	u32 grp_b3ds;
166	};	166	};
167		167
168	#define MX6UL_IOM_DDR_BASE 0x020e0200	168	#define MX6UL_IOM_DDR_BASE 0x020e0200
169	struct mx6ul_iomux_ddr_regs {	169	struct mx6ul_iomux_ddr_regs {
170	u32 res1[17];	170	u32 res1[17];
171	u32 dram_dqm0;	171	u32 dram_dqm0;
172	u32 dram_dqm1;	172	u32 dram_dqm1;
173	u32 dram_ras;	173	u32 dram_ras;
174	u32 dram_cas;	174	u32 dram_cas;
175	u32 dram_cs0;	175	u32 dram_cs0;
176	u32 dram_cs1;	176	u32 dram_cs1;
177	u32 dram_sdwe_b;	177	u32 dram_sdwe_b;
178	u32 dram_odt0;	178	u32 dram_odt0;
179	u32 dram_odt1;	179	u32 dram_odt1;
180	u32 dram_sdba0;	180	u32 dram_sdba0;
181	u32 dram_sdba1;	181	u32 dram_sdba1;
182	u32 dram_sdba2;	182	u32 dram_sdba2;
183	u32 dram_sdcke0;	183	u32 dram_sdcke0;
184	u32 dram_sdcke1;	184	u32 dram_sdcke1;
185	u32 dram_sdclk_0;	185	u32 dram_sdclk_0;
186	u32 dram_sdqs0;	186	u32 dram_sdqs0;
187	u32 dram_sdqs1;	187	u32 dram_sdqs1;
188	u32 dram_reset;	188	u32 dram_reset;
189	};	189	};
190		190
191	#define MX6UL_IOM_GRP_BASE 0x020e0400	191	#define MX6UL_IOM_GRP_BASE 0x020e0400
192	struct mx6ul_iomux_grp_regs {	192	struct mx6ul_iomux_grp_regs {
193	u32 res1[36];	193	u32 res1[36];
194	u32 grp_addds;	194	u32 grp_addds;
195	u32 grp_ddrmode_ctl;	195	u32 grp_ddrmode_ctl;
196	u32 grp_b0ds;	196	u32 grp_b0ds;
197	u32 grp_ddrpk;	197	u32 grp_ddrpk;
198	u32 grp_ctlds;	198	u32 grp_ctlds;
199	u32 grp_b1ds;	199	u32 grp_b1ds;
200	u32 grp_ddrhys;	200	u32 grp_ddrhys;
201	u32 grp_ddrpke;	201	u32 grp_ddrpke;
202	u32 grp_ddrmode;	202	u32 grp_ddrmode;
203	u32 grp_ddr_type;	203	u32 grp_ddr_type;
204	};	204	};
205		205
206	#define MX6SX_IOM_DDR_BASE 0x020e0200	206	#define MX6SX_IOM_DDR_BASE 0x020e0200
207	struct mx6sx_iomux_ddr_regs {	207	struct mx6sx_iomux_ddr_regs {
208	u32 res1[59];	208	u32 res1[59];
209	u32 dram_dqm0;	209	u32 dram_dqm0;
210	u32 dram_dqm1;	210	u32 dram_dqm1;
211	u32 dram_dqm2;	211	u32 dram_dqm2;
212	u32 dram_dqm3;	212	u32 dram_dqm3;
213	u32 dram_ras;	213	u32 dram_ras;
214	u32 dram_cas;	214	u32 dram_cas;
215	u32 res2[2];	215	u32 res2[2];
216	u32 dram_sdwe_b;	216	u32 dram_sdwe_b;
217	u32 dram_odt0;	217	u32 dram_odt0;
218	u32 dram_odt1;	218	u32 dram_odt1;
219	u32 dram_sdba0;	219	u32 dram_sdba0;
220	u32 dram_sdba1;	220	u32 dram_sdba1;
221	u32 dram_sdba2;	221	u32 dram_sdba2;
222	u32 dram_sdcke0;	222	u32 dram_sdcke0;
223	u32 dram_sdcke1;	223	u32 dram_sdcke1;
224	u32 dram_sdclk_0;	224	u32 dram_sdclk_0;
225	u32 dram_sdqs0;	225	u32 dram_sdqs0;
226	u32 dram_sdqs1;	226	u32 dram_sdqs1;
227	u32 dram_sdqs2;	227	u32 dram_sdqs2;
228	u32 dram_sdqs3;	228	u32 dram_sdqs3;
229	u32 dram_reset;	229	u32 dram_reset;
230	};	230	};
231		231
232	#define MX6SX_IOM_GRP_BASE 0x020e0500	232	#define MX6SX_IOM_GRP_BASE 0x020e0500
233	struct mx6sx_iomux_grp_regs {	233	struct mx6sx_iomux_grp_regs {
234	u32 res1[61];	234	u32 res1[61];
235	u32 grp_addds;	235	u32 grp_addds;
236	u32 grp_ddrmode_ctl;	236	u32 grp_ddrmode_ctl;
237	u32 grp_ddrpke;	237	u32 grp_ddrpke;
238	u32 grp_ddrpk;	238	u32 grp_ddrpk;
239	u32 grp_ddrhys;	239	u32 grp_ddrhys;
240	u32 grp_ddrmode;	240	u32 grp_ddrmode;
241	u32 grp_b0ds;	241	u32 grp_b0ds;
242	u32 grp_b1ds;	242	u32 grp_b1ds;
243	u32 grp_ctlds;	243	u32 grp_ctlds;
244	u32 grp_ddr_type;	244	u32 grp_ddr_type;
245	u32 grp_b2ds;	245	u32 grp_b2ds;
246	u32 grp_b3ds;	246	u32 grp_b3ds;
247	};	247	};
248		248
249	/*	249	/*
250	* MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)	250	* MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
251	*/	251	*/
252	#define MX6DQ_IOM_DDR_BASE 0x020e0500	252	#define MX6DQ_IOM_DDR_BASE 0x020e0500
253	struct mx6dq_iomux_ddr_regs {	253	struct mx6dq_iomux_ddr_regs {
254	u32 res1[3];	254	u32 res1[3];
255	u32 dram_sdqs5;	255	u32 dram_sdqs5;
256	u32 dram_dqm5;	256	u32 dram_dqm5;
257	u32 dram_dqm4;	257	u32 dram_dqm4;
258	u32 dram_sdqs4;	258	u32 dram_sdqs4;
259	u32 dram_sdqs3;	259	u32 dram_sdqs3;
260	u32 dram_dqm3;	260	u32 dram_dqm3;
261	u32 dram_sdqs2;	261	u32 dram_sdqs2;
262	u32 dram_dqm2;	262	u32 dram_dqm2;
263	u32 res2[16];	263	u32 res2[16];
264	u32 dram_cas;	264	u32 dram_cas;
265	u32 res3[2];	265	u32 res3[2];
266	u32 dram_ras;	266	u32 dram_ras;
267	u32 dram_reset;	267	u32 dram_reset;
268	u32 res4[2];	268	u32 res4[2];
269	u32 dram_sdclk_0;	269	u32 dram_sdclk_0;
270	u32 dram_sdba2;	270	u32 dram_sdba2;
271	u32 dram_sdcke0;	271	u32 dram_sdcke0;
272	u32 dram_sdclk_1;	272	u32 dram_sdclk_1;
273	u32 dram_sdcke1;	273	u32 dram_sdcke1;
274	u32 dram_sdodt0;	274	u32 dram_sdodt0;
275	u32 dram_sdodt1;	275	u32 dram_sdodt1;
276	u32 res5;	276	u32 res5;
277	u32 dram_sdqs0;	277	u32 dram_sdqs0;
278	u32 dram_dqm0;	278	u32 dram_dqm0;
279	u32 dram_sdqs1;	279	u32 dram_sdqs1;
280	u32 dram_dqm1;	280	u32 dram_dqm1;
281	u32 dram_sdqs6;	281	u32 dram_sdqs6;
282	u32 dram_dqm6;	282	u32 dram_dqm6;
283	u32 dram_sdqs7;	283	u32 dram_sdqs7;
284	u32 dram_dqm7;	284	u32 dram_dqm7;
285	};	285	};
286		286
287	#define MX6DQ_IOM_GRP_BASE 0x020e0700	287	#define MX6DQ_IOM_GRP_BASE 0x020e0700
288	struct mx6dq_iomux_grp_regs {	288	struct mx6dq_iomux_grp_regs {
289	u32 res1[18];	289	u32 res1[18];
290	u32 grp_b7ds;	290	u32 grp_b7ds;
291	u32 grp_addds;	291	u32 grp_addds;
292	u32 grp_ddrmode_ctl;	292	u32 grp_ddrmode_ctl;
293	u32 res2;	293	u32 res2;
294	u32 grp_ddrpke;	294	u32 grp_ddrpke;
295	u32 res3[6];	295	u32 res3[6];
296	u32 grp_ddrmode;	296	u32 grp_ddrmode;
297	u32 res4[3];	297	u32 res4[3];
298	u32 grp_b0ds;	298	u32 grp_b0ds;
299	u32 grp_b1ds;	299	u32 grp_b1ds;
300	u32 grp_ctlds;	300	u32 grp_ctlds;
301	u32 res5;	301	u32 res5;
302	u32 grp_b2ds;	302	u32 grp_b2ds;
303	u32 grp_ddr_type;	303	u32 grp_ddr_type;
304	u32 grp_b3ds;	304	u32 grp_b3ds;
305	u32 grp_b4ds;	305	u32 grp_b4ds;
306	u32 grp_b5ds;	306	u32 grp_b5ds;
307	u32 grp_b6ds;	307	u32 grp_b6ds;
308	};	308	};
309		309
310	#define MX6SDL_IOM_DDR_BASE 0x020e0400	310	#define MX6SDL_IOM_DDR_BASE 0x020e0400
311	struct mx6sdl_iomux_ddr_regs {	311	struct mx6sdl_iomux_ddr_regs {
312	u32 res1[25];	312	u32 res1[25];
313	u32 dram_cas;	313	u32 dram_cas;
314	u32 res2[2];	314	u32 res2[2];
315	u32 dram_dqm0;	315	u32 dram_dqm0;
316	u32 dram_dqm1;	316	u32 dram_dqm1;
317	u32 dram_dqm2;	317	u32 dram_dqm2;
318	u32 dram_dqm3;	318	u32 dram_dqm3;
319	u32 dram_dqm4;	319	u32 dram_dqm4;
320	u32 dram_dqm5;	320	u32 dram_dqm5;
321	u32 dram_dqm6;	321	u32 dram_dqm6;
322	u32 dram_dqm7;	322	u32 dram_dqm7;
323	u32 dram_ras;	323	u32 dram_ras;
324	u32 dram_reset;	324	u32 dram_reset;
325	u32 res3[2];	325	u32 res3[2];
326	u32 dram_sdba2;	326	u32 dram_sdba2;
327	u32 dram_sdcke0;	327	u32 dram_sdcke0;
328	u32 dram_sdcke1;	328	u32 dram_sdcke1;
329	u32 dram_sdclk_0;	329	u32 dram_sdclk_0;
330	u32 dram_sdclk_1;	330	u32 dram_sdclk_1;
331	u32 dram_sdodt0;	331	u32 dram_sdodt0;
332	u32 dram_sdodt1;	332	u32 dram_sdodt1;
333	u32 dram_sdqs0;	333	u32 dram_sdqs0;
334	u32 dram_sdqs1;	334	u32 dram_sdqs1;
335	u32 dram_sdqs2;	335	u32 dram_sdqs2;
336	u32 dram_sdqs3;	336	u32 dram_sdqs3;
337	u32 dram_sdqs4;	337	u32 dram_sdqs4;
338	u32 dram_sdqs5;	338	u32 dram_sdqs5;
339	u32 dram_sdqs6;	339	u32 dram_sdqs6;
340	u32 dram_sdqs7;	340	u32 dram_sdqs7;
341	};	341	};
342		342
343	#define MX6SDL_IOM_GRP_BASE 0x020e0700	343	#define MX6SDL_IOM_GRP_BASE 0x020e0700
344	struct mx6sdl_iomux_grp_regs {	344	struct mx6sdl_iomux_grp_regs {
345	u32 res1[18];	345	u32 res1[18];
346	u32 grp_b7ds;	346	u32 grp_b7ds;
347	u32 grp_addds;	347	u32 grp_addds;
348	u32 grp_ddrmode_ctl;	348	u32 grp_ddrmode_ctl;
349	u32 grp_ddrpke;	349	u32 grp_ddrpke;
350	u32 res2[2];	350	u32 res2[2];
351	u32 grp_ddrmode;	351	u32 grp_ddrmode;
352	u32 grp_b0ds;	352	u32 grp_b0ds;
353	u32 res3;	353	u32 res3;
354	u32 grp_ctlds;	354	u32 grp_ctlds;
355	u32 grp_b1ds;	355	u32 grp_b1ds;
356	u32 grp_ddr_type;	356	u32 grp_ddr_type;
357	u32 grp_b2ds;	357	u32 grp_b2ds;
358	u32 grp_b3ds;	358	u32 grp_b3ds;
359	u32 grp_b4ds;	359	u32 grp_b4ds;
360	u32 grp_b5ds;	360	u32 grp_b5ds;
361	u32 res4;	361	u32 res4;
362	u32 grp_b6ds;	362	u32 grp_b6ds;
363	};	363	};
364		364
365	/* Device Information: Varies per DDR3 part number and speed grade */	365	/* Device Information: Varies per DDR3 part number and speed grade */
366	struct mx6_ddr3_cfg {	366	struct mx6_ddr3_cfg {
367	u16 mem_speed; /* ie 1600 for DDR3-1600 (800,1066,1333,1600) */	367	u16 mem_speed; /* ie 1600 for DDR3-1600 (800,1066,1333,1600) */
368	u8 density; /* chip density (Gb) (1,2,4,8) */	368	u8 density; /* chip density (Gb) (1,2,4,8) */
369	u8 width; /* bus width (bits) (4,8,16) */	369	u8 width; /* bus width (bits) (4,8,16) */
370	u8 banks; /* number of banks */	370	u8 banks; /* number of banks */
371	u8 rowaddr; /* row address bits (11-16)*/	371	u8 rowaddr; /* row address bits (11-16)*/
372	u8 coladdr; /* col address bits (9-12) */	372	u8 coladdr; /* col address bits (9-12) */
373	u8 pagesz; /* page size (K) (1-2) */	373	u8 pagesz; /* page size (K) (1-2) */
374	u16 trcd; /* tRCD=tRP=CL (ns100) /	374	u16 trcd; /* tRCD=tRP=CL (ns100) /
375	u16 trcmin; /* tRC min (ns100) /	375	u16 trcmin; /* tRC min (ns100) /
376	u16 trasmin; /* tRAS min (ns100) /	376	u16 trasmin; /* tRAS min (ns100) /
377	u8 SRT; /* self-refresh temperature: 0=normal, 1=extended */	377	u8 SRT; /* self-refresh temperature: 0=normal, 1=extended */
378	};	378	};
379		379
380	/* Device Information: Varies per LPDDR2 part number and speed grade */	380	/* Device Information: Varies per LPDDR2 part number and speed grade */
381	struct mx6_lpddr2_cfg {	381	struct mx6_lpddr2_cfg {
382	u16 mem_speed; /* ie 800 for LPDDR2-800 */	382	u16 mem_speed; /* ie 800 for LPDDR2-800 */
383	u8 density; /* chip density (Gb) (1,2,4,8) */	383	u8 density; /* chip density (Gb) (1,2,4,8) */
384	u8 width; /* bus width (bits) (4,8,16) */	384	u8 width; /* bus width (bits) (4,8,16) */
385	u8 banks; /* number of banks */	385	u8 banks; /* number of banks */
386	u8 rowaddr; /* row address bits (11-16)*/	386	u8 rowaddr; /* row address bits (11-16)*/
387	u8 coladdr; /* col address bits (9-12) */	387	u8 coladdr; /* col address bits (9-12) */
388	u16 trcd_lp;	388	u16 trcd_lp;
389	u16 trppb_lp;	389	u16 trppb_lp;
390	u16 trpab_lp;	390	u16 trpab_lp;
391	u16 trcmin; /* tRC min (ns100) /	391	u16 trcmin; /* tRC min (ns100) /
392	u16 trasmin; /* tRAS min (ns100) /	392	u16 trasmin; /* tRAS min (ns100) /
393	};	393	};
394		394
395	/* System Information: Varies per board design, layout, and term choices */	395	/* System Information: Varies per board design, layout, and term choices */
396	struct mx6_ddr_sysinfo {	396	struct mx6_ddr_sysinfo {
397	u8 dsize; /* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */	397	u8 dsize; /* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */
398	u8 cs_density; /* density per chip select (Gb) */	398	u8 cs_density; /* density per chip select (Gb) */
399	u8 ncs; /* number chip selects used (1\|2) */	399	u8 ncs; /* number chip selects used (1\|2) */
400	char cs1_mirror;/* enable address mirror (0\|1) */	400	char cs1_mirror;/* enable address mirror (0\|1) */
401	char bi_on; /* Bank interleaving enable */	401	char bi_on; /* Bank interleaving enable */
402	u8 rtt_nom; /* Rtt_Nom (DDR3_RTT_) /	402	u8 rtt_nom; /* Rtt_Nom (DDR3_RTT_) /
403	u8 rtt_wr; /* Rtt_Wr (DDR3_RTT_) /	403	u8 rtt_wr; /* Rtt_Wr (DDR3_RTT_) /
404	u8 ralat; /* Read Additional Latency (0-7) */	404	u8 ralat; /* Read Additional Latency (0-7) */
405	u8 walat; /* Write Additional Latency (0-3) */	405	u8 walat; /* Write Additional Latency (0-3) */
406	u8 mif3_mode; /* Command prediction working mode */	406	u8 mif3_mode; /* Command prediction working mode */
407	u8 rst_to_cke; /* Time from SDE enable to CKE rise */	407	u8 rst_to_cke; /* Time from SDE enable to CKE rise */
408	u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */	408	u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */
409	u8 pd_fast_exit;/* enable precharge powerdown fast-exit */	409	u8 pd_fast_exit;/* enable precharge powerdown fast-exit */
410	u8 ddr_type; /* DDR type: DDR3(0) or LPDDR2(1) */	410	u8 ddr_type; /* DDR type: DDR3(0) or LPDDR2(1) */
411	u8 refsel; /* REF_SEL field of register MDREF */	411	u8 refsel; /* REF_SEL field of register MDREF */
412	u8 refr; /* REFR field of register MDREF */	412	u8 refr; /* REFR field of register MDREF */
413	};	413	};
414		414
415	/*	415	/*
416	* Board specific calibration:	416	* Board specific calibration:
417	* This includes write leveling calibration values as well as DQS gating	417	* This includes write leveling calibration values as well as DQS gating
418	* and read/write delays. These values are board/layout/device specific.	418	* and read/write delays. These values are board/layout/device specific.
419	* Freescale recommends using the i.MX6 DDR Stress Test Tool V1.0.2	419	* Freescale recommends using the i.MX6 DDR Stress Test Tool V1.0.2
420	* (DOC-96412) to determine these values over a range of boards and	420	* (DOC-96412) to determine these values over a range of boards and
421	* temperatures.	421	* temperatures.
422	*/	422	*/
423	struct mx6_mmdc_calibration {	423	struct mx6_mmdc_calibration {
424	/* write leveling calibration */	424	/* write leveling calibration */
425	u32 p0_mpwldectrl0;	425	u32 p0_mpwldectrl0;
426	u32 p0_mpwldectrl1;	426	u32 p0_mpwldectrl1;
427	u32 p1_mpwldectrl0;	427	u32 p1_mpwldectrl0;
428	u32 p1_mpwldectrl1;	428	u32 p1_mpwldectrl1;
429	/* read DQS gating */	429	/* read DQS gating */
430	u32 p0_mpdgctrl0;	430	u32 p0_mpdgctrl0;
431	u32 p0_mpdgctrl1;	431	u32 p0_mpdgctrl1;
432	u32 p1_mpdgctrl0;	432	u32 p1_mpdgctrl0;
433	u32 p1_mpdgctrl1;	433	u32 p1_mpdgctrl1;
434	/* read delay */	434	/* read delay */
435	u32 p0_mprddlctl;	435	u32 p0_mprddlctl;
436	u32 p1_mprddlctl;	436	u32 p1_mprddlctl;
437	/* write delay */	437	/* write delay */
438	u32 p0_mpwrdlctl;	438	u32 p0_mpwrdlctl;
439	u32 p1_mpwrdlctl;	439	u32 p1_mpwrdlctl;
440	/* lpddr2 zq hw calibration */	440	/* lpddr2 zq hw calibration */
441	u32 mpzqlp2ctl;	441	u32 mpzqlp2ctl;
442	};	442	};
443		443
444	/* configure iomux (pinctl/padctl) */	444	/* configure iomux (pinctl/padctl) */
445	void mx6dq_dram_iocfg(unsigned width,	445	void mx6dq_dram_iocfg(unsigned width,
446	const struct mx6dq_iomux_ddr_regs *,	446	const struct mx6dq_iomux_ddr_regs *,
447	const struct mx6dq_iomux_grp_regs *);	447	const struct mx6dq_iomux_grp_regs *);
448	void mx6sdl_dram_iocfg(unsigned width,	448	void mx6sdl_dram_iocfg(unsigned width,
449	const struct mx6sdl_iomux_ddr_regs *,	449	const struct mx6sdl_iomux_ddr_regs *,
450	const struct mx6sdl_iomux_grp_regs *);	450	const struct mx6sdl_iomux_grp_regs *);
451	void mx6sx_dram_iocfg(unsigned width,	451	void mx6sx_dram_iocfg(unsigned width,
452	const struct mx6sx_iomux_ddr_regs *,	452	const struct mx6sx_iomux_ddr_regs *,
453	const struct mx6sx_iomux_grp_regs *);	453	const struct mx6sx_iomux_grp_regs *);
454	void mx6ul_dram_iocfg(unsigned width,	454	void mx6ul_dram_iocfg(unsigned width,
455	const struct mx6ul_iomux_ddr_regs *,	455	const struct mx6ul_iomux_ddr_regs *,
456	const struct mx6ul_iomux_grp_regs *);	456	const struct mx6ul_iomux_grp_regs *);
457	void mx6sl_dram_iocfg(unsigned width,	457	void mx6sl_dram_iocfg(unsigned width,
458	const struct mx6sl_iomux_ddr_regs *,	458	const struct mx6sl_iomux_ddr_regs *,
459	const struct mx6sl_iomux_grp_regs *);	459	const struct mx6sl_iomux_grp_regs *);
460		460
461	#if defined(CONFIG_MX6_DDRCAL)	461	#if defined(CONFIG_MX6_DDRCAL)
462	int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo);	462	int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo);
463	int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo);	463	int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo);
464	void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo,	464	void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo,
465	struct mx6_mmdc_calibration *calib);	465	struct mx6_mmdc_calibration *calib);
466	#endif	466	#endif
467		467
468	/* configure mx6 mmdc registers */	468	/* configure mx6 mmdc registers */
469	void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,	469	void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
470	const struct mx6_mmdc_calibration *,	470	const struct mx6_mmdc_calibration *,
471	const void *);	471	const void *);
472		472
473	#endif /* CONFIG_SPL_BUILD */	473	#endif /* CONFIG_SPL_BUILD */
474		474
475	#define MX6_MMDC_P0_MDCTL 0x021b0000	475	#define MX6_MMDC_P0_MDCTL 0x021b0000
476	#define MX6_MMDC_P0_MDPDC 0x021b0004	476	#define MX6_MMDC_P0_MDPDC 0x021b0004
477	#define MX6_MMDC_P0_MDOTC 0x021b0008	477	#define MX6_MMDC_P0_MDOTC 0x021b0008
478	#define MX6_MMDC_P0_MDCFG0 0x021b000c	478	#define MX6_MMDC_P0_MDCFG0 0x021b000c
479	#define MX6_MMDC_P0_MDCFG1 0x021b0010	479	#define MX6_MMDC_P0_MDCFG1 0x021b0010
480	#define MX6_MMDC_P0_MDCFG2 0x021b0014	480	#define MX6_MMDC_P0_MDCFG2 0x021b0014
481	#define MX6_MMDC_P0_MDMISC 0x021b0018	481	#define MX6_MMDC_P0_MDMISC 0x021b0018
482	#define MX6_MMDC_P0_MDSCR 0x021b001c	482	#define MX6_MMDC_P0_MDSCR 0x021b001c
483	#define MX6_MMDC_P0_MDREF 0x021b0020	483	#define MX6_MMDC_P0_MDREF 0x021b0020
484	#define MX6_MMDC_P0_MDRWD 0x021b002c	484	#define MX6_MMDC_P0_MDRWD 0x021b002c
485	#define MX6_MMDC_P0_MDOR 0x021b0030	485	#define MX6_MMDC_P0_MDOR 0x021b0030
486	#define MX6_MMDC_P0_MDASP 0x021b0040	486	#define MX6_MMDC_P0_MDASP 0x021b0040
487	#define MX6_MMDC_P0_MAPSR 0x021b0404	487	#define MX6_MMDC_P0_MAPSR 0x021b0404
488	#define MX6_MMDC_P0_MPZQHWCTRL 0x021b0800	488	#define MX6_MMDC_P0_MPZQHWCTRL 0x021b0800
489	#define MX6_MMDC_P0_MPWLDECTRL0 0x021b080c	489	#define MX6_MMDC_P0_MPWLDECTRL0 0x021b080c
490	#define MX6_MMDC_P0_MPWLDECTRL1 0x021b0810	490	#define MX6_MMDC_P0_MPWLDECTRL1 0x021b0810
491	#define MX6_MMDC_P0_MPODTCTRL 0x021b0818	491	#define MX6_MMDC_P0_MPODTCTRL 0x021b0818
492	#define MX6_MMDC_P0_MPRDDQBY0DL 0x021b081c	492	#define MX6_MMDC_P0_MPRDDQBY0DL 0x021b081c
493	#define MX6_MMDC_P0_MPRDDQBY1DL 0x021b0820	493	#define MX6_MMDC_P0_MPRDDQBY1DL 0x021b0820
494	#define MX6_MMDC_P0_MPRDDQBY2DL 0x021b0824	494	#define MX6_MMDC_P0_MPRDDQBY2DL 0x021b0824
495	#define MX6_MMDC_P0_MPRDDQBY3DL 0x021b0828	495	#define MX6_MMDC_P0_MPRDDQBY3DL 0x021b0828
496	#define MX6_MMDC_P0_MPDGCTRL0 0x021b083c	496	#define MX6_MMDC_P0_MPDGCTRL0 0x021b083c
497	#define MX6_MMDC_P0_MPDGCTRL1 0x021b0840	497	#define MX6_MMDC_P0_MPDGCTRL1 0x021b0840
498	#define MX6_MMDC_P0_MPRDDLCTL 0x021b0848	498	#define MX6_MMDC_P0_MPRDDLCTL 0x021b0848
499	#define MX6_MMDC_P0_MPWRDLCTL 0x021b0850	499	#define MX6_MMDC_P0_MPWRDLCTL 0x021b0850
500	#define MX6_MMDC_P0_MPZQLP2CTL 0x021b085C	500	#define MX6_MMDC_P0_MPZQLP2CTL 0x021b085C
501	#define MX6_MMDC_P0_MPMUR0 0x021b08b8	501	#define MX6_MMDC_P0_MPMUR0 0x021b08b8
502		502
503	#define MX6_MMDC_P1_MDCTL 0x021b4000	503	#define MX6_MMDC_P1_MDCTL 0x021b4000
504	#define MX6_MMDC_P1_MDPDC 0x021b4004	504	#define MX6_MMDC_P1_MDPDC 0x021b4004
505	#define MX6_MMDC_P1_MDOTC 0x021b4008	505	#define MX6_MMDC_P1_MDOTC 0x021b4008
506	#define MX6_MMDC_P1_MDCFG0 0x021b400c	506	#define MX6_MMDC_P1_MDCFG0 0x021b400c
507	#define MX6_MMDC_P1_MDCFG1 0x021b4010	507	#define MX6_MMDC_P1_MDCFG1 0x021b4010
508	#define MX6_MMDC_P1_MDCFG2 0x021b4014	508	#define MX6_MMDC_P1_MDCFG2 0x021b4014
509	#define MX6_MMDC_P1_MDMISC 0x021b4018	509	#define MX6_MMDC_P1_MDMISC 0x021b4018
510	#define MX6_MMDC_P1_MDSCR 0x021b401c	510	#define MX6_MMDC_P1_MDSCR 0x021b401c
511	#define MX6_MMDC_P1_MDREF 0x021b4020	511	#define MX6_MMDC_P1_MDREF 0x021b4020
512	#define MX6_MMDC_P1_MDRWD 0x021b402c	512	#define MX6_MMDC_P1_MDRWD 0x021b402c
513	#define MX6_MMDC_P1_MDOR 0x021b4030	513	#define MX6_MMDC_P1_MDOR 0x021b4030
514	#define MX6_MMDC_P1_MDASP 0x021b4040	514	#define MX6_MMDC_P1_MDASP 0x021b4040
515	#define MX6_MMDC_P1_MAPSR 0x021b4404	515	#define MX6_MMDC_P1_MAPSR 0x021b4404
516	#define MX6_MMDC_P1_MPZQHWCTRL 0x021b4800	516	#define MX6_MMDC_P1_MPZQHWCTRL 0x021b4800
517	#define MX6_MMDC_P1_MPWLDECTRL0 0x021b480c	517	#define MX6_MMDC_P1_MPWLDECTRL0 0x021b480c
518	#define MX6_MMDC_P1_MPWLDECTRL1 0x021b4810	518	#define MX6_MMDC_P1_MPWLDECTRL1 0x021b4810
519	#define MX6_MMDC_P1_MPODTCTRL 0x021b4818	519	#define MX6_MMDC_P1_MPODTCTRL 0x021b4818
520	#define MX6_MMDC_P1_MPRDDQBY0DL 0x021b481c	520	#define MX6_MMDC_P1_MPRDDQBY0DL 0x021b481c
521	#define MX6_MMDC_P1_MPRDDQBY1DL 0x021b4820	521	#define MX6_MMDC_P1_MPRDDQBY1DL 0x021b4820
522	#define MX6_MMDC_P1_MPRDDQBY2DL 0x021b4824	522	#define MX6_MMDC_P1_MPRDDQBY2DL 0x021b4824
523	#define MX6_MMDC_P1_MPRDDQBY3DL 0x021b4828	523	#define MX6_MMDC_P1_MPRDDQBY3DL 0x021b4828
524	#define MX6_MMDC_P1_MPDGCTRL0 0x021b483c	524	#define MX6_MMDC_P1_MPDGCTRL0 0x021b483c
525	#define MX6_MMDC_P1_MPDGCTRL1 0x021b4840	525	#define MX6_MMDC_P1_MPDGCTRL1 0x021b4840
526	#define MX6_MMDC_P1_MPRDDLCTL 0x021b4848	526	#define MX6_MMDC_P1_MPRDDLCTL 0x021b4848
527	#define MX6_MMDC_P1_MPWRDLCTL 0x021b4850	527	#define MX6_MMDC_P1_MPWRDLCTL 0x021b4850
528	#define MX6_MMDC_P1_MPZQLP2CTL 0x021b485C	528	#define MX6_MMDC_P1_MPZQLP2CTL 0x021b485C
529	#define MX6_MMDC_P1_MPMUR0 0x021b48b8	529	#define MX6_MMDC_P1_MPMUR0 0x021b48b8
530		530
531	#endif /__ASM_ARCH_MX6_DDR_H__ /	531	#endif /__ASM_ARCH_MX6_DDR_H__ /
532		532

arch/arm/include/asm/arch-mx6/mx6ul-ddr.h

Diff comments View file @ 290e7cf

arch/arm/include/asm/mach-imx/iomux-v3.h

Diff comments View file @ 290e7cf

arch/arm/include/asm/mach-imx/regs-lcdif.h

Diff comments View file @ 290e7cf

arch/arm/mach-imx/mx6/Kconfig

Diff comments View file @ 290e7cf

1	if ARCH_MX6	1	if ARCH_MX6
2		2
3	config MX6_SMP	3	config MX6_SMP
4	select ARM_ERRATA_751472	4	select ARM_ERRATA_751472
5	select ARM_ERRATA_761320	5	select ARM_ERRATA_761320
6	select ARM_ERRATA_794072	6	select ARM_ERRATA_794072
7	select ARM_ERRATA_845369	7	select ARM_ERRATA_845369
8	bool	8	bool
9		9
10	config MX6	10	config MX6
11	select ARM_ERRATA_743622 if !MX6UL	11	select ARM_ERRATA_743622 if !MX6UL && !MX6ULL
12	bool	12	bool
13	default y	13	default y
14	imply CMD_FUSE	14	imply CMD_FUSE
15		15
16	config MX6D	16	config MX6D
17	select HAS_CAAM	17	select HAS_CAAM
18	select MX6_SMP	18	select MX6_SMP
19	bool	19	bool
20		20
21	config MX6DL	21	config MX6DL
22	select HAS_CAAM	22	select HAS_CAAM
23	select MX6_SMP	23	select MX6_SMP
24	bool	24	bool
25		25
26	config MX6Q	26	config MX6Q
27	select HAS_CAAM	27	select HAS_CAAM
28	select MX6_SMP	28	select MX6_SMP
29	bool	29	bool
30		30
31	config MX6QDL	31	config MX6QDL
32	select HAS_CAAM	32	select HAS_CAAM
33	select MX6_SMP	33	select MX6_SMP
34	bool	34	bool
35		35
36	config MX6S	36	config MX6S
37	select HAS_CAAM	37	select HAS_CAAM
38	bool	38	bool
39		39
40	config MX6SL	40	config MX6SL
41	bool	41	bool
42		42
43	config MX6SX	43	config MX6SX
44	select HAS_CAAM	44	select HAS_CAAM
45	select ROM_UNIFIED_SECTIONS	45	select ROM_UNIFIED_SECTIONS
46	bool	46	bool
47		47
48	config MX6SLL	48	config MX6SLL
49	select ROM_UNIFIED_SECTIONS	49	select ROM_UNIFIED_SECTIONS
50	bool	50	bool
51		51
52	config MX6UL	52	config MX6UL
53	select HAS_CAAM	53	select HAS_CAAM
54	select SYS_L2CACHE_OFF	54	select SYS_L2CACHE_OFF
55	select ROM_UNIFIED_SECTIONS	55	select ROM_UNIFIED_SECTIONS
56	bool	56	bool
57		57
58	config MX6UL_LITESOM	58	config MX6UL_LITESOM
59	bool	59	bool
60	select MX6UL	60	select MX6UL
61	select DM	61	select DM
62	select DM_THERMAL	62	select DM_THERMAL
63	select SUPPORT_SPL	63	select SUPPORT_SPL
64		64
65	config MX6UL_OPOS6UL	65	config MX6UL_OPOS6UL
66	bool	66	bool
67	select MX6UL	67	select MX6UL
68	select BOARD_LATE_INIT	68	select BOARD_LATE_INIT
69	select DM	69	select DM
70	select DM_GPIO	70	select DM_GPIO
71	select DM_MMC	71	select DM_MMC
72	select DM_THERMAL	72	select DM_THERMAL
73	select SUPPORT_SPL	73	select SUPPORT_SPL
74		74
75	config MX6ULL	75	config MX6ULL
76	select SYS_L2CACHE_OFF	76	select SYS_L2CACHE_OFF
77	select ROM_UNIFIED_SECTIONS	77	select ROM_UNIFIED_SECTIONS
78	bool	78	bool
79		79
80	config MX6_DDRCAL	80	config MX6_DDRCAL
81	bool "Include dynamic DDR calibration routines"	81	bool "Include dynamic DDR calibration routines"
82	depends on SPL	82	depends on SPL
83	default n	83	default n
84	help	84	help
85	Say "Y" if your board uses dynamic (per-boot) DDR calibration.	85	Say "Y" if your board uses dynamic (per-boot) DDR calibration.
86	If unsure, say N.	86	If unsure, say N.
87		87
88	choice	88	choice
89	prompt "MX6 board select"	89	prompt "MX6 board select"
90	optional	90	optional
91		91
92	config TARGET_ADVANTECH_DMS_BA16	92	config TARGET_ADVANTECH_DMS_BA16
93	bool "Advantech dms-ba16"	93	bool "Advantech dms-ba16"
94	select BOARD_LATE_INIT	94	select BOARD_LATE_INIT
95	select MX6Q	95	select MX6Q
96	imply CMD_SATA	96	imply CMD_SATA
97		97
98	config TARGET_APALIS_IMX6	98	config TARGET_APALIS_IMX6
99	bool "Toradex Apalis iMX6 board"	99	bool "Toradex Apalis iMX6 board"
100	select BOARD_LATE_INIT	100	select BOARD_LATE_INIT
101	select SUPPORT_SPL	101	select SUPPORT_SPL
102	select DM	102	select DM
103	select DM_SERIAL	103	select DM_SERIAL
104	select DM_THERMAL	104	select DM_THERMAL
105	imply CMD_SATA	105	imply CMD_SATA
106		106
107	config TARGET_ARISTAINETOS	107	config TARGET_ARISTAINETOS
108	bool "aristainetos"	108	bool "aristainetos"
109		109
110	config TARGET_ARISTAINETOS2	110	config TARGET_ARISTAINETOS2
111	bool "aristainetos2"	111	bool "aristainetos2"
112	select BOARD_LATE_INIT	112	select BOARD_LATE_INIT
113		113
114	config TARGET_ARISTAINETOS2B	114	config TARGET_ARISTAINETOS2B
115	bool "Support aristainetos2-revB"	115	bool "Support aristainetos2-revB"
116	select BOARD_LATE_INIT	116	select BOARD_LATE_INIT
117		117
118	config TARGET_CGTQMX6EVAL	118	config TARGET_CGTQMX6EVAL
119	bool "cgtqmx6eval"	119	bool "cgtqmx6eval"
120	select MX6QDL	120	select MX6QDL
121	select BOARD_LATE_INIT	121	select BOARD_LATE_INIT
122	select SUPPORT_SPL	122	select SUPPORT_SPL
123	select DM	123	select DM
124	select DM_THERMAL	124	select DM_THERMAL
125		125
126	config TARGET_CM_FX6	126	config TARGET_CM_FX6
127	bool "CM-FX6"	127	bool "CM-FX6"
128	select SUPPORT_SPL	128	select SUPPORT_SPL
129	select MX6QDL	129	select MX6QDL
130	select DM	130	select DM
131	select DM_SERIAL	131	select DM_SERIAL
132	select DM_GPIO	132	select DM_GPIO
133		133
134	config TARGET_COLIBRI_IMX6	134	config TARGET_COLIBRI_IMX6
135	bool "Toradex Colibri iMX6 board"	135	bool "Toradex Colibri iMX6 board"
136	select BOARD_LATE_INIT	136	select BOARD_LATE_INIT
137	select SUPPORT_SPL	137	select SUPPORT_SPL
138	select DM	138	select DM
139	select DM_SERIAL	139	select DM_SERIAL
140	select DM_THERMAL	140	select DM_THERMAL
141		141
142	config TARGET_DHCOMIMX6	142	config TARGET_DHCOMIMX6
143	bool "dh_imx6"	143	bool "dh_imx6"
144	select MX6QDL	144	select MX6QDL
145	select BOARD_LATE_INIT	145	select BOARD_LATE_INIT
146	select BOARD_EARLY_INIT_F	146	select BOARD_EARLY_INIT_F
147	select SUPPORT_SPL	147	select SUPPORT_SPL
148	select DM	148	select DM
149	select DM_THERMAL	149	select DM_THERMAL
150	imply CMD_SPL	150	imply CMD_SPL
151		151
152	config TARGET_DISPLAY5	152	config TARGET_DISPLAY5
153	bool "LWN DISPLAY5 board"	153	bool "LWN DISPLAY5 board"
154	select SUPPORT_SPL	154	select SUPPORT_SPL
155	select DM	155	select DM
156	select DM_SERIAL	156	select DM_SERIAL
157		157
158	config TARGET_EMBESTMX6BOARDS	158	config TARGET_EMBESTMX6BOARDS
159	bool "embestmx6boards"	159	bool "embestmx6boards"
160	select BOARD_LATE_INIT	160	select BOARD_LATE_INIT
161		161
162	config TARGET_GE_B450V3	162	config TARGET_GE_B450V3
163	bool "General Electric B450v3"	163	bool "General Electric B450v3"
164	select BOARD_LATE_INIT	164	select BOARD_LATE_INIT
165	select MX6Q	165	select MX6Q
166		166
167	config TARGET_GE_B650V3	167	config TARGET_GE_B650V3
168	bool "General Electric B650v3"	168	bool "General Electric B650v3"
169	select BOARD_LATE_INIT	169	select BOARD_LATE_INIT
170	select MX6Q	170	select MX6Q
171		171
172	config TARGET_GE_B850V3	172	config TARGET_GE_B850V3
173	bool "General Electric B850v3"	173	bool "General Electric B850v3"
174	select BOARD_LATE_INIT	174	select BOARD_LATE_INIT
175	select MX6Q	175	select MX6Q
176		176
177	config TARGET_GW_VENTANA	177	config TARGET_GW_VENTANA
178	bool "gw_ventana"	178	bool "gw_ventana"
179	select MX6QDL	179	select MX6QDL
180	select SUPPORT_SPL	180	select SUPPORT_SPL
181	imply CMD_SATA	181	imply CMD_SATA
182	imply CMD_SPL	182	imply CMD_SPL
183		183
184	config TARGET_KOSAGI_NOVENA	184	config TARGET_KOSAGI_NOVENA
185	bool "Kosagi Novena"	185	bool "Kosagi Novena"
186	select BOARD_LATE_INIT	186	select BOARD_LATE_INIT
187	select SUPPORT_SPL	187	select SUPPORT_SPL
188		188
189	config TARGET_MCCMON6	189	config TARGET_MCCMON6
190	bool "mccmon6"	190	bool "mccmon6"
191	select MX6QDL	191	select MX6QDL
192	select SUPPORT_SPL	192	select SUPPORT_SPL
193		193
194	config TARGET_MX6CUBOXI	194	config TARGET_MX6CUBOXI
195	bool "Solid-run mx6 boards"	195	bool "Solid-run mx6 boards"
196	select MX6QDL	196	select MX6QDL
197	select BOARD_LATE_INIT	197	select BOARD_LATE_INIT
198	select SUPPORT_SPL	198	select SUPPORT_SPL
199		199
200	config TARGET_MX6LOGICPD	200	config TARGET_MX6LOGICPD
201	bool "Logic PD i.MX6 SOM"	201	bool "Logic PD i.MX6 SOM"
202	select BOARD_EARLY_INIT_F	202	select BOARD_EARLY_INIT_F
203	select BOARD_LATE_INIT	203	select BOARD_LATE_INIT
204	select DM	204	select DM
205	select DM_ETH	205	select DM_ETH
206	select DM_GPIO	206	select DM_GPIO
207	select DM_I2C	207	select DM_I2C
208	select DM_MMC	208	select DM_MMC
209	select DM_PMIC	209	select DM_PMIC
210	select DM_REGULATOR	210	select DM_REGULATOR
211	select OF_CONTROL	211	select OF_CONTROL
212		212
213	config TARGET_MX6MEMCAL	213	config TARGET_MX6MEMCAL
214	bool "mx6memcal"	214	bool "mx6memcal"
215	select SUPPORT_SPL	215	select SUPPORT_SPL
216	help	216	help
217	The mx6memcal board is a virtual board that can be used to validate	217	The mx6memcal board is a virtual board that can be used to validate
218	and characterize the memory layout of a new design during the initial	218	and characterize the memory layout of a new design during the initial
219	development and pre-production stages.	219	development and pre-production stages.
220		220
221	config TARGET_MX6QARM2	221	config TARGET_MX6QARM2
222	bool "mx6qarm2"	222	bool "mx6qarm2"
223		223
224	config TARGET_MX6Q_ENGICAM	224	config TARGET_MX6Q_ENGICAM
225	bool "Support Engicam i.Core(RQS)"	225	bool "Support Engicam i.Core(RQS)"
226	select BOARD_LATE_INIT	226	select BOARD_LATE_INIT
227	select MX6QDL	227	select MX6QDL
228	select OF_CONTROL	228	select OF_CONTROL
229	select SPL_OF_LIBFDT	229	select SPL_OF_LIBFDT
230	select DM	230	select DM
231	select DM_ETH	231	select DM_ETH
232	select DM_GPIO	232	select DM_GPIO
233	select DM_I2C	233	select DM_I2C
234	select DM_MMC	234	select DM_MMC
235	select DM_THERMAL	235	select DM_THERMAL
236	select SUPPORT_SPL	236	select SUPPORT_SPL
237	select SPL_LOAD_FIT	237	select SPL_LOAD_FIT
238	select SPL_DM if SPL	238	select SPL_DM if SPL
239	select SPL_OF_CONTROL if SPL	239	select SPL_OF_CONTROL if SPL
240	select SPL_SEPARATE_BSS if SPL	240	select SPL_SEPARATE_BSS if SPL
241	select SPL_PINCTRL if SPL	241	select SPL_PINCTRL if SPL
242		242
243	config TARGET_MX6SABREAUTO	243	config TARGET_MX6SABREAUTO
244	bool "mx6sabreauto"	244	bool "mx6sabreauto"
245	select MX6QDL	245	select MX6QDL
246	select BOARD_LATE_INIT	246	select BOARD_LATE_INIT
247	select SUPPORT_SPL	247	select SUPPORT_SPL
248	select DM	248	select DM
249	select DM_THERMAL	249	select DM_THERMAL
250	select BOARD_EARLY_INIT_F	250	select BOARD_EARLY_INIT_F
251		251
252	config TARGET_MX6SABRESD	252	config TARGET_MX6SABRESD
253	bool "mx6sabresd"	253	bool "mx6sabresd"
254	select MX6QDL	254	select MX6QDL
255	select BOARD_LATE_INIT	255	select BOARD_LATE_INIT
256	select SUPPORT_SPL	256	select SUPPORT_SPL
257	select DM	257	select DM
258	select DM_THERMAL	258	select DM_THERMAL
259	select BOARD_EARLY_INIT_F	259	select BOARD_EARLY_INIT_F
260		260
261	config TARGET_MX6SLEVK	261	config TARGET_MX6SLEVK
262	bool "mx6slevk"	262	bool "mx6slevk"
263	select MX6SL	263	select MX6SL
264	select SUPPORT_SPL	264	select SUPPORT_SPL
265		265
266	config TARGET_MX6SLLEVK	266	config TARGET_MX6SLLEVK
267	bool "mx6sll evk"	267	bool "mx6sll evk"
268	select BOARD_LATE_INIT	268	select BOARD_LATE_INIT
269	select MX6SLL	269	select MX6SLL
270	select DM	270	select DM
271	select DM_THERMAL	271	select DM_THERMAL
272		272
273	config TARGET_MX6SXSABRESD	273	config TARGET_MX6SXSABRESD
274	bool "mx6sxsabresd"	274	bool "mx6sxsabresd"
275	select BOARD_LATE_INIT	275	select BOARD_LATE_INIT
276	select MX6SX	276	select MX6SX
277	select SUPPORT_SPL	277	select SUPPORT_SPL
278	select DM	278	select DM
279	select DM_THERMAL	279	select DM_THERMAL
280	select BOARD_EARLY_INIT_F	280	select BOARD_EARLY_INIT_F
281		281
282	config TARGET_MX6SXSABREAUTO	282	config TARGET_MX6SXSABREAUTO
283	bool "mx6sxsabreauto"	283	bool "mx6sxsabreauto"
284	select BOARD_LATE_INIT	284	select BOARD_LATE_INIT
285	select MX6SX	285	select MX6SX
286	select DM	286	select DM
287	select DM_THERMAL	287	select DM_THERMAL
288	select BOARD_EARLY_INIT_F	288	select BOARD_EARLY_INIT_F
289		289
290	config TARGET_MX6UL_9X9_EVK	290	config TARGET_MX6UL_9X9_EVK
291	bool "mx6ul_9x9_evk"	291	bool "mx6ul_9x9_evk"
292	select BOARD_LATE_INIT	292	select BOARD_LATE_INIT
293	select MX6UL	293	select MX6UL
294	select DM	294	select DM
295	select DM_THERMAL	295	select DM_THERMAL
296	select SUPPORT_SPL	296	select SUPPORT_SPL
297		297
298	config TARGET_MX6UL_14X14_EVK	298	config TARGET_MX6UL_14X14_EVK
299	select BOARD_LATE_INIT	299	select BOARD_LATE_INIT
300	bool "mx6ul_14x14_evk"	300	bool "mx6ul_14x14_evk"
301	select MX6UL	301	select MX6UL
302	select DM	302	select DM
303	select DM_THERMAL	303	select DM_THERMAL
304	select SUPPORT_SPL	304	select SUPPORT_SPL
305		305
306	config TARGET_MX6UL_ENGICAM	306	config TARGET_MX6UL_ENGICAM
307	bool "Support Engicam GEAM6UL/Is.IoT"	307	bool "Support Engicam GEAM6UL/Is.IoT"
308	select BOARD_LATE_INIT	308	select BOARD_LATE_INIT
309	select MX6UL	309	select MX6UL
310	select OF_CONTROL	310	select OF_CONTROL
311	select DM	311	select DM
312	select DM_ETH	312	select DM_ETH
313	select DM_GPIO	313	select DM_GPIO
314	select DM_I2C	314	select DM_I2C
315	select DM_MMC	315	select DM_MMC
316	select DM_THERMAL	316	select DM_THERMAL
317	select SUPPORT_SPL	317	select SUPPORT_SPL
318	select SPL_DM if SPL	318	select SPL_DM if SPL
319	select SPL_OF_CONTROL if SPL	319	select SPL_OF_CONTROL if SPL
320	select SPL_SEPARATE_BSS if SPL	320	select SPL_SEPARATE_BSS if SPL
321	select SPL_PINCTRL if SPL	321	select SPL_PINCTRL if SPL
322		322
323	config TARGET_MX6ULL_14X14_EVK	323	config TARGET_MX6ULL_14X14_EVK
324	bool "Support mx6ull_14x14_evk"	324	bool "Support mx6ull_14x14_evk"
325	select BOARD_LATE_INIT	325	select BOARD_LATE_INIT
326	select MX6ULL	326	select MX6ULL
327	select DM	327	select DM
328	select DM_THERMAL	328	select DM_THERMAL
329		329
330	config TARGET_NITROGEN6X	330	config TARGET_NITROGEN6X
331	bool "nitrogen6x"	331	bool "nitrogen6x"
332	imply USB_HOST_ETHER	332	imply USB_HOST_ETHER
333	imply USB_ETHER_ASIX	333	imply USB_ETHER_ASIX
334	imply USB_ETHER_SMSC95XX	334	imply USB_ETHER_SMSC95XX
335	imply USB_ETHER_MCS7830	335	imply USB_ETHER_MCS7830
336		336
337	config TARGET_OPOS6ULDEV	337	config TARGET_OPOS6ULDEV
338	bool "Armadeus OPOS6ULDev board"	338	bool "Armadeus OPOS6ULDev board"
339	select MX6UL_OPOS6UL	339	select MX6UL_OPOS6UL
340		340
341	config TARGET_OT1200	341	config TARGET_OT1200
342	bool "Bachmann OT1200"	342	bool "Bachmann OT1200"
343	select SUPPORT_SPL	343	select SUPPORT_SPL
344	imply CMD_SATA	344	imply CMD_SATA
345		345
346	config TARGET_PICO_IMX6UL	346	config TARGET_PICO_IMX6UL
347	bool "PICO-IMX6UL-EMMC"	347	bool "PICO-IMX6UL-EMMC"
348	select MX6UL	348	select MX6UL
349		349
350	config TARGET_LITEBOARD	350	config TARGET_LITEBOARD
351	bool "Grinn liteBoard (i.MX6UL)"	351	bool "Grinn liteBoard (i.MX6UL)"
352	select BOARD_LATE_INIT	352	select BOARD_LATE_INIT
353	select MX6UL_LITESOM	353	select MX6UL_LITESOM
354		354
355	config TARGET_PLATINUM_PICON	355	config TARGET_PLATINUM_PICON
356	bool "platinum-picon"	356	bool "platinum-picon"
357	select SUPPORT_SPL	357	select SUPPORT_SPL
358		358
359	config TARGET_PLATINUM_TITANIUM	359	config TARGET_PLATINUM_TITANIUM
360	bool "platinum-titanium"	360	bool "platinum-titanium"
361	select SUPPORT_SPL	361	select SUPPORT_SPL
362		362
363	config TARGET_PCM058	363	config TARGET_PCM058
364	bool "Phytec PCM058 i.MX6 Quad"	364	bool "Phytec PCM058 i.MX6 Quad"
365	select BOARD_LATE_INIT	365	select BOARD_LATE_INIT
366	select SUPPORT_SPL	366	select SUPPORT_SPL
367		367
368	config TARGET_PFLA02	368	config TARGET_PFLA02
369	bool "Phytec PFLA02 (PhyFlex) i.MX6 Quad"	369	bool "Phytec PFLA02 (PhyFlex) i.MX6 Quad"
370	select MX6QDL	370	select MX6QDL
371	select BOARD_LATE_INIT	371	select BOARD_LATE_INIT
372	select SUPPORT_SPL	372	select SUPPORT_SPL
373		373
374	config TARGET_SECOMX6	374	config TARGET_SECOMX6
375	bool "secomx6 boards"	375	bool "secomx6 boards"
376		376
377	config TARGET_TBS2910	377	config TARGET_TBS2910
378	bool "TBS2910 Matrix ARM mini PC"	378	bool "TBS2910 Matrix ARM mini PC"
379		379
380	config TARGET_TITANIUM	380	config TARGET_TITANIUM
381	bool "titanium"	381	bool "titanium"
382		382
383	config TARGET_TQMA6	383	config TARGET_TQMA6
384	bool "TQ Systems TQMa6 board"	384	bool "TQ Systems TQMa6 board"
385	select BOARD_LATE_INIT	385	select BOARD_LATE_INIT
386		386
387	config TARGET_UDOO	387	config TARGET_UDOO
388	bool "udoo"	388	bool "udoo"
389	select MX6QDL	389	select MX6QDL
390	select BOARD_LATE_INIT	390	select BOARD_LATE_INIT
391	select SUPPORT_SPL	391	select SUPPORT_SPL
392		392
393	config TARGET_UDOO_NEO	393	config TARGET_UDOO_NEO
394	bool "UDOO Neo"	394	bool "UDOO Neo"
395	select BOARD_LATE_INIT	395	select BOARD_LATE_INIT
396	select SUPPORT_SPL	396	select SUPPORT_SPL
397	select MX6SX	397	select MX6SX
398	select DM	398	select DM
399	select DM_THERMAL	399	select DM_THERMAL
400		400
401	config TARGET_SAMTEC_VINING_2000	401	config TARGET_SAMTEC_VINING_2000
402	bool "samtec VIN\|ING 2000"	402	bool "samtec VIN\|ING 2000"
403	select BOARD_LATE_INIT	403	select BOARD_LATE_INIT
404	select MX6SX	404	select MX6SX
405	select DM	405	select DM
406	select DM_THERMAL	406	select DM_THERMAL
407		407
408	config TARGET_WANDBOARD	408	config TARGET_WANDBOARD
409	bool "wandboard"	409	bool "wandboard"
410	select MX6QDL	410	select MX6QDL
411	select BOARD_LATE_INIT	411	select BOARD_LATE_INIT
412	select SUPPORT_SPL	412	select SUPPORT_SPL
413		413
414	config TARGET_WARP	414	config TARGET_WARP
415	bool "WaRP"	415	bool "WaRP"
416	select MX6SL	416	select MX6SL
417	select BOARD_LATE_INIT	417	select BOARD_LATE_INIT
418		418
419	config TARGET_XPRESS	419	config TARGET_XPRESS
420	bool "CCV xPress"	420	bool "CCV xPress"
421	select BOARD_LATE_INIT	421	select BOARD_LATE_INIT
422	select MX6UL	422	select MX6UL
423	select DM	423	select DM
424	select DM_THERMAL	424	select DM_THERMAL
425	select SUPPORT_SPL	425	select SUPPORT_SPL
426		426
427	config TARGET_ZC5202	427	config TARGET_ZC5202
428	bool "zc5202"	428	bool "zc5202"
429	select BOARD_LATE_INIT	429	select BOARD_LATE_INIT
430	select SUPPORT_SPL	430	select SUPPORT_SPL
431	select DM	431	select DM
432	select DM_THERMAL	432	select DM_THERMAL
433		433
434	config TARGET_ZC5601	434	config TARGET_ZC5601
435	bool "zc5601"	435	bool "zc5601"
436	select BOARD_LATE_INIT	436	select BOARD_LATE_INIT
437	select SUPPORT_SPL	437	select SUPPORT_SPL
438	select DM	438	select DM
439	select DM_THERMAL	439	select DM_THERMAL
440		440
441	endchoice	441	endchoice
442		442
443	config SYS_SOC	443	config SYS_SOC
444	default "mx6"	444	default "mx6"
445		445
446	source "board/ge/bx50v3/Kconfig"	446	source "board/ge/bx50v3/Kconfig"
447	source "board/advantech/dms-ba16/Kconfig"	447	source "board/advantech/dms-ba16/Kconfig"
448	source "board/aristainetos/Kconfig"	448	source "board/aristainetos/Kconfig"
449	source "board/armadeus/opos6uldev/Kconfig"	449	source "board/armadeus/opos6uldev/Kconfig"
450	source "board/bachmann/ot1200/Kconfig"	450	source "board/bachmann/ot1200/Kconfig"
451	source "board/barco/platinum/Kconfig"	451	source "board/barco/platinum/Kconfig"
452	source "board/barco/titanium/Kconfig"	452	source "board/barco/titanium/Kconfig"
453	source "board/boundary/nitrogen6x/Kconfig"	453	source "board/boundary/nitrogen6x/Kconfig"
454	source "board/ccv/xpress/Kconfig"	454	source "board/ccv/xpress/Kconfig"
455	source "board/compulab/cm_fx6/Kconfig"	455	source "board/compulab/cm_fx6/Kconfig"
456	source "board/congatec/cgtqmx6eval/Kconfig"	456	source "board/congatec/cgtqmx6eval/Kconfig"
457	source "board/dhelectronics/dh_imx6/Kconfig"	457	source "board/dhelectronics/dh_imx6/Kconfig"
458	source "board/el/el6x/Kconfig"	458	source "board/el/el6x/Kconfig"
459	source "board/embest/mx6boards/Kconfig"	459	source "board/embest/mx6boards/Kconfig"
460	source "board/engicam/imx6q/Kconfig"	460	source "board/engicam/imx6q/Kconfig"
461	source "board/engicam/imx6ul/Kconfig"	461	source "board/engicam/imx6ul/Kconfig"
462	source "board/freescale/mx6qarm2/Kconfig"	462	source "board/freescale/mx6qarm2/Kconfig"
463	source "board/freescale/mx6memcal/Kconfig"	463	source "board/freescale/mx6memcal/Kconfig"
464	source "board/freescale/mx6sabreauto/Kconfig"	464	source "board/freescale/mx6sabreauto/Kconfig"
465	source "board/freescale/mx6sabresd/Kconfig"	465	source "board/freescale/mx6sabresd/Kconfig"
466	source "board/freescale/mx6slevk/Kconfig"	466	source "board/freescale/mx6slevk/Kconfig"
467	source "board/freescale/mx6sllevk/Kconfig"	467	source "board/freescale/mx6sllevk/Kconfig"
468	source "board/freescale/mx6sxsabresd/Kconfig"	468	source "board/freescale/mx6sxsabresd/Kconfig"
469	source "board/freescale/mx6sxsabreauto/Kconfig"	469	source "board/freescale/mx6sxsabreauto/Kconfig"
470	source "board/freescale/mx6ul_14x14_evk/Kconfig"	470	source "board/freescale/mx6ul_14x14_evk/Kconfig"
471	source "board/freescale/mx6ullevk/Kconfig"	471	source "board/freescale/mx6ullevk/Kconfig"
472	source "board/grinn/liteboard/Kconfig"	472	source "board/grinn/liteboard/Kconfig"
473	source "board/phytec/pcm058/Kconfig"	473	source "board/phytec/pcm058/Kconfig"
474	source "board/phytec/pfla02/Kconfig"	474	source "board/phytec/pfla02/Kconfig"
475	source "board/gateworks/gw_ventana/Kconfig"	475	source "board/gateworks/gw_ventana/Kconfig"
476	source "board/kosagi/novena/Kconfig"	476	source "board/kosagi/novena/Kconfig"
477	source "board/samtec/vining_2000/Kconfig"	477	source "board/samtec/vining_2000/Kconfig"
478	source "board/liebherr/display5/Kconfig"	478	source "board/liebherr/display5/Kconfig"
479	source "board/liebherr/mccmon6/Kconfig"	479	source "board/liebherr/mccmon6/Kconfig"
480	source "board/logicpd/imx6/Kconfig"	480	source "board/logicpd/imx6/Kconfig"
481	source "board/seco/Kconfig"	481	source "board/seco/Kconfig"
482	source "board/solidrun/mx6cuboxi/Kconfig"	482	source "board/solidrun/mx6cuboxi/Kconfig"
483	source "board/technexion/pico-imx6ul/Kconfig"	483	source "board/technexion/pico-imx6ul/Kconfig"
484	source "board/tbs/tbs2910/Kconfig"	484	source "board/tbs/tbs2910/Kconfig"
485	source "board/tqc/tqma6/Kconfig"	485	source "board/tqc/tqma6/Kconfig"
486	source "board/toradex/apalis_imx6/Kconfig"	486	source "board/toradex/apalis_imx6/Kconfig"
487	source "board/toradex/colibri_imx6/Kconfig"	487	source "board/toradex/colibri_imx6/Kconfig"
488	source "board/udoo/Kconfig"	488	source "board/udoo/Kconfig"
489	source "board/udoo/neo/Kconfig"	489	source "board/udoo/neo/Kconfig"
490	source "board/wandboard/Kconfig"	490	source "board/wandboard/Kconfig"
491	source "board/warp/Kconfig"	491	source "board/warp/Kconfig"
492		492
493	endif	493	endif
494		494

arch/arm/mach-imx/mx6/ddr.c

Diff comments View file @ 290e7cf

drivers/gpio/mxc_gpio.c

Diff comments View file @ 290e7cf

1	/*	1	/*
2	* Copyright (C) 2009	2	* Copyright (C) 2009
3	* Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>	3	* Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
4	*	4	*
5	* Copyright (C) 2011	5	* Copyright (C) 2011
6	* Stefano Babic, DENX Software Engineering, <sbabic@denx.de>	6	* Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
7	*	7	*
8	* SPDX-License-Identifier: GPL-2.0+	8	* SPDX-License-Identifier: GPL-2.0+
9	*/	9	*/
10	#include <common.h>	10	#include <common.h>
11	#include <errno.h>	11	#include <errno.h>
12	#include <dm.h>	12	#include <dm.h>
13	#include <malloc.h>	13	#include <malloc.h>
14	#include <asm/arch/imx-regs.h>	14	#include <asm/arch/imx-regs.h>
15	#include <asm/gpio.h>	15	#include <asm/gpio.h>
16	#include <asm/io.h>	16	#include <asm/io.h>
17		17
18	enum mxc_gpio_direction {	18	enum mxc_gpio_direction {
19	MXC_GPIO_DIRECTION_IN,	19	MXC_GPIO_DIRECTION_IN,
20	MXC_GPIO_DIRECTION_OUT,	20	MXC_GPIO_DIRECTION_OUT,
21	};	21	};
22		22
23	#define GPIO_PER_BANK 32	23	#define GPIO_PER_BANK 32
24		24
25	struct mxc_gpio_plat {	25	struct mxc_gpio_plat {
26	int bank_index;	26	int bank_index;
27	struct gpio_regs *regs;	27	struct gpio_regs *regs;
28	};	28	};
29		29
30	struct mxc_bank_info {	30	struct mxc_bank_info {
31	struct gpio_regs *regs;	31	struct gpio_regs *regs;
32	};	32	};
33		33
34	#ifndef CONFIG_DM_GPIO	34	#ifndef CONFIG_DM_GPIO
35	#define GPIO_TO_PORT(n) (n / 32)	35	#define GPIO_TO_PORT(n) (n / 32)
36		36
37	/* GPIO port description */	37	/* GPIO port description */
38	static unsigned long gpio_ports[] = {	38	static unsigned long gpio_ports[] = {
39	[0] = GPIO1_BASE_ADDR,	39	[0] = GPIO1_BASE_ADDR,
40	[1] = GPIO2_BASE_ADDR,	40	[1] = GPIO2_BASE_ADDR,
41	[2] = GPIO3_BASE_ADDR,	41	[2] = GPIO3_BASE_ADDR,
42	#if defined(CONFIG_MX25) \|\| defined(CONFIG_MX27) \|\| defined(CONFIG_MX51) \|\| \	42	#if defined(CONFIG_MX25) \|\| defined(CONFIG_MX27) \|\| defined(CONFIG_MX51) \|\| \
43	defined(CONFIG_MX53) \|\| defined(CONFIG_MX6) \|\| \	43	defined(CONFIG_MX53) \|\| defined(CONFIG_MX6) \|\| \
44	defined(CONFIG_MX7)	44	defined(CONFIG_MX7)
45	[3] = GPIO4_BASE_ADDR,	45	[3] = GPIO4_BASE_ADDR,
46	#endif	46	#endif
47	#if defined(CONFIG_MX27) \|\| defined(CONFIG_MX53) \|\| defined(CONFIG_MX6) \|\| \	47	#if defined(CONFIG_MX27) \|\| defined(CONFIG_MX53) \|\| defined(CONFIG_MX6) \|\| \
48	defined(CONFIG_MX7)	48	defined(CONFIG_MX7)
49	[4] = GPIO5_BASE_ADDR,	49	[4] = GPIO5_BASE_ADDR,
50	#ifndef CONFIG_MX6UL	50	#if !(defined(CONFIG_MX6UL) \|\| defined(CONFIG_MX6ULL))
51	[5] = GPIO6_BASE_ADDR,	51	[5] = GPIO6_BASE_ADDR,
52	#endif	52	#endif
53	#endif	53	#endif
54	#if defined(CONFIG_MX53) \|\| defined(CONFIG_MX6) \|\| defined(CONFIG_MX7)	54	#if defined(CONFIG_MX53) \|\| defined(CONFIG_MX6) \|\| defined(CONFIG_MX7)
55	#ifndef CONFIG_MX6UL	55	#if !(defined(CONFIG_MX6UL) \|\| defined(CONFIG_MX6ULL))
56	[6] = GPIO7_BASE_ADDR,	56	[6] = GPIO7_BASE_ADDR,
57	#endif	57	#endif
58	#endif	58	#endif
59	};	59	};
60		60
61	static int mxc_gpio_direction(unsigned int gpio,	61	static int mxc_gpio_direction(unsigned int gpio,
62	enum mxc_gpio_direction direction)	62	enum mxc_gpio_direction direction)
63	{	63	{
64	unsigned int port = GPIO_TO_PORT(gpio);	64	unsigned int port = GPIO_TO_PORT(gpio);
65	struct gpio_regs *regs;	65	struct gpio_regs *regs;
66	u32 l;	66	u32 l;
67		67
68	if (port >= ARRAY_SIZE(gpio_ports))	68	if (port >= ARRAY_SIZE(gpio_ports))
69	return -1;	69	return -1;
70		70
71	gpio &= 0x1f;	71	gpio &= 0x1f;
72		72
73	regs = (struct gpio_regs *)gpio_ports[port];	73	regs = (struct gpio_regs *)gpio_ports[port];
74		74
75	l = readl(&regs->gpio_dir);	75	l = readl(&regs->gpio_dir);
76		76
77	switch (direction) {	77	switch (direction) {
78	case MXC_GPIO_DIRECTION_OUT:	78	case MXC_GPIO_DIRECTION_OUT:
79	l \|= 1 << gpio;	79	l \|= 1 << gpio;
80	break;	80	break;
81	case MXC_GPIO_DIRECTION_IN:	81	case MXC_GPIO_DIRECTION_IN:
82	l &= ~(1 << gpio);	82	l &= ~(1 << gpio);
83	}	83	}
84	writel(l, &regs->gpio_dir);	84	writel(l, &regs->gpio_dir);
85		85
86	return 0;	86	return 0;
87	}	87	}
88		88
89	int gpio_set_value(unsigned gpio, int value)	89	int gpio_set_value(unsigned gpio, int value)
90	{	90	{
91	unsigned int port = GPIO_TO_PORT(gpio);	91	unsigned int port = GPIO_TO_PORT(gpio);
92	struct gpio_regs *regs;	92	struct gpio_regs *regs;
93	u32 l;	93	u32 l;
94		94
95	if (port >= ARRAY_SIZE(gpio_ports))	95	if (port >= ARRAY_SIZE(gpio_ports))
96	return -1;	96	return -1;
97		97
98	gpio &= 0x1f;	98	gpio &= 0x1f;
99		99
100	regs = (struct gpio_regs *)gpio_ports[port];	100	regs = (struct gpio_regs *)gpio_ports[port];
101		101
102	l = readl(&regs->gpio_dr);	102	l = readl(&regs->gpio_dr);
103	if (value)	103	if (value)
104	l \|= 1 << gpio;	104	l \|= 1 << gpio;
105	else	105	else
106	l &= ~(1 << gpio);	106	l &= ~(1 << gpio);
107	writel(l, &regs->gpio_dr);	107	writel(l, &regs->gpio_dr);
108		108
109	return 0;	109	return 0;
110	}	110	}
111		111
112	int gpio_get_value(unsigned gpio)	112	int gpio_get_value(unsigned gpio)
113	{	113	{
114	unsigned int port = GPIO_TO_PORT(gpio);	114	unsigned int port = GPIO_TO_PORT(gpio);
115	struct gpio_regs *regs;	115	struct gpio_regs *regs;
116	u32 val;	116	u32 val;
117		117
118	if (port >= ARRAY_SIZE(gpio_ports))	118	if (port >= ARRAY_SIZE(gpio_ports))
119	return -1;	119	return -1;
120		120
121	gpio &= 0x1f;	121	gpio &= 0x1f;
122		122
123	regs = (struct gpio_regs *)gpio_ports[port];	123	regs = (struct gpio_regs *)gpio_ports[port];
124		124
125	val = (readl(&regs->gpio_psr) >> gpio) & 0x01;	125	val = (readl(&regs->gpio_psr) >> gpio) & 0x01;
126		126
127	return val;	127	return val;
128	}	128	}
129		129
130	int gpio_request(unsigned gpio, const char *label)	130	int gpio_request(unsigned gpio, const char *label)
131	{	131	{
132	unsigned int port = GPIO_TO_PORT(gpio);	132	unsigned int port = GPIO_TO_PORT(gpio);
133	if (port >= ARRAY_SIZE(gpio_ports))	133	if (port >= ARRAY_SIZE(gpio_ports))
134	return -1;	134	return -1;
135	return 0;	135	return 0;
136	}	136	}
137		137
138	int gpio_free(unsigned gpio)	138	int gpio_free(unsigned gpio)
139	{	139	{
140	return 0;	140	return 0;
141	}	141	}
142		142
143	int gpio_direction_input(unsigned gpio)	143	int gpio_direction_input(unsigned gpio)
144	{	144	{
145	return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_IN);	145	return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_IN);
146	}	146	}
147		147
148	int gpio_direction_output(unsigned gpio, int value)	148	int gpio_direction_output(unsigned gpio, int value)
149	{	149	{
150	int ret = gpio_set_value(gpio, value);	150	int ret = gpio_set_value(gpio, value);
151		151
152	if (ret < 0)	152	if (ret < 0)
153	return ret;	153	return ret;
154		154
155	return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_OUT);	155	return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_OUT);
156	}	156	}
157	#endif	157	#endif
158		158
159	#ifdef CONFIG_DM_GPIO	159	#ifdef CONFIG_DM_GPIO
160	#include <fdtdec.h>	160	#include <fdtdec.h>
161	DECLARE_GLOBAL_DATA_PTR;	161	DECLARE_GLOBAL_DATA_PTR;
162		162
163	static int mxc_gpio_is_output(struct gpio_regs *regs, int offset)	163	static int mxc_gpio_is_output(struct gpio_regs *regs, int offset)
164	{	164	{
165	u32 val;	165	u32 val;
166		166
167	val = readl(&regs->gpio_dir);	167	val = readl(&regs->gpio_dir);
168		168
169	return val & (1 << offset) ? 1 : 0;	169	return val & (1 << offset) ? 1 : 0;
170	}	170	}
171		171
172	static void mxc_gpio_bank_direction(struct gpio_regs *regs, int offset,	172	static void mxc_gpio_bank_direction(struct gpio_regs *regs, int offset,
173	enum mxc_gpio_direction direction)	173	enum mxc_gpio_direction direction)
174	{	174	{
175	u32 l;	175	u32 l;
176		176
177	l = readl(&regs->gpio_dir);	177	l = readl(&regs->gpio_dir);
178		178
179	switch (direction) {	179	switch (direction) {
180	case MXC_GPIO_DIRECTION_OUT:	180	case MXC_GPIO_DIRECTION_OUT:
181	l \|= 1 << offset;	181	l \|= 1 << offset;
182	break;	182	break;
183	case MXC_GPIO_DIRECTION_IN:	183	case MXC_GPIO_DIRECTION_IN:
184	l &= ~(1 << offset);	184	l &= ~(1 << offset);
185	}	185	}
186	writel(l, &regs->gpio_dir);	186	writel(l, &regs->gpio_dir);
187	}	187	}
188		188
189	static void mxc_gpio_bank_set_value(struct gpio_regs *regs, int offset,	189	static void mxc_gpio_bank_set_value(struct gpio_regs *regs, int offset,
190	int value)	190	int value)
191	{	191	{
192	u32 l;	192	u32 l;
193		193
194	l = readl(&regs->gpio_dr);	194	l = readl(&regs->gpio_dr);
195	if (value)	195	if (value)
196	l \|= 1 << offset;	196	l \|= 1 << offset;
197	else	197	else
198	l &= ~(1 << offset);	198	l &= ~(1 << offset);
199	writel(l, &regs->gpio_dr);	199	writel(l, &regs->gpio_dr);
200	}	200	}
201		201
202	static int mxc_gpio_bank_get_value(struct gpio_regs *regs, int offset)	202	static int mxc_gpio_bank_get_value(struct gpio_regs *regs, int offset)
203	{	203	{
204	return (readl(&regs->gpio_psr) >> offset) & 0x01;	204	return (readl(&regs->gpio_psr) >> offset) & 0x01;
205	}	205	}
206		206
207	/* set GPIO pin 'gpio' as an input */	207	/* set GPIO pin 'gpio' as an input */
208	static int mxc_gpio_direction_input(struct udevice *dev, unsigned offset)	208	static int mxc_gpio_direction_input(struct udevice *dev, unsigned offset)
209	{	209	{
210	struct mxc_bank_info *bank = dev_get_priv(dev);	210	struct mxc_bank_info *bank = dev_get_priv(dev);
211		211
212	/* Configure GPIO direction as input. */	212	/* Configure GPIO direction as input. */
213	mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_IN);	213	mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_IN);
214		214
215	return 0;	215	return 0;
216	}	216	}
217		217
218	/* set GPIO pin 'gpio' as an output, with polarity 'value' */	218	/* set GPIO pin 'gpio' as an output, with polarity 'value' */
219	static int mxc_gpio_direction_output(struct udevice *dev, unsigned offset,	219	static int mxc_gpio_direction_output(struct udevice *dev, unsigned offset,
220	int value)	220	int value)
221	{	221	{
222	struct mxc_bank_info *bank = dev_get_priv(dev);	222	struct mxc_bank_info *bank = dev_get_priv(dev);
223		223
224	/* Configure GPIO output value. */	224	/* Configure GPIO output value. */
225	mxc_gpio_bank_set_value(bank->regs, offset, value);	225	mxc_gpio_bank_set_value(bank->regs, offset, value);
226		226
227	/* Configure GPIO direction as output. */	227	/* Configure GPIO direction as output. */
228	mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_OUT);	228	mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_OUT);
229		229
230	return 0;	230	return 0;
231	}	231	}
232		232
233	/* read GPIO IN value of pin 'gpio' */	233	/* read GPIO IN value of pin 'gpio' */
234	static int mxc_gpio_get_value(struct udevice *dev, unsigned offset)	234	static int mxc_gpio_get_value(struct udevice *dev, unsigned offset)
235	{	235	{
236	struct mxc_bank_info *bank = dev_get_priv(dev);	236	struct mxc_bank_info *bank = dev_get_priv(dev);
237		237
238	return mxc_gpio_bank_get_value(bank->regs, offset);	238	return mxc_gpio_bank_get_value(bank->regs, offset);
239	}	239	}
240		240
241	/* write GPIO OUT value to pin 'gpio' */	241	/* write GPIO OUT value to pin 'gpio' */
242	static int mxc_gpio_set_value(struct udevice *dev, unsigned offset,	242	static int mxc_gpio_set_value(struct udevice *dev, unsigned offset,
243	int value)	243	int value)
244	{	244	{
245	struct mxc_bank_info *bank = dev_get_priv(dev);	245	struct mxc_bank_info *bank = dev_get_priv(dev);
246		246
247	mxc_gpio_bank_set_value(bank->regs, offset, value);	247	mxc_gpio_bank_set_value(bank->regs, offset, value);
248		248
249	return 0;	249	return 0;
250	}	250	}
251		251
252	static int mxc_gpio_get_function(struct udevice *dev, unsigned offset)	252	static int mxc_gpio_get_function(struct udevice *dev, unsigned offset)
253	{	253	{
254	struct mxc_bank_info *bank = dev_get_priv(dev);	254	struct mxc_bank_info *bank = dev_get_priv(dev);
255		255
256	/* GPIOF_FUNC is not implemented yet */	256	/* GPIOF_FUNC is not implemented yet */
257	if (mxc_gpio_is_output(bank->regs, offset))	257	if (mxc_gpio_is_output(bank->regs, offset))
258	return GPIOF_OUTPUT;	258	return GPIOF_OUTPUT;
259	else	259	else
260	return GPIOF_INPUT;	260	return GPIOF_INPUT;
261	}	261	}
262		262
263	static const struct dm_gpio_ops gpio_mxc_ops = {	263	static const struct dm_gpio_ops gpio_mxc_ops = {
264	.direction_input = mxc_gpio_direction_input,	264	.direction_input = mxc_gpio_direction_input,
265	.direction_output = mxc_gpio_direction_output,	265	.direction_output = mxc_gpio_direction_output,
266	.get_value = mxc_gpio_get_value,	266	.get_value = mxc_gpio_get_value,
267	.set_value = mxc_gpio_set_value,	267	.set_value = mxc_gpio_set_value,
268	.get_function = mxc_gpio_get_function,	268	.get_function = mxc_gpio_get_function,
269	};	269	};
270		270
271	static int mxc_gpio_probe(struct udevice *dev)	271	static int mxc_gpio_probe(struct udevice *dev)
272	{	272	{
273	struct mxc_bank_info *bank = dev_get_priv(dev);	273	struct mxc_bank_info *bank = dev_get_priv(dev);
274	struct mxc_gpio_plat *plat = dev_get_platdata(dev);	274	struct mxc_gpio_plat *plat = dev_get_platdata(dev);
275	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);	275	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
276	int banknum;	276	int banknum;
277	char name[18], *str;	277	char name[18], *str;
278		278
279	banknum = plat->bank_index;	279	banknum = plat->bank_index;
280	sprintf(name, "GPIO%d_", banknum + 1);	280	sprintf(name, "GPIO%d_", banknum + 1);
281	str = strdup(name);	281	str = strdup(name);
282	if (!str)	282	if (!str)
283	return -ENOMEM;	283	return -ENOMEM;
284	uc_priv->bank_name = str;	284	uc_priv->bank_name = str;
285	uc_priv->gpio_count = GPIO_PER_BANK;	285	uc_priv->gpio_count = GPIO_PER_BANK;
286	bank->regs = plat->regs;	286	bank->regs = plat->regs;
287		287
288	return 0;	288	return 0;
289	}	289	}
290		290
291	static int mxc_gpio_bind(struct udevice *dev)	291	static int mxc_gpio_bind(struct udevice *dev)
292	{	292	{
293	struct mxc_gpio_plat *plat = dev->platdata;	293	struct mxc_gpio_plat *plat = dev->platdata;
294	fdt_addr_t addr;	294	fdt_addr_t addr;
295		295
296	/*	296	/*
297	* If platdata already exsits, directly return.	297	* If platdata already exsits, directly return.
298	* Actually only when DT is not supported, platdata	298	* Actually only when DT is not supported, platdata
299	* is statically initialized in U_BOOT_DEVICES.Here	299	* is statically initialized in U_BOOT_DEVICES.Here
300	* will return.	300	* will return.
301	*/	301	*/
302	if (plat)	302	if (plat)
303	return 0;	303	return 0;
304		304
305	addr = devfdt_get_addr(dev);	305	addr = devfdt_get_addr(dev);
306	if (addr == FDT_ADDR_T_NONE)	306	if (addr == FDT_ADDR_T_NONE)
307	return -EINVAL;	307	return -EINVAL;
308		308
309	/*	309	/*
310	* TODO:	310	* TODO:
311	* When every board is converted to driver model and DT is supported,	311	* When every board is converted to driver model and DT is supported,
312	* this can be done by auto-alloc feature, but not using calloc	312	* this can be done by auto-alloc feature, but not using calloc
313	* to alloc memory for platdata.	313	* to alloc memory for platdata.
314	*	314	*
315	* For example mxc_plat below uses platform data rather than device	315	* For example mxc_plat below uses platform data rather than device
316	* tree.	316	* tree.
317	*	317	*
318	* NOTE: DO NOT COPY this code if you are using device tree.	318	* NOTE: DO NOT COPY this code if you are using device tree.
319	*/	319	*/
320	plat = calloc(1, sizeof(*plat));	320	plat = calloc(1, sizeof(*plat));
321	if (!plat)	321	if (!plat)
322	return -ENOMEM;	322	return -ENOMEM;
323		323
324	plat->regs = (struct gpio_regs *)addr;	324	plat->regs = (struct gpio_regs *)addr;
325	plat->bank_index = dev->req_seq;	325	plat->bank_index = dev->req_seq;
326	dev->platdata = plat;	326	dev->platdata = plat;
327		327
328	return 0;	328	return 0;
329	}	329	}
330		330
331	static const struct udevice_id mxc_gpio_ids[] = {	331	static const struct udevice_id mxc_gpio_ids[] = {
332	{ .compatible = "fsl,imx35-gpio" },	332	{ .compatible = "fsl,imx35-gpio" },
333	{ }	333	{ }
334	};	334	};
335		335
336	U_BOOT_DRIVER(gpio_mxc) = {	336	U_BOOT_DRIVER(gpio_mxc) = {
337	.name = "gpio_mxc",	337	.name = "gpio_mxc",
338	.id = UCLASS_GPIO,	338	.id = UCLASS_GPIO,
339	.ops = &gpio_mxc_ops,	339	.ops = &gpio_mxc_ops,
340	.probe = mxc_gpio_probe,	340	.probe = mxc_gpio_probe,
341	.priv_auto_alloc_size = sizeof(struct mxc_bank_info),	341	.priv_auto_alloc_size = sizeof(struct mxc_bank_info),
342	.of_match = mxc_gpio_ids,	342	.of_match = mxc_gpio_ids,
343	.bind = mxc_gpio_bind,	343	.bind = mxc_gpio_bind,
344	};	344	};
345		345
346	#if !CONFIG_IS_ENABLED(OF_CONTROL)	346	#if !CONFIG_IS_ENABLED(OF_CONTROL)
347	static const struct mxc_gpio_plat mxc_plat[] = {	347	static const struct mxc_gpio_plat mxc_plat[] = {
348	{ 0, (struct gpio_regs *)GPIO1_BASE_ADDR },	348	{ 0, (struct gpio_regs *)GPIO1_BASE_ADDR },
349	{ 1, (struct gpio_regs *)GPIO2_BASE_ADDR },	349	{ 1, (struct gpio_regs *)GPIO2_BASE_ADDR },
350	{ 2, (struct gpio_regs *)GPIO3_BASE_ADDR },	350	{ 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
351	#if defined(CONFIG_MX25) \|\| defined(CONFIG_MX27) \|\| defined(CONFIG_MX51) \|\| \	351	#if defined(CONFIG_MX25) \|\| defined(CONFIG_MX27) \|\| defined(CONFIG_MX51) \|\| \
352	defined(CONFIG_MX53) \|\| defined(CONFIG_MX6)	352	defined(CONFIG_MX53) \|\| defined(CONFIG_MX6)
353	{ 3, (struct gpio_regs *)GPIO4_BASE_ADDR },	353	{ 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
354	#endif	354	#endif
355	#if defined(CONFIG_MX27) \|\| defined(CONFIG_MX53) \|\| defined(CONFIG_MX6)	355	#if defined(CONFIG_MX27) \|\| defined(CONFIG_MX53) \|\| defined(CONFIG_MX6)
356	{ 4, (struct gpio_regs *)GPIO5_BASE_ADDR },	356	{ 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
357	{ 5, (struct gpio_regs *)GPIO6_BASE_ADDR },	357	{ 5, (struct gpio_regs *)GPIO6_BASE_ADDR },
358	#endif	358	#endif
359	#if defined(CONFIG_MX53) \|\| defined(CONFIG_MX6)	359	#if defined(CONFIG_MX53) \|\| defined(CONFIG_MX6)
360	{ 6, (struct gpio_regs *)GPIO7_BASE_ADDR },	360	{ 6, (struct gpio_regs *)GPIO7_BASE_ADDR },
361	#endif	361	#endif
362	};	362	};
363		363
364	U_BOOT_DEVICES(mxc_gpios) = {	364	U_BOOT_DEVICES(mxc_gpios) = {
365	{ "gpio_mxc", &mxc_plat[0] },	365	{ "gpio_mxc", &mxc_plat[0] },
366	{ "gpio_mxc", &mxc_plat[1] },	366	{ "gpio_mxc", &mxc_plat[1] },
367	{ "gpio_mxc", &mxc_plat[2] },	367	{ "gpio_mxc", &mxc_plat[2] },
368	#if defined(CONFIG_MX25) \|\| defined(CONFIG_MX27) \|\| defined(CONFIG_MX51) \|\| \	368	#if defined(CONFIG_MX25) \|\| defined(CONFIG_MX27) \|\| defined(CONFIG_MX51) \|\| \
369	defined(CONFIG_MX53) \|\| defined(CONFIG_MX6)	369	defined(CONFIG_MX53) \|\| defined(CONFIG_MX6)
370	{ "gpio_mxc", &mxc_plat[3] },	370	{ "gpio_mxc", &mxc_plat[3] },
371	#endif	371	#endif
372	#if defined(CONFIG_MX27) \|\| defined(CONFIG_MX53) \|\| defined(CONFIG_MX6)	372	#if defined(CONFIG_MX27) \|\| defined(CONFIG_MX53) \|\| defined(CONFIG_MX6)
373	{ "gpio_mxc", &mxc_plat[4] },	373	{ "gpio_mxc", &mxc_plat[4] },
374	{ "gpio_mxc", &mxc_plat[5] },	374	{ "gpio_mxc", &mxc_plat[5] },
375	#endif	375	#endif
376	#if defined(CONFIG_MX53) \|\| defined(CONFIG_MX6)	376	#if defined(CONFIG_MX53) \|\| defined(CONFIG_MX6)
377	{ "gpio_mxc", &mxc_plat[6] },	377	{ "gpio_mxc", &mxc_plat[6] },
378	#endif	378	#endif
379	};	379	};
380	#endif	380	#endif
381	#endif	381	#endif
382		382

include/configs/imx6_spl.h

Diff comments View file @ 290e7cf

 /*
  * Copyright (C) 2014 Gateworks Corporation
  * Author: Tim Harvey <tharvey@gateworks.com>
  *
  * SPDX-License-Identifier:     GPL-2.0+
  */
 #ifndef __IMX6_SPL_CONFIG_H
 #define __IMX6_SPL_CONFIG_H
 #ifdef CONFIG_SPL
 #define CONFIG_SPL_FRAMEWORK
 /*
  * see Figure 8-3 in IMX6DQ/IMX6SDL Reference manuals:
  *  - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091FFFF
  *  - IMX6DQ has 2x IRAM of IMX6SDL but we intend to support IMX6SDL as well
  *  - BOOT ROM stack is at 0x0091FFB8
  *  - if icache/dcache is enabled (eFuse/strapping controlled) then the
  *    IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to
  *    fit between 0x00907000 and 0x00918000.
  *  - Additionally the BOOT ROM loads what they consider the firmware image
  *    which consists of a 4K header in front of us that contains the IVT, DCD
  *    and some padding thus 'our' max size is really 0x00908000 - 0x00918000
  *    or 64KB
  */
 #define CONFIG_SPL_TEXT_BASE		0x00908000
 #define CONFIG_SPL_MAX_SIZE		0x10000
 #define CONFIG_SPL_STACK		0x0091FFB8
 /*
  * Pad SPL to 68KB (4KB header + 64KB max size). This allows to write the
  * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a
  * boot media (given that boot media specific offset is configured properly).
  */
 #define CONFIG_SPL_PAD_TO		0x11000
 /* MMC support */
 #if defined(CONFIG_SPL_MMC_SUPPORT)
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
 #define CONFIG_SYS_MONITOR_LEN			409600	/* 400 KB */
 #endif
 /* SATA support */
 #if defined(CONFIG_SPL_SATA_SUPPORT)
 #define CONFIG_SPL_SATA_BOOT_DEVICE		0
 #define CONFIG_SYS_SATA_FAT_BOOT_PARTITION	1
 #endif
 /* Define the payload for FAT/EXT support */
 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
 # ifdef CONFIG_OF_CONTROL
 #  define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot-dtb.img"
 # else
 #  define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
 # endif
 #endif
-#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6SL)
+#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL) || \
+	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
 #define CONFIG_SPL_BSS_START_ADDR      0x88200000
 #define CONFIG_SPL_BSS_MAX_SIZE        0x100000		/* 1 MB */
 #define CONFIG_SYS_SPL_MALLOC_START    0x88300000
 #define CONFIG_SYS_SPL_MALLOC_SIZE     0x100000		/* 1 MB */
 #define CONFIG_SYS_TEXT_BASE           0x87800000
 #else
 #define CONFIG_SPL_BSS_START_ADDR	0x18200000
 #define CONFIG_SPL_BSS_MAX_SIZE		0x100000	/* 1 MB */
 #define CONFIG_SYS_SPL_MALLOC_START	0x18300000
 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000	/* 1 MB */
 #define CONFIG_SYS_TEXT_BASE		0x17800000
 #endif
 #endif
 #endif

include/configs/mx6_common.h

Diff comments View file @ 290e7cf

 /*
  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
  *
  * SPDX-License-Identifier:	GPL-2.0
  */
 #ifndef __MX6_COMMON_H
 #define __MX6_COMMON_H
-#ifndef CONFIG_MX6UL
+#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
 #ifndef CONFIG_SYS_L2CACHE_OFF
 #define CONFIG_SYS_L2_PL310
 #define CONFIG_SYS_PL310_BASE	L2_PL310_BASE
 #endif
 #define CONFIG_MP
 #endif
 #define CONFIG_BOARD_POSTCLK_INIT
 #define CONFIG_MXC_GPT_HCLK
 #define CONFIG_SYS_BOOTM_LEN	0x1000000
 #include <linux/sizes.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/mach-imx/gpio.h>
 #ifndef CONFIG_MX6
 #define CONFIG_MX6
 #endif
 #define CONFIG_SYS_FSL_CLK
 /* ATAGs */
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
 #define CONFIG_REVISION_TAG
 /* Boot options */
-#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL) || \
+#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
-	defined(CONFIG_MX6UL) || defined(CONFIG_MX6SLL))
+	defined(CONFIG_MX6SX) || \
+	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
 #define CONFIG_LOADADDR		0x82000000
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE	0x87800000
 #endif
 #else
 #define CONFIG_LOADADDR		0x12000000
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE	0x17800000
 #endif
 #endif
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX       1
 /* Filesystems and image support */
 #define CONFIG_SUPPORT_RAW_INITRD
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE	512
 #define CONFIG_SYS_MAXARGS	32
 /* GPIO */
 #define CONFIG_MXC_GPIO
 /* MMC */
 #define CONFIG_BOUNCE_BUFFER
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
 /* Fuses */
 #define CONFIG_MXC_OCOTP
 /* Secure boot (HAB) support */
 #ifdef CONFIG_SECURE_BOOT
 #define CONFIG_CSF_SIZE			0x2000
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
 #endif
 #endif
 #endif

1	/*	1	/*
2	* Copyright (C) 2015 Freescale Semiconductor, Inc.	2	* Copyright (C) 2015 Freescale Semiconductor, Inc.
3	*	3	*
4	* SPDX-License-Identifier: GPL-2.0+	4	* SPDX-License-Identifier: GPL-2.0+
5	*/	5	*/
6		6
7	#ifndef __ASM_ARCH_MX6UL_DDR_H__	7	#ifndef __ASM_ARCH_MX6UL_DDR_H__
8	#define __ASM_ARCH_MX6UL_DDR_H__	8	#define __ASM_ARCH_MX6UL_DDR_H__
9		9
10	#ifndef CONFIG_MX6UL	10	#if !(defined(CONFIG_MX6UL) \|\| defined(CONFIG_MX6ULL))
11	#error "wrong CPU"	11	#error "wrong CPU"
12	#endif	12	#endif
13		13
14	#define MX6_IOM_DRAM_DQM0 0x020e0244	14	#define MX6_IOM_DRAM_DQM0 0x020e0244
15	#define MX6_IOM_DRAM_DQM1 0x020e0248	15	#define MX6_IOM_DRAM_DQM1 0x020e0248
16		16
17	#define MX6_IOM_DRAM_RAS 0x020e024c	17	#define MX6_IOM_DRAM_RAS 0x020e024c
18	#define MX6_IOM_DRAM_CAS 0x020e0250	18	#define MX6_IOM_DRAM_CAS 0x020e0250
19	#define MX6_IOM_DRAM_CS0 0x020e0254	19	#define MX6_IOM_DRAM_CS0 0x020e0254
20	#define MX6_IOM_DRAM_CS1 0x020e0258	20	#define MX6_IOM_DRAM_CS1 0x020e0258
21	#define MX6_IOM_DRAM_SDWE_B 0x020e025c	21	#define MX6_IOM_DRAM_SDWE_B 0x020e025c
22	#define MX6_IOM_DRAM_SDODT0 0x020e0260	22	#define MX6_IOM_DRAM_SDODT0 0x020e0260
23	#define MX6_IOM_DRAM_SDODT1 0x020e0264	23	#define MX6_IOM_DRAM_SDODT1 0x020e0264
24	#define MX6_IOM_DRAM_SDBA0 0x020e0268	24	#define MX6_IOM_DRAM_SDBA0 0x020e0268
25	#define MX6_IOM_DRAM_SDBA1 0x020e026c	25	#define MX6_IOM_DRAM_SDBA1 0x020e026c
26	#define MX6_IOM_DRAM_SDBA2 0x020e0270	26	#define MX6_IOM_DRAM_SDBA2 0x020e0270
27	#define MX6_IOM_DRAM_SDCKE0 0x020e0274	27	#define MX6_IOM_DRAM_SDCKE0 0x020e0274
28	#define MX6_IOM_DRAM_SDCKE1 0x020e0278	28	#define MX6_IOM_DRAM_SDCKE1 0x020e0278
29	#define MX6_IOM_DRAM_SDCLK_0 0x020e027c	29	#define MX6_IOM_DRAM_SDCLK_0 0x020e027c
30	#define MX6_IOM_DRAM_SDQS0 0x020e0280	30	#define MX6_IOM_DRAM_SDQS0 0x020e0280
31	#define MX6_IOM_DRAM_SDQS1 0x020e0284	31	#define MX6_IOM_DRAM_SDQS1 0x020e0284
32	#define MX6_IOM_DRAM_RESET 0x020e0288	32	#define MX6_IOM_DRAM_RESET 0x020e0288
33		33
34	#define MX6_IOM_GRP_ADDDS 0x020e0490	34	#define MX6_IOM_GRP_ADDDS 0x020e0490
35	#define MX6_IOM_DDRMODE_CTL 0x020e0494	35	#define MX6_IOM_DDRMODE_CTL 0x020e0494
36	#define MX6_IOM_GRP_B0DS 0x020e0498	36	#define MX6_IOM_GRP_B0DS 0x020e0498
37	#define MX6_IOM_GRP_DDRPK 0x020e049c	37	#define MX6_IOM_GRP_DDRPK 0x020e049c
38	#define MX6_IOM_GRP_CTLDS 0x020e04a0	38	#define MX6_IOM_GRP_CTLDS 0x020e04a0
39	#define MX6_IOM_GRP_B1DS 0x020e04a4	39	#define MX6_IOM_GRP_B1DS 0x020e04a4
40	#define MX6_IOM_GRP_DDRHYS 0x020e04a8	40	#define MX6_IOM_GRP_DDRHYS 0x020e04a8
41	#define MX6_IOM_GRP_DDRPKE 0x020e04ac	41	#define MX6_IOM_GRP_DDRPKE 0x020e04ac
42	#define MX6_IOM_GRP_DDRMODE 0x020e04b0	42	#define MX6_IOM_GRP_DDRMODE 0x020e04b0
43	#define MX6_IOM_GRP_DDR_TYPE 0x020e04b4	43	#define MX6_IOM_GRP_DDR_TYPE 0x020e04b4
44		44
45	#endif /__ASM_ARCH_MX6SX_DDR_H__ /	45	#endif /__ASM_ARCH_MX6SX_DDR_H__ /
46		46

1	/*	1	/*
2	* Based on Linux i.MX iomux-v3.h file:	2	* Based on Linux i.MX iomux-v3.h file:
3	* Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,	3	* Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
4	* <armlinux@phytec.de>	4	* <armlinux@phytec.de>
5	*	5	*
6	* Copyright (C) 2011 Freescale Semiconductor, Inc.	6	* Copyright (C) 2011 Freescale Semiconductor, Inc.
7	*	7	*
8	* SPDX-License-Identifier: GPL-2.0+	8	* SPDX-License-Identifier: GPL-2.0+
9	*/	9	*/
10		10
11	#ifndef __MACH_IOMUX_V3_H__	11	#ifndef __MACH_IOMUX_V3_H__
12	#define __MACH_IOMUX_V3_H__	12	#define __MACH_IOMUX_V3_H__
13		13
14	#include <common.h>	14	#include <common.h>
15		15
16	/*	16	/*
17	* build IOMUX_PAD structure	17	* build IOMUX_PAD structure
18	*	18	*
19	* This iomux scheme is based around pads, which are the physical balls	19	* This iomux scheme is based around pads, which are the physical balls
20	* on the processor.	20	* on the processor.
21	*	21	*
22	* - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls	22	* - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
23	* things like driving strength and pullup/pulldown.	23	* things like driving strength and pullup/pulldown.
24	* - Each pad can have but not necessarily does have an output routing register	24	* - Each pad can have but not necessarily does have an output routing register
25	* (IOMUXC_SW_MUX_CTL_PAD_x).	25	* (IOMUXC_SW_MUX_CTL_PAD_x).
26	* - Each pad can have but not necessarily does have an input routing register	26	* - Each pad can have but not necessarily does have an input routing register
27	* (IOMUXC_x_SELECT_INPUT)	27	* (IOMUXC_x_SELECT_INPUT)
28	*	28	*
29	* The three register sets do not have a fixed offset to each other,	29	* The three register sets do not have a fixed offset to each other,
30	* hence we order this table by pad control registers (which all pads	30	* hence we order this table by pad control registers (which all pads
31	* have) and put the optional i/o routing registers into additional	31	* have) and put the optional i/o routing registers into additional
32	* fields.	32	* fields.
33	*	33	*
34	* The naming convention for the pad modes is SOC_PAD_<padname>__<padmode>	34	* The naming convention for the pad modes is SOC_PAD_<padname>__<padmode>
35	* If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>	35	* If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
36	*	36	*
37	* IOMUX/PAD Bit field definitions	37	* IOMUX/PAD Bit field definitions
38	*	38	*
39	* MUX_CTRL_OFS: 0..11 (12)	39	* MUX_CTRL_OFS: 0..11 (12)
40	* PAD_CTRL_OFS: 12..23 (12)	40	* PAD_CTRL_OFS: 12..23 (12)
41	* SEL_INPUT_OFS: 24..35 (12)	41	* SEL_INPUT_OFS: 24..35 (12)
42	* MUX_MODE + SION + LPSR: 36..41 (6)	42	* MUX_MODE + SION + LPSR: 36..41 (6)
43	* PAD_CTRL + NO_PAD_CTRL: 42..59 (18)	43	* PAD_CTRL + NO_PAD_CTRL: 42..59 (18)
44	* SEL_INP: 60..63 (4)	44	* SEL_INP: 60..63 (4)
45	*/	45	*/
46		46
47	typedef u64 iomux_v3_cfg_t;	47	typedef u64 iomux_v3_cfg_t;
48		48
49	#define MUX_CTRL_OFS_SHIFT 0	49	#define MUX_CTRL_OFS_SHIFT 0
50	#define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)	50	#define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
51	#define MUX_PAD_CTRL_OFS_SHIFT 12	51	#define MUX_PAD_CTRL_OFS_SHIFT 12
52	#define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << \	52	#define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << \
53	MUX_PAD_CTRL_OFS_SHIFT)	53	MUX_PAD_CTRL_OFS_SHIFT)
54	#define MUX_SEL_INPUT_OFS_SHIFT 24	54	#define MUX_SEL_INPUT_OFS_SHIFT 24
55	#define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << \	55	#define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << \
56	MUX_SEL_INPUT_OFS_SHIFT)	56	MUX_SEL_INPUT_OFS_SHIFT)
57		57
58	#define MUX_MODE_SHIFT 36	58	#define MUX_MODE_SHIFT 36
59	#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x3f << MUX_MODE_SHIFT)	59	#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x3f << MUX_MODE_SHIFT)
60	#define MUX_PAD_CTRL_SHIFT 42	60	#define MUX_PAD_CTRL_SHIFT 42
61	#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT)	61	#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT)
62	#define MUX_SEL_INPUT_SHIFT 60	62	#define MUX_SEL_INPUT_SHIFT 60
63	#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)	63	#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
64		64
65	#define MUX_MODE_SION ((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \	65	#define MUX_MODE_SION ((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \
66	MUX_MODE_SHIFT)	66	MUX_MODE_SHIFT)
67	#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)	67	#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
68		68
69	#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \	69	#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \
70	sel_input, pad_ctrl) \	70	sel_input, pad_ctrl) \
71	(((iomux_v3_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) \| \	71	(((iomux_v3_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) \| \
72	((iomux_v3_cfg_t)(mux_mode) << MUX_MODE_SHIFT) \| \	72	((iomux_v3_cfg_t)(mux_mode) << MUX_MODE_SHIFT) \| \
73	((iomux_v3_cfg_t)(pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) \| \	73	((iomux_v3_cfg_t)(pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) \| \
74	((iomux_v3_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) \| \	74	((iomux_v3_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) \| \
75	((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)\| \	75	((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)\| \
76	((iomux_v3_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT))	76	((iomux_v3_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT))
77		77
78	#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) \| \	78	#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) \| \
79	MUX_PAD_CTRL(pad))	79	MUX_PAD_CTRL(pad))
80		80
81	#define __NA_ 0x000	81	#define __NA_ 0x000
82	#define NO_MUX_I 0	82	#define NO_MUX_I 0
83	#define NO_PAD_I 0	83	#define NO_PAD_I 0
84		84
85	#define NO_PAD_CTRL (1 << 17)	85	#define NO_PAD_CTRL (1 << 17)
86		86
87	#define IOMUX_CONFIG_LPSR 0x20	87	#define IOMUX_CONFIG_LPSR 0x20
88	#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \	88	#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
89	MUX_MODE_SHIFT)	89	MUX_MODE_SHIFT)
90	#ifdef CONFIG_MX7	90	#ifdef CONFIG_MX7
91		91
92	#define IOMUX_LPSR_SEL_INPUT_OFS 0x70000	92	#define IOMUX_LPSR_SEL_INPUT_OFS 0x70000
93		93
94	#define PAD_CTL_DSE_1P8V_140OHM (0x0<<0)	94	#define PAD_CTL_DSE_1P8V_140OHM (0x0<<0)
95	#define PAD_CTL_DSE_1P8V_35OHM (0x1<<0)	95	#define PAD_CTL_DSE_1P8V_35OHM (0x1<<0)
96	#define PAD_CTL_DSE_1P8V_70OHM (0x2<<0)	96	#define PAD_CTL_DSE_1P8V_70OHM (0x2<<0)
97	#define PAD_CTL_DSE_1P8V_23OHM (0x3<<0)	97	#define PAD_CTL_DSE_1P8V_23OHM (0x3<<0)
98		98
99	#define PAD_CTL_DSE_3P3V_196OHM (0x0<<0)	99	#define PAD_CTL_DSE_3P3V_196OHM (0x0<<0)
100	#define PAD_CTL_DSE_3P3V_49OHM (0x1<<0)	100	#define PAD_CTL_DSE_3P3V_49OHM (0x1<<0)
101	#define PAD_CTL_DSE_3P3V_98OHM (0x2<<0)	101	#define PAD_CTL_DSE_3P3V_98OHM (0x2<<0)
102	#define PAD_CTL_DSE_3P3V_32OHM (0x3<<0)	102	#define PAD_CTL_DSE_3P3V_32OHM (0x3<<0)
103		103
104	#define PAD_CTL_SRE_FAST (0 << 2)	104	#define PAD_CTL_SRE_FAST (0 << 2)
105	#define PAD_CTL_SRE_SLOW (0x1 << 2)	105	#define PAD_CTL_SRE_SLOW (0x1 << 2)
106		106
107	#define PAD_CTL_HYS (0x1 << 3)	107	#define PAD_CTL_HYS (0x1 << 3)
108	#define PAD_CTL_PUE (0x1 << 4)	108	#define PAD_CTL_PUE (0x1 << 4)
109		109
110	#define PAD_CTL_PUS_PD100KOHM ((0x0 << 5) \| PAD_CTL_PUE)	110	#define PAD_CTL_PUS_PD100KOHM ((0x0 << 5) \| PAD_CTL_PUE)
111	#define PAD_CTL_PUS_PU5KOHM ((0x1 << 5) \| PAD_CTL_PUE)	111	#define PAD_CTL_PUS_PU5KOHM ((0x1 << 5) \| PAD_CTL_PUE)
112	#define PAD_CTL_PUS_PU47KOHM ((0x2 << 5) \| PAD_CTL_PUE)	112	#define PAD_CTL_PUS_PU47KOHM ((0x2 << 5) \| PAD_CTL_PUE)
113	#define PAD_CTL_PUS_PU100KOHM ((0x3 << 5) \| PAD_CTL_PUE)	113	#define PAD_CTL_PUS_PU100KOHM ((0x3 << 5) \| PAD_CTL_PUE)
114		114
115	#else	115	#else
116		116
117	#ifdef CONFIG_MX6	117	#ifdef CONFIG_MX6
118		118
119	#define PAD_CTL_HYS (1 << 16)	119	#define PAD_CTL_HYS (1 << 16)
120		120
121	#define PAD_CTL_PUS_100K_DOWN (0 << 14 \| PAD_CTL_PUE)	121	#define PAD_CTL_PUS_100K_DOWN (0 << 14 \| PAD_CTL_PUE)
122	#define PAD_CTL_PUS_47K_UP (1 << 14 \| PAD_CTL_PUE)	122	#define PAD_CTL_PUS_47K_UP (1 << 14 \| PAD_CTL_PUE)
123	#define PAD_CTL_PUS_100K_UP (2 << 14 \| PAD_CTL_PUE)	123	#define PAD_CTL_PUS_100K_UP (2 << 14 \| PAD_CTL_PUE)
124	#define PAD_CTL_PUS_22K_UP (3 << 14 \| PAD_CTL_PUE)	124	#define PAD_CTL_PUS_22K_UP (3 << 14 \| PAD_CTL_PUE)
125	#define PAD_CTL_PUE (1 << 13 \| PAD_CTL_PKE)	125	#define PAD_CTL_PUE (1 << 13 \| PAD_CTL_PKE)
126	#define PAD_CTL_PKE (1 << 12)	126	#define PAD_CTL_PKE (1 << 12)
127		127
128	#define PAD_CTL_ODE (1 << 11)	128	#define PAD_CTL_ODE (1 << 11)
129		129
130	#if defined(CONFIG_MX6SX) \|\| defined(CONFIG_MX6UL)	130	#if defined(CONFIG_MX6SX) \|\| defined(CONFIG_MX6UL) \|\| defined(CONFIG_MX6ULL)
131	#define PAD_CTL_SPEED_LOW (0 << 6)	131	#define PAD_CTL_SPEED_LOW (0 << 6)
132	#else	132	#else
133	#define PAD_CTL_SPEED_LOW (1 << 6)	133	#define PAD_CTL_SPEED_LOW (1 << 6)
134	#endif	134	#endif
135	#define PAD_CTL_SPEED_MED (2 << 6)	135	#define PAD_CTL_SPEED_MED (2 << 6)
136	#define PAD_CTL_SPEED_HIGH (3 << 6)	136	#define PAD_CTL_SPEED_HIGH (3 << 6)
137		137
138	#define PAD_CTL_DSE_DISABLE (0 << 3)	138	#define PAD_CTL_DSE_DISABLE (0 << 3)
139	#define PAD_CTL_DSE_240ohm (1 << 3)	139	#define PAD_CTL_DSE_240ohm (1 << 3)
140	#define PAD_CTL_DSE_120ohm (2 << 3)	140	#define PAD_CTL_DSE_120ohm (2 << 3)
141	#define PAD_CTL_DSE_80ohm (3 << 3)	141	#define PAD_CTL_DSE_80ohm (3 << 3)
142	#define PAD_CTL_DSE_60ohm (4 << 3)	142	#define PAD_CTL_DSE_60ohm (4 << 3)
143	#define PAD_CTL_DSE_48ohm (5 << 3)	143	#define PAD_CTL_DSE_48ohm (5 << 3)
144	#define PAD_CTL_DSE_40ohm (6 << 3)	144	#define PAD_CTL_DSE_40ohm (6 << 3)
145	#define PAD_CTL_DSE_34ohm (7 << 3)	145	#define PAD_CTL_DSE_34ohm (7 << 3)
146		146
147	/* i.MX6SL/SLL */	147	/* i.MX6SL/SLL */
148	#define PAD_CTL_LVE (1 << 1)	148	#define PAD_CTL_LVE (1 << 1)
149	#define PAD_CTL_LVE_BIT (1 << 22)	149	#define PAD_CTL_LVE_BIT (1 << 22)
150		150
151	/* i.MX6SLL */	151	/* i.MX6SLL */
152	#define PAD_CTL_IPD_BIT (1 << 27)	152	#define PAD_CTL_IPD_BIT (1 << 27)
153		153
154	#elif defined(CONFIG_VF610)	154	#elif defined(CONFIG_VF610)
155		155
156	#define PAD_MUX_MODE_SHIFT 20	156	#define PAD_MUX_MODE_SHIFT 20
157		157
158	#define PAD_CTL_INPUT_DIFFERENTIAL (1 << 16)	158	#define PAD_CTL_INPUT_DIFFERENTIAL (1 << 16)
159		159
160	#define PAD_CTL_SPEED_MED (1 << 12)	160	#define PAD_CTL_SPEED_MED (1 << 12)
161	#define PAD_CTL_SPEED_HIGH (3 << 12)	161	#define PAD_CTL_SPEED_HIGH (3 << 12)
162		162
163	#define PAD_CTL_SRE (1 << 11)	163	#define PAD_CTL_SRE (1 << 11)
164		164
165	#define PAD_CTL_ODE (1 << 10)	165	#define PAD_CTL_ODE (1 << 10)
166		166
167	#define PAD_CTL_DSE_150ohm (1 << 6)	167	#define PAD_CTL_DSE_150ohm (1 << 6)
168	#define PAD_CTL_DSE_75ohm (2 << 6)	168	#define PAD_CTL_DSE_75ohm (2 << 6)
169	#define PAD_CTL_DSE_50ohm (3 << 6)	169	#define PAD_CTL_DSE_50ohm (3 << 6)
170	#define PAD_CTL_DSE_37ohm (4 << 6)	170	#define PAD_CTL_DSE_37ohm (4 << 6)
171	#define PAD_CTL_DSE_30ohm (5 << 6)	171	#define PAD_CTL_DSE_30ohm (5 << 6)
172	#define PAD_CTL_DSE_25ohm (6 << 6)	172	#define PAD_CTL_DSE_25ohm (6 << 6)
173	#define PAD_CTL_DSE_20ohm (7 << 6)	173	#define PAD_CTL_DSE_20ohm (7 << 6)
174		174
175	#define PAD_CTL_PUS_47K_UP (1 << 4 \| PAD_CTL_PUE)	175	#define PAD_CTL_PUS_47K_UP (1 << 4 \| PAD_CTL_PUE)
176	#define PAD_CTL_PUS_100K_UP (2 << 4 \| PAD_CTL_PUE)	176	#define PAD_CTL_PUS_100K_UP (2 << 4 \| PAD_CTL_PUE)
177	#define PAD_CTL_PUS_22K_UP (3 << 4 \| PAD_CTL_PUE)	177	#define PAD_CTL_PUS_22K_UP (3 << 4 \| PAD_CTL_PUE)
178	#define PAD_CTL_PKE (1 << 3)	178	#define PAD_CTL_PKE (1 << 3)
179	#define PAD_CTL_PUE (1 << 2 \| PAD_CTL_PKE)	179	#define PAD_CTL_PUE (1 << 2 \| PAD_CTL_PKE)
180		180
181	#define PAD_CTL_OBE_IBE_ENABLE (3 << 0)	181	#define PAD_CTL_OBE_IBE_ENABLE (3 << 0)
182	#define PAD_CTL_OBE_ENABLE (1 << 1)	182	#define PAD_CTL_OBE_ENABLE (1 << 1)
183	#define PAD_CTL_IBE_ENABLE (1 << 0)	183	#define PAD_CTL_IBE_ENABLE (1 << 0)
184		184
185	#else	185	#else
186		186
187	#define PAD_CTL_DVS (1 << 13)	187	#define PAD_CTL_DVS (1 << 13)
188	#define PAD_CTL_INPUT_DDR (1 << 9)	188	#define PAD_CTL_INPUT_DDR (1 << 9)
189	#define PAD_CTL_HYS (1 << 8)	189	#define PAD_CTL_HYS (1 << 8)
190		190
191	#define PAD_CTL_PKE (1 << 7)	191	#define PAD_CTL_PKE (1 << 7)
192	#define PAD_CTL_PUE (1 << 6 \| PAD_CTL_PKE)	192	#define PAD_CTL_PUE (1 << 6 \| PAD_CTL_PKE)
193	#define PAD_CTL_PUS_100K_DOWN (0 << 4 \| PAD_CTL_PUE)	193	#define PAD_CTL_PUS_100K_DOWN (0 << 4 \| PAD_CTL_PUE)
194	#define PAD_CTL_PUS_47K_UP (1 << 4 \| PAD_CTL_PUE)	194	#define PAD_CTL_PUS_47K_UP (1 << 4 \| PAD_CTL_PUE)
195	#define PAD_CTL_PUS_100K_UP (2 << 4 \| PAD_CTL_PUE)	195	#define PAD_CTL_PUS_100K_UP (2 << 4 \| PAD_CTL_PUE)
196	#define PAD_CTL_PUS_22K_UP (3 << 4 \| PAD_CTL_PUE)	196	#define PAD_CTL_PUS_22K_UP (3 << 4 \| PAD_CTL_PUE)
197		197
198	#define PAD_CTL_ODE (1 << 3)	198	#define PAD_CTL_ODE (1 << 3)
199		199
200	#define PAD_CTL_DSE_LOW (0 << 1)	200	#define PAD_CTL_DSE_LOW (0 << 1)
201	#define PAD_CTL_DSE_MED (1 << 1)	201	#define PAD_CTL_DSE_MED (1 << 1)
202	#define PAD_CTL_DSE_HIGH (2 << 1)	202	#define PAD_CTL_DSE_HIGH (2 << 1)
203	#define PAD_CTL_DSE_MAX (3 << 1)	203	#define PAD_CTL_DSE_MAX (3 << 1)
204		204
205	#endif	205	#endif
206		206
207	#define PAD_CTL_SRE_SLOW (0 << 0)	207	#define PAD_CTL_SRE_SLOW (0 << 0)
208	#define PAD_CTL_SRE_FAST (1 << 0)	208	#define PAD_CTL_SRE_FAST (1 << 0)
209		209
210	#endif	210	#endif
211		211
212	#define IOMUX_CONFIG_SION 0x10	212	#define IOMUX_CONFIG_SION 0x10
213		213
214	#define GPIO_PIN_MASK 0x1f	214	#define GPIO_PIN_MASK 0x1f
215	#define GPIO_PORT_SHIFT 5	215	#define GPIO_PORT_SHIFT 5
216	#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)	216	#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
217	#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)	217	#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
218	#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)	218	#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
219	#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)	219	#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
220	#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)	220	#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
221	#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)	221	#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
222	#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)	222	#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
223		223
224	void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);	224	void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
225	void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,	225	void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
226	unsigned count);	226	unsigned count);
227	/*	227	/*
228	* Set bits for general purpose registers	228	* Set bits for general purpose registers
229	*/	229	*/
230	void imx_iomux_set_gpr_register(int group, int start_bit,	230	void imx_iomux_set_gpr_register(int group, int start_bit,
231	int num_bits, int value);	231	int num_bits, int value);
232	#ifdef CONFIG_IOMUX_SHARE_CONF_REG	232	#ifdef CONFIG_IOMUX_SHARE_CONF_REG
233	void imx_iomux_gpio_set_direction(unsigned int gpio,	233	void imx_iomux_gpio_set_direction(unsigned int gpio,
234	unsigned int direction);	234	unsigned int direction);
235	void imx_iomux_gpio_get_function(unsigned int gpio,	235	void imx_iomux_gpio_get_function(unsigned int gpio,
236	u32 *gpio_state);	236	u32 *gpio_state);
237	#endif	237	#endif
238		238
239	/* macros for declaring and using pinmux array */	239	/* macros for declaring and using pinmux array */
240	#if defined(CONFIG_MX6QDL)	240	#if defined(CONFIG_MX6QDL)
241	#define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x)	241	#define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x)
242	#define SETUP_IOMUX_PAD(def) \	242	#define SETUP_IOMUX_PAD(def) \
243	if (is_cpu_type(MXC_CPU_MX6Q) \|\| is_cpu_type(MXC_CPU_MX6D)) { \	243	if (is_cpu_type(MXC_CPU_MX6Q) \|\| is_cpu_type(MXC_CPU_MX6D)) { \
244	imx_iomux_v3_setup_pad(MX6Q_##def); \	244	imx_iomux_v3_setup_pad(MX6Q_##def); \
245	} else { \	245	} else { \
246	imx_iomux_v3_setup_pad(MX6DL_##def); \	246	imx_iomux_v3_setup_pad(MX6DL_##def); \
247	}	247	}
248	#define SETUP_IOMUX_PADS(x) \	248	#define SETUP_IOMUX_PADS(x) \
249	imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2)	249	imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2)
250	#elif defined(CONFIG_MX6Q) \|\| defined(CONFIG_MX6D)	250	#elif defined(CONFIG_MX6Q) \|\| defined(CONFIG_MX6D)
251	#define IOMUX_PADS(x) MX6Q_##x	251	#define IOMUX_PADS(x) MX6Q_##x
252	#define SETUP_IOMUX_PAD(def) \	252	#define SETUP_IOMUX_PAD(def) \
253	imx_iomux_v3_setup_pad(MX6Q_##def);	253	imx_iomux_v3_setup_pad(MX6Q_##def);
254	#define SETUP_IOMUX_PADS(x) \	254	#define SETUP_IOMUX_PADS(x) \
255	imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))	255	imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
256	#elif defined(CONFIG_MX6UL)	256	#elif defined(CONFIG_MX6UL) \|\| defined(CONFIG_MX6ULL)
257	#define IOMUX_PADS(x) MX6_##x	257	#define IOMUX_PADS(x) MX6_##x
258	#define SETUP_IOMUX_PAD(def) \	258	#define SETUP_IOMUX_PAD(def) \
259	imx_iomux_v3_setup_pad(MX6_##def);	259	imx_iomux_v3_setup_pad(MX6_##def);
260	#define SETUP_IOMUX_PADS(x) \	260	#define SETUP_IOMUX_PADS(x) \
261	imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))	261	imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
262	#else	262	#else
263	#define IOMUX_PADS(x) MX6DL_##x	263	#define IOMUX_PADS(x) MX6DL_##x
264	#define SETUP_IOMUX_PAD(def) \	264	#define SETUP_IOMUX_PAD(def) \
265	imx_iomux_v3_setup_pad(MX6DL_##def);	265	imx_iomux_v3_setup_pad(MX6DL_##def);
266	#define SETUP_IOMUX_PADS(x) \	266	#define SETUP_IOMUX_PADS(x) \
267	imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))	267	imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
268	#endif	268	#endif
269		269
270	#endif /* __MACH_IOMUX_V3_H__*/	270	#endif /* __MACH_IOMUX_V3_H__*/
271		271

1	/*	1	/*
2	* Freescale i.MX28/6SX/6UL/7D LCDIF Register Definitions	2	* Freescale i.MX28/6SX/6UL/7D LCDIF Register Definitions
3	*	3	*
4	* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>	4	* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5	* on behalf of DENX Software Engineering GmbH	5	* on behalf of DENX Software Engineering GmbH
6	*	6	*
7	* Based on code from LTIB:	7	* Based on code from LTIB:
8	* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.	8	* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
9	*	9	*
10	* SPDX-License-Identifier: GPL-2.0+	10	* SPDX-License-Identifier: GPL-2.0+
11	*/	11	*/
12		12
13	#ifndef __IMX_REGS_LCDIF_H__	13	#ifndef __IMX_REGS_LCDIF_H__
14	#define __IMX_REGS_LCDIF_H__	14	#define __IMX_REGS_LCDIF_H__
15		15
16	#ifndef __ASSEMBLY__	16	#ifndef __ASSEMBLY__
17	#include <asm/mach-imx/regs-common.h>	17	#include <asm/mach-imx/regs-common.h>
18		18
19	struct mxs_lcdif_regs {	19	struct mxs_lcdif_regs {
20	mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */	20	mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */
21	mxs_reg_32(hw_lcdif_ctrl1) /* 0x10 */	21	mxs_reg_32(hw_lcdif_ctrl1) /* 0x10 */
22	#if defined(CONFIG_MX28) \|\| defined(CONFIG_MX6SX) \|\| defined(CONFIG_MX6UL) \|\| \	22
23	defined(CONFIG_MX7) \|\| defined(CONFIG_MX6SL) \|\| defined(CONFIG_MX6SLL)	23	#if defined(CONFIG_MX28) \|\| defined(CONFIG_MX6SX) \|\| \
		24	defined(CONFIG_MX6SL) \|\| defined(CONFIG_MX6SLL) \|\| \
		25	defined(CONFIG_MX6UL) \|\| defined(CONFIG_MX6ULL) \|\| \
		26	defined(CONFIG_MX7)
24	mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */	27	mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */
25	#endif	28	#endif
26	mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */	29	mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */
27	mxs_reg_32(hw_lcdif_cur_buf) /* 0x30/0x40 */	30	mxs_reg_32(hw_lcdif_cur_buf) /* 0x30/0x40 */
28	mxs_reg_32(hw_lcdif_next_buf) /* 0x40/0x50 */	31	mxs_reg_32(hw_lcdif_next_buf) /* 0x40/0x50 */
29		32
30	#if defined(CONFIG_MX23)	33	#if defined(CONFIG_MX23)
31	uint32_t reserved1[4];	34	uint32_t reserved1[4];
32	#endif	35	#endif
33		36
34	mxs_reg_32(hw_lcdif_timing) /* 0x60 */	37	mxs_reg_32(hw_lcdif_timing) /* 0x60 */
35	mxs_reg_32(hw_lcdif_vdctrl0) /* 0x70 */	38	mxs_reg_32(hw_lcdif_vdctrl0) /* 0x70 */
36	mxs_reg_32(hw_lcdif_vdctrl1) /* 0x80 */	39	mxs_reg_32(hw_lcdif_vdctrl1) /* 0x80 */
37	mxs_reg_32(hw_lcdif_vdctrl2) /* 0x90 */	40	mxs_reg_32(hw_lcdif_vdctrl2) /* 0x90 */
38	mxs_reg_32(hw_lcdif_vdctrl3) /* 0xa0 */	41	mxs_reg_32(hw_lcdif_vdctrl3) /* 0xa0 */
39	mxs_reg_32(hw_lcdif_vdctrl4) /* 0xb0 */	42	mxs_reg_32(hw_lcdif_vdctrl4) /* 0xb0 */
40	mxs_reg_32(hw_lcdif_dvictrl0) /* 0xc0 */	43	mxs_reg_32(hw_lcdif_dvictrl0) /* 0xc0 */
41	mxs_reg_32(hw_lcdif_dvictrl1) /* 0xd0 */	44	mxs_reg_32(hw_lcdif_dvictrl1) /* 0xd0 */
42	mxs_reg_32(hw_lcdif_dvictrl2) /* 0xe0 */	45	mxs_reg_32(hw_lcdif_dvictrl2) /* 0xe0 */
43	mxs_reg_32(hw_lcdif_dvictrl3) /* 0xf0 */	46	mxs_reg_32(hw_lcdif_dvictrl3) /* 0xf0 */
44	mxs_reg_32(hw_lcdif_dvictrl4) /* 0x100 */	47	mxs_reg_32(hw_lcdif_dvictrl4) /* 0x100 */
45	mxs_reg_32(hw_lcdif_csc_coeffctrl0) /* 0x110 */	48	mxs_reg_32(hw_lcdif_csc_coeffctrl0) /* 0x110 */
46	mxs_reg_32(hw_lcdif_csc_coeffctrl1) /* 0x120 */	49	mxs_reg_32(hw_lcdif_csc_coeffctrl1) /* 0x120 */
47	mxs_reg_32(hw_lcdif_csc_coeffctrl2) /* 0x130 */	50	mxs_reg_32(hw_lcdif_csc_coeffctrl2) /* 0x130 */
48	mxs_reg_32(hw_lcdif_csc_coeffctrl3) /* 0x140 */	51	mxs_reg_32(hw_lcdif_csc_coeffctrl3) /* 0x140 */
49	mxs_reg_32(hw_lcdif_csc_coeffctrl4) /* 0x150 */	52	mxs_reg_32(hw_lcdif_csc_coeffctrl4) /* 0x150 */
50	mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */	53	mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */
51	mxs_reg_32(hw_lcdif_csc_limit) /* 0x170 */	54	mxs_reg_32(hw_lcdif_csc_limit) /* 0x170 */
52		55
53	#if defined(CONFIG_MX23)	56	#if defined(CONFIG_MX23)
54	uint32_t reserved2[12];	57	uint32_t reserved2[12];
55	#endif	58	#endif
56	mxs_reg_32(hw_lcdif_data) /* 0x1b0/0x180 */	59	mxs_reg_32(hw_lcdif_data) /* 0x1b0/0x180 */
57	mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x1c0/0x190 */	60	mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x1c0/0x190 */
58	#if defined(CONFIG_MX28) \|\| defined(CONFIG_MX6SX) \|\| defined(CONFIG_MX6UL) \|\| \	61	#if defined(CONFIG_MX28) \|\| defined(CONFIG_MX6SX) \|\| \
59	defined(CONFIG_MX7) \|\| defined(CONFIG_MX6SL) \|\| defined(CONFIG_MX6SLL)	62	defined(CONFIG_MX6SL) \|\| defined(CONFIG_MX6SLL) \|\| \
		63	defined(CONFIG_MX6UL) \|\| defined(CONFIG_MX6ULL) \|\| \
		64	defined(CONFIG_MX7)
60	mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */	65	mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
61	#endif	66	#endif
62	mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */	67	mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */
63	mxs_reg_32(hw_lcdif_version) /* 0x1e0/0x1c0 */	68	mxs_reg_32(hw_lcdif_version) /* 0x1e0/0x1c0 */
64	mxs_reg_32(hw_lcdif_debug0) /* 0x1f0/0x1d0 */	69	mxs_reg_32(hw_lcdif_debug0) /* 0x1f0/0x1d0 */
65	mxs_reg_32(hw_lcdif_debug1) /* 0x200/0x1e0 */	70	mxs_reg_32(hw_lcdif_debug1) /* 0x200/0x1e0 */
66	mxs_reg_32(hw_lcdif_debug2) /* 0x1f0 */	71	mxs_reg_32(hw_lcdif_debug2) /* 0x1f0 */
67	#if defined(CONFIG_MX6SX) \|\| defined(CONFIG_MX6UL) \|\| defined(CONFIG_MX7) \|\| \	72	#if defined(CONFIG_MX6SX) \|\| \
68	defined(CONFIG_MX6SL) \|\| defined(CONFIG_MX6SLL)	73	defined(CONFIG_MX6SL) \|\| defined(CONFIG_MX6SLL) \|\| \
		74	defined(CONFIG_MX6UL) \|\| defined(CONFIG_MX6ULL) \|\| \
		75	defined(CONFIG_MX7)
69	mxs_reg_32(hw_lcdif_thres)	76	mxs_reg_32(hw_lcdif_thres)
70	mxs_reg_32(hw_lcdif_as_ctrl)	77	mxs_reg_32(hw_lcdif_as_ctrl)
71	mxs_reg_32(hw_lcdif_as_buf)	78	mxs_reg_32(hw_lcdif_as_buf)
72	mxs_reg_32(hw_lcdif_as_next_buf)	79	mxs_reg_32(hw_lcdif_as_next_buf)
73	mxs_reg_32(hw_lcdif_as_clrkeylow)	80	mxs_reg_32(hw_lcdif_as_clrkeylow)
74	mxs_reg_32(hw_lcdif_as_clrkeyhigh)	81	mxs_reg_32(hw_lcdif_as_clrkeyhigh)
75	mxs_reg_32(hw_lcdif_as_sync_delay)	82	mxs_reg_32(hw_lcdif_as_sync_delay)
76	mxs_reg_32(hw_lcdif_as_debug3)	83	mxs_reg_32(hw_lcdif_as_debug3)
77	mxs_reg_32(hw_lcdif_as_debug4)	84	mxs_reg_32(hw_lcdif_as_debug4)
78	mxs_reg_32(hw_lcdif_as_debug5)	85	mxs_reg_32(hw_lcdif_as_debug5)
79	#endif	86	#endif
80	};	87	};
81	#endif	88	#endif
82		89
83	#define LCDIF_CTRL_SFTRST (1 << 31)	90	#define LCDIF_CTRL_SFTRST (1 << 31)
84	#define LCDIF_CTRL_CLKGATE (1 << 30)	91	#define LCDIF_CTRL_CLKGATE (1 << 30)
85	#define LCDIF_CTRL_YCBCR422_INPUT (1 << 29)	92	#define LCDIF_CTRL_YCBCR422_INPUT (1 << 29)
86	#define LCDIF_CTRL_READ_WRITEB (1 << 28)	93	#define LCDIF_CTRL_READ_WRITEB (1 << 28)
87	#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE (1 << 27)	94	#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE (1 << 27)
88	#define LCDIF_CTRL_DATA_SHIFT_DIR (1 << 26)	95	#define LCDIF_CTRL_DATA_SHIFT_DIR (1 << 26)
89	#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x1f << 21)	96	#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x1f << 21)
90	#define LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET 21	97	#define LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET 21
91	#define LCDIF_CTRL_DVI_MODE (1 << 20)	98	#define LCDIF_CTRL_DVI_MODE (1 << 20)
92	#define LCDIF_CTRL_BYPASS_COUNT (1 << 19)	99	#define LCDIF_CTRL_BYPASS_COUNT (1 << 19)
93	#define LCDIF_CTRL_VSYNC_MODE (1 << 18)	100	#define LCDIF_CTRL_VSYNC_MODE (1 << 18)
94	#define LCDIF_CTRL_DOTCLK_MODE (1 << 17)	101	#define LCDIF_CTRL_DOTCLK_MODE (1 << 17)
95	#define LCDIF_CTRL_DATA_SELECT (1 << 16)	102	#define LCDIF_CTRL_DATA_SELECT (1 << 16)
96	#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0x3 << 14)	103	#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0x3 << 14)
97	#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET 14	104	#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET 14
98	#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3 << 12)	105	#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3 << 12)
99	#define LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET 12	106	#define LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET 12
100	#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0x3 << 10)	107	#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0x3 << 10)
101	#define LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET 10	108	#define LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET 10
102	#define LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT (0 << 10)	109	#define LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT (0 << 10)
103	#define LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT (1 << 10)	110	#define LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT (1 << 10)
104	#define LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT (2 << 10)	111	#define LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT (2 << 10)
105	#define LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT (3 << 10)	112	#define LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT (3 << 10)
106	#define LCDIF_CTRL_WORD_LENGTH_MASK (0x3 << 8)	113	#define LCDIF_CTRL_WORD_LENGTH_MASK (0x3 << 8)
107	#define LCDIF_CTRL_WORD_LENGTH_OFFSET 8	114	#define LCDIF_CTRL_WORD_LENGTH_OFFSET 8
108	#define LCDIF_CTRL_WORD_LENGTH_16BIT (0 << 8)	115	#define LCDIF_CTRL_WORD_LENGTH_16BIT (0 << 8)
109	#define LCDIF_CTRL_WORD_LENGTH_8BIT (1 << 8)	116	#define LCDIF_CTRL_WORD_LENGTH_8BIT (1 << 8)
110	#define LCDIF_CTRL_WORD_LENGTH_18BIT (2 << 8)	117	#define LCDIF_CTRL_WORD_LENGTH_18BIT (2 << 8)
111	#define LCDIF_CTRL_WORD_LENGTH_24BIT (3 << 8)	118	#define LCDIF_CTRL_WORD_LENGTH_24BIT (3 << 8)
112	#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC (1 << 7)	119	#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC (1 << 7)
113	#define LCDIF_CTRL_LCDIF_MASTER (1 << 5)	120	#define LCDIF_CTRL_LCDIF_MASTER (1 << 5)
114	#define LCDIF_CTRL_DATA_FORMAT_16_BIT (1 << 3)	121	#define LCDIF_CTRL_DATA_FORMAT_16_BIT (1 << 3)
115	#define LCDIF_CTRL_DATA_FORMAT_18_BIT (1 << 2)	122	#define LCDIF_CTRL_DATA_FORMAT_18_BIT (1 << 2)
116	#define LCDIF_CTRL_DATA_FORMAT_24_BIT (1 << 1)	123	#define LCDIF_CTRL_DATA_FORMAT_24_BIT (1 << 1)
117	#define LCDIF_CTRL_RUN (1 << 0)	124	#define LCDIF_CTRL_RUN (1 << 0)
118		125
119	#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB (1 << 27)	126	#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB (1 << 27)
120	#define LCDIF_CTRL1_BM_ERROR_IRQ_EN (1 << 26)	127	#define LCDIF_CTRL1_BM_ERROR_IRQ_EN (1 << 26)
121	#define LCDIF_CTRL1_BM_ERROR_IRQ (1 << 25)	128	#define LCDIF_CTRL1_BM_ERROR_IRQ (1 << 25)
122	#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW (1 << 24)	129	#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW (1 << 24)
123	#define LCDIF_CTRL1_INTERLACE_FIELDS (1 << 23)	130	#define LCDIF_CTRL1_INTERLACE_FIELDS (1 << 23)
124	#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD (1 << 22)	131	#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD (1 << 22)
125	#define LCDIF_CTRL1_FIFO_CLEAR (1 << 21)	132	#define LCDIF_CTRL1_FIFO_CLEAR (1 << 21)
126	#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS (1 << 20)	133	#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS (1 << 20)
127	#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf << 16)	134	#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf << 16)
128	#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET 16	135	#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET 16
129	#define LCDIF_CTRL1_OVERFLOW_IRQ_EN (1 << 15)	136	#define LCDIF_CTRL1_OVERFLOW_IRQ_EN (1 << 15)
130	#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN (1 << 14)	137	#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN (1 << 14)
131	#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13)	138	#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13)
132	#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN (1 << 12)	139	#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN (1 << 12)
133	#define LCDIF_CTRL1_OVERFLOW_IRQ (1 << 11)	140	#define LCDIF_CTRL1_OVERFLOW_IRQ (1 << 11)
134	#define LCDIF_CTRL1_UNDERFLOW_IRQ (1 << 10)	141	#define LCDIF_CTRL1_UNDERFLOW_IRQ (1 << 10)
135	#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ (1 << 9)	142	#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ (1 << 9)
136	#define LCDIF_CTRL1_VSYNC_EDGE_IRQ (1 << 8)	143	#define LCDIF_CTRL1_VSYNC_EDGE_IRQ (1 << 8)
137	#define LCDIF_CTRL1_BUSY_ENABLE (1 << 2)	144	#define LCDIF_CTRL1_BUSY_ENABLE (1 << 2)
138	#define LCDIF_CTRL1_MODE86 (1 << 1)	145	#define LCDIF_CTRL1_MODE86 (1 << 1)
139	#define LCDIF_CTRL1_RESET (1 << 0)	146	#define LCDIF_CTRL1_RESET (1 << 0)
140		147
141	#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0x7 << 21)	148	#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0x7 << 21)
142	#define LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET 21	149	#define LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET 21
143	#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1 (0x0 << 21)	150	#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1 (0x0 << 21)
144	#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2 (0x1 << 21)	151	#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2 (0x1 << 21)
145	#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4 (0x2 << 21)	152	#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4 (0x2 << 21)
146	#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8 (0x3 << 21)	153	#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8 (0x3 << 21)
147	#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16 (0x4 << 21)	154	#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16 (0x4 << 21)
148	#define LCDIF_CTRL2_BURST_LEN_8 (1 << 20)	155	#define LCDIF_CTRL2_BURST_LEN_8 (1 << 20)
149	#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x7 << 16)	156	#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x7 << 16)
150	#define LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET 16	157	#define LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET 16
151	#define LCDIF_CTRL2_ODD_LINE_PATTERN_RGB (0x0 << 16)	158	#define LCDIF_CTRL2_ODD_LINE_PATTERN_RGB (0x0 << 16)
152	#define LCDIF_CTRL2_ODD_LINE_PATTERN_RBG (0x1 << 16)	159	#define LCDIF_CTRL2_ODD_LINE_PATTERN_RBG (0x1 << 16)
153	#define LCDIF_CTRL2_ODD_LINE_PATTERN_GBR (0x2 << 16)	160	#define LCDIF_CTRL2_ODD_LINE_PATTERN_GBR (0x2 << 16)
154	#define LCDIF_CTRL2_ODD_LINE_PATTERN_GRB (0x3 << 16)	161	#define LCDIF_CTRL2_ODD_LINE_PATTERN_GRB (0x3 << 16)
155	#define LCDIF_CTRL2_ODD_LINE_PATTERN_BRG (0x4 << 16)	162	#define LCDIF_CTRL2_ODD_LINE_PATTERN_BRG (0x4 << 16)
156	#define LCDIF_CTRL2_ODD_LINE_PATTERN_BGR (0x5 << 16)	163	#define LCDIF_CTRL2_ODD_LINE_PATTERN_BGR (0x5 << 16)
157	#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7 << 12)	164	#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7 << 12)
158	#define LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET 12	165	#define LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET 12
159	#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB (0x0 << 12)	166	#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB (0x0 << 12)
160	#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG (0x1 << 12)	167	#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG (0x1 << 12)
161	#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR (0x2 << 12)	168	#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR (0x2 << 12)
162	#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB (0x3 << 12)	169	#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB (0x3 << 12)
163	#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG (0x4 << 12)	170	#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG (0x4 << 12)
164	#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR (0x5 << 12)	171	#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR (0x5 << 12)
165	#define LCDIF_CTRL2_READ_PACK_DIR (1 << 10)	172	#define LCDIF_CTRL2_READ_PACK_DIR (1 << 10)
166	#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT (1 << 9)	173	#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT (1 << 9)
167	#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT (1 << 8)	174	#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT (1 << 8)
168	#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x7 << 4)	175	#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x7 << 4)
169	#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET 4	176	#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET 4
170	#define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0x7 << 1)	177	#define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0x7 << 1)
171	#define LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET 1	178	#define LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET 1
172		179
173	#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff << 16)	180	#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff << 16)
174	#define LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET 16	181	#define LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET 16
175	#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffff << 0)	182	#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffff << 0)
176	#define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET 0	183	#define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET 0
177		184
178	#define LCDIF_CUR_BUF_ADDR_MASK 0xffffffff	185	#define LCDIF_CUR_BUF_ADDR_MASK 0xffffffff
179	#define LCDIF_CUR_BUF_ADDR_OFFSET 0	186	#define LCDIF_CUR_BUF_ADDR_OFFSET 0
180		187
181	#define LCDIF_NEXT_BUF_ADDR_MASK 0xffffffff	188	#define LCDIF_NEXT_BUF_ADDR_MASK 0xffffffff
182	#define LCDIF_NEXT_BUF_ADDR_OFFSET 0	189	#define LCDIF_NEXT_BUF_ADDR_OFFSET 0
183		190
184	#define LCDIF_TIMING_CMD_HOLD_MASK (0xff << 24)	191	#define LCDIF_TIMING_CMD_HOLD_MASK (0xff << 24)
185	#define LCDIF_TIMING_CMD_HOLD_OFFSET 24	192	#define LCDIF_TIMING_CMD_HOLD_OFFSET 24
186	#define LCDIF_TIMING_CMD_SETUP_MASK (0xff << 16)	193	#define LCDIF_TIMING_CMD_SETUP_MASK (0xff << 16)
187	#define LCDIF_TIMING_CMD_SETUP_OFFSET 16	194	#define LCDIF_TIMING_CMD_SETUP_OFFSET 16
188	#define LCDIF_TIMING_DATA_HOLD_MASK (0xff << 8)	195	#define LCDIF_TIMING_DATA_HOLD_MASK (0xff << 8)
189	#define LCDIF_TIMING_DATA_HOLD_OFFSET 8	196	#define LCDIF_TIMING_DATA_HOLD_OFFSET 8
190	#define LCDIF_TIMING_DATA_SETUP_MASK (0xff << 0)	197	#define LCDIF_TIMING_DATA_SETUP_MASK (0xff << 0)
191	#define LCDIF_TIMING_DATA_SETUP_OFFSET 0	198	#define LCDIF_TIMING_DATA_SETUP_OFFSET 0
192		199
193	#define LCDIF_VDCTRL0_VSYNC_OEB (1 << 29)	200	#define LCDIF_VDCTRL0_VSYNC_OEB (1 << 29)
194	#define LCDIF_VDCTRL0_ENABLE_PRESENT (1 << 28)	201	#define LCDIF_VDCTRL0_ENABLE_PRESENT (1 << 28)
195	#define LCDIF_VDCTRL0_VSYNC_POL (1 << 27)	202	#define LCDIF_VDCTRL0_VSYNC_POL (1 << 27)
196	#define LCDIF_VDCTRL0_HSYNC_POL (1 << 26)	203	#define LCDIF_VDCTRL0_HSYNC_POL (1 << 26)
197	#define LCDIF_VDCTRL0_DOTCLK_POL (1 << 25)	204	#define LCDIF_VDCTRL0_DOTCLK_POL (1 << 25)
198	#define LCDIF_VDCTRL0_ENABLE_POL (1 << 24)	205	#define LCDIF_VDCTRL0_ENABLE_POL (1 << 24)
199	#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21)	206	#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21)
200	#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20)	207	#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20)
201	#define LCDIF_VDCTRL0_HALF_LINE (1 << 19)	208	#define LCDIF_VDCTRL0_HALF_LINE (1 << 19)
202	#define LCDIF_VDCTRL0_HALF_LINE_MODE (1 << 18)	209	#define LCDIF_VDCTRL0_HALF_LINE_MODE (1 << 18)
203	#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3ffff	210	#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3ffff
204	#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET 0	211	#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET 0
205		212
206	#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff	213	#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff
207	#define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0	214	#define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0
208		215
209	#if defined(CONFIG_MX23)	216	#if defined(CONFIG_MX23)
210	#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xff << 24)	217	#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xff << 24)
211	#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 24	218	#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 24
212	#else	219	#else
213	#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18)	220	#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18)
214	#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18	221	#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18
215	#endif	222	#endif
216	#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff	223	#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff
217	#define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0	224	#define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0
218		225
219	#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS (1 << 29)	226	#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS (1 << 29)
220	#define LCDIF_VDCTRL3_VSYNC_ONLY (1 << 28)	227	#define LCDIF_VDCTRL3_VSYNC_ONLY (1 << 28)
221	#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff << 16)	228	#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff << 16)
222	#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET 16	229	#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET 16
223	#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffff << 0)	230	#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffff << 0)
224	#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET 0	231	#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET 0
225		232
226	#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0x7 << 29)	233	#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0x7 << 29)
227	#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET 29	234	#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET 29
228	#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON (1 << 18)	235	#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON (1 << 18)
229	#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff	236	#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff
230	#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0	237	#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0
231		238
232	#endif /* __IMX_REGS_LCDIF_H__ */	239	#endif /* __IMX_REGS_LCDIF_H__ */
233		240

1	/*	1	/*
2	* Copyright (C) 2014 Gateworks Corporation	2	* Copyright (C) 2014 Gateworks Corporation
3	* Author: Tim Harvey <tharvey@gateworks.com>	3	* Author: Tim Harvey <tharvey@gateworks.com>
4	*	4	*
5	* SPDX-License-Identifier: GPL-2.0+	5	* SPDX-License-Identifier: GPL-2.0+
6	*/	6	*/
7		7
8	#include <common.h>	8	#include <common.h>
9	#include <linux/types.h>	9	#include <linux/types.h>
10	#include <asm/arch/clock.h>	10	#include <asm/arch/clock.h>
11	#include <asm/arch/mx6-ddr.h>	11	#include <asm/arch/mx6-ddr.h>
12	#include <asm/arch/sys_proto.h>	12	#include <asm/arch/sys_proto.h>
13	#include <asm/io.h>	13	#include <asm/io.h>
14	#include <asm/types.h>	14	#include <asm/types.h>
15	#include <wait_bit.h>	15	#include <wait_bit.h>
16		16
17	#if defined(CONFIG_MX6_DDRCAL)	17	#if defined(CONFIG_MX6_DDRCAL)
18	static void reset_read_data_fifos(void)	18	static void reset_read_data_fifos(void)
19	{	19	{
20	struct mmdc_p_regs mmdc0 = (struct mmdc_p_regs )MMDC_P0_BASE_ADDR;	20	struct mmdc_p_regs mmdc0 = (struct mmdc_p_regs )MMDC_P0_BASE_ADDR;
21		21
22	/* Reset data FIFOs twice. */	22	/* Reset data FIFOs twice. */
23	setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);	23	setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
24	wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);	24	wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
25		25
26	setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);	26	setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
27	wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);	27	wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
28	}	28	}
29		29
30	static void precharge_all(const bool cs0_enable, const bool cs1_enable)	30	static void precharge_all(const bool cs0_enable, const bool cs1_enable)
31	{	31	{
32	struct mmdc_p_regs mmdc0 = (struct mmdc_p_regs )MMDC_P0_BASE_ADDR;	32	struct mmdc_p_regs mmdc0 = (struct mmdc_p_regs )MMDC_P0_BASE_ADDR;
33		33
34	/*	34	/*
35	* Issue the Precharge-All command to the DDR device for both	35	* Issue the Precharge-All command to the DDR device for both
36	* chip selects. Note, CON_REQ bit should also remain set. If	36	* chip selects. Note, CON_REQ bit should also remain set. If
37	* only using one chip select, then precharge only the desired	37	* only using one chip select, then precharge only the desired
38	* chip select.	38	* chip select.
39	*/	39	*/
40	if (cs0_enable) { /* CS0 */	40	if (cs0_enable) { /* CS0 */