Commit 292b88d4d031332433c5f18d9a219b278cefdfaa

Authored by Ji Luo
1 parent 3833ec0d15

MA-17226 Invalidate the dcache after DMA operation

The main memory contents can spontaneously come to the cache due to
the speculative memory access by the CPU, this may cause coherency
problem if this happens during the DMA operaion is on-going.

Invalidate the dcache range after DMA opeartion but before the main
memory read to avoid coherency problem.

Test: reboot test.

Change-Id: I93824deab9285b5478669e0a311e0b338bf02f8a
Signed-off-by: Ji Luo <ji.luo@nxp.com>

Showing 1 changed file with 21 additions and 0 deletions Side-by-side Diff

lib/trusty/ql-tipc/hwcrypto.c
... ... @@ -186,6 +186,12 @@
186 186  
187 187 int rc = hwcrypto_do_tipc(HWCRYPTO_HASH, (void*)&req,
188 188 sizeof(req), NULL, 0, false);
  189 +
  190 + /* invalidate the dcache again before read to avoid coherency
  191 + * problem caused by speculative memory access by the CPU.
  192 + */
  193 + invalidate_dcache_range(start, end);
  194 +
189 195 return rc;
190 196 }
191 197  
... ... @@ -216,6 +222,11 @@
216 222  
217 223 int rc = hwcrypto_do_tipc(HWCRYPTO_ENCAP_BLOB, (void*)&req,
218 224 sizeof(req), NULL, 0, false);
  225 +
  226 + /* invalidate the dcache again before read to avoid coherency
  227 + * problem caused by speculative memory access by the CPU.
  228 + */
  229 + invalidate_dcache_range(start, end);
219 230 return rc;
220 231 }
221 232  
... ... @@ -238,6 +249,11 @@
238 249  
239 250 int rc = hwcrypto_do_tipc(HWCRYPTO_GEN_RNG, (void*)&req,
240 251 sizeof(req), NULL, 0, false);
  252 +
  253 + /* invalidate the dcache again before read to avoid coherency
  254 + * problem caused by speculative memory access by the CPU.
  255 + */
  256 + invalidate_dcache_range(start, end);
241 257 return rc;
242 258 }
243 259  
... ... @@ -260,6 +276,11 @@
260 276  
261 277 int rc = hwcrypto_do_tipc(HWCRYPTO_GEN_BKEK, (void*)&req,
262 278 sizeof(req), NULL, 0, false);
  279 +
  280 + /* invalidate the dcache again before read to avoid coherency
  281 + * problem caused by speculative memory access by the CPU.
  282 + */
  283 + invalidate_dcache_range(start, end);
263 284 return rc;
264 285 }
265 286