mx28evk: Add initial support for MX28EVK board

Add initial support for Freescale MX28EVK board. Tested boot via SD card and by loading a kernel via TFTP through the FEC interface. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>

mx28evk: Add initial support for MX28EVK board
Add initial support for Freescale MX28EVK board. Tested boot via SD card and by loading a kernel via TFTP through the FEC interface. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
Fabio Estevam · Albert ARIBAUD
1 parent 5bcc6a8901
Showing 7 changed files with 548 additions and 0 deletions Side-by-side Diff
MAINTAINERS
board/freescale/mx28evk/Makefile
board/freescale/mx28evk/iomux.c
board/freescale/mx28evk/mx28evk.c
board/freescale/mx28evk/u-boot.bd
boards.cfg
include/configs/mx28evk.h
@@ -642,6 +642,7 @@
 Fabio Estevam <fabio.estevam@freescale.com>
  
 	mx25pdk		i.MX25
+	mx28evk		i.MX28
 	mx31pdk		i.MX31
 	mx53ard		i.MX53
 	mx53smd		i.MX53
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+ifndef	CONFIG_SPL_BUILD
+COBJS	:= mx28evk.o
+else
+COBJS	:= iomux.o
+endif
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+all:	$(ALL)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+/*
+ * Freescale MX28EVK IOMUX setup
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define	MUX_CONFIG_SSP0	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_ENET	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
+
+const iomux_cfg_t iomux_setup[] = {
+	/* DUART */
+	MX28_PAD_PWM0__DUART_RX,
+	MX28_PAD_PWM1__DUART_TX,
+
+	/* MMC0 */
+	MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
+		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+	MX28_PAD_SSP0_SCK__SSP0_SCK |
+		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+	/* write protect */
+	MX28_PAD_SSP1_SCK__GPIO_2_12,
+	/* MMC0 slot power enable */
+	MX28_PAD_PWM3__GPIO_3_28 |
+		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+
+	/* FEC0 */
+	MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
+	/* FEC0 Enable */
+	MX28_PAD_SSP1_DATA3__GPIO_2_15 |
+		(MXS_PAD_12MA | MXS_PAD_3V3),
+	/* FEC0 Reset */
+	MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
+		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+
+	/* FEC1 */
+	MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
+
+	/* EMI */
+	MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
+
+	MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+};
+
+void board_init_ll(void)
+{
+	mx28_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
+}
+/*
+ * Freescale MX28EVK board
+ *
+ * (C) Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * Based on m28evk.c:
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/mii.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Functions
+ */
+int board_early_init_f(void)
+{
+	/* IO0 clock at 480MHz */
+	mx28_set_ioclk(MXC_IOCLK0, 480000);
+	/* IO1 clock at 480MHz */
+	mx28_set_ioclk(MXC_IOCLK1, 480000);
+
+	/* SSP0 clock at 96MHz */
+	mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
+	/* SSP2 clock at 96MHz */
+	mx28_set_sspclk(MXC_SSPCLK2, 96000, 0);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	return mx28_dram_init();
+}
+
+int board_init(void)
+{
+	/* Adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+#ifdef	CONFIG_CMD_MMC
+static int mx28evk_mmc_wp(int id)
+{
+	if (id != 0) {
+		printf("MXS MMC: Invalid card selected (card id = %d)\n", id);
+		return 1;
+	}
+
+	return gpio_get_value(MX28_PAD_SSP1_SCK__GPIO_2_12);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	/* Configure WP as input */
+	gpio_direction_input(MX28_PAD_SSP1_SCK__GPIO_2_12);
+
+	/* Configure MMC0 Power Enable */
+	gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
+
+	return mxsmmc_initialize(bis, 0, mx28evk_mmc_wp);
+}
+#endif
+
+#ifdef	CONFIG_CMD_NET
+
+#define	MII_OPMODE_STRAP_OVERRIDE	0x16
+#define	MII_PHY_CTRL1			0x1e
+#define	MII_PHY_CTRL2			0x1f
+
+int fecmxc_mii_postcall(int phy)
+{
+	miiphy_write("FEC1", phy, MII_BMCR, 0x9000);
+	miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202);
+	if (phy == 3)
+		miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8180);
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	struct mx28_clkctrl_regs *clkctrl_regs =
+		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	struct eth_device *dev;
+	int ret;
+
+	ret = cpu_eth_init(bis);
+
+	/* MX28EVK uses ENET_CLK PAD to drive FEC clock */
+	writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN,
+					&clkctrl_regs->hw_clkctrl_enet);
+
+	/* Power-on FECs */
+	gpio_direction_output(MX28_PAD_SSP1_DATA3__GPIO_2_15, 0);
+
+	/* Reset FEC PHYs */
+	gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
+	udelay(200);
+	gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
+
+	ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
+	if (ret) {
+		puts("FEC MXS: Unable to init FEC0\n");
+		return ret;
+	}
+
+	ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE);
+	if (ret) {
+		puts("FEC MXS: Unable to init FEC1\n");
+		return ret;
+	}
+
+	dev = eth_get_dev_by_name("FEC0");
+	if (!dev) {
+		puts("FEC MXS: Unable to get FEC0 device entry\n");
+		return -EINVAL;
+	}
+
+	ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
+	if (ret) {
+		puts("FEC MXS: Unable to register FEC0 mii postcall\n");
+		return ret;
+	}
+
+	dev = eth_get_dev_by_name("FEC1");
+	if (!dev) {
+		puts("FEC MXS: Unable to get FEC1 device entry\n");
+		return -EINVAL;
+	}
+
+	ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
+	if (ret) {
+		puts("FEC MXS: Unable to register FEC1 mii postcall\n");
+		return ret;
+	}
+
+	return ret;
+}
+
+#endif
+sources {
+	u_boot_spl="spl/u-boot-spl.bin";
+	u_boot="u-boot.bin";
+}
+
+section (0) {
+	load u_boot_spl > 0x0000;
+	load ivt (entry = 0x0014) > 0x8000;
+	hab call 0x8000;
+
+	load u_boot > 0x40000100;
+	load ivt (entry = 0x40000100) > 0x8000;
+	hab call 0x8000;
+}
@@ -160,6 +160,7 @@
 imx27lite                    arm         arm926ejs   imx27lite           logicpd        mx27
 magnesium                    arm         arm926ejs   imx27lite           logicpd        mx27
 m28evk                       arm         arm926ejs   -                   denx           mx28
+mx28evk                      arm         arm926ejs   -                   freescale      mx28
 nhk8815                      arm         arm926ejs   nhk8815             st             nomadik
 nhk8815_onenand              arm         arm926ejs   nhk8815             st             nomadik       nhk8815:BOOT_ONENAND
 omap1610h2		     arm	 arm926ejs   omap1610inn	 ti		omap	    omap1610inn:CS3_BOOT
+/*
+ * (C) Copyright 2011 Freescale Semiconductor, Inc.
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * Based on m28evk.h:
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/regs-base.h>
+
+/*
+ * SoC configurations
+ */
+#define CONFIG_MX28				/* i.MX28 SoC */
+#define CONFIG_MXS_GPIO			/* GPIO control */
+#define CONFIG_SYS_HZ		1000		/* Ticks per second */
+
+#define CONFIG_MACH_TYPE	MACH_TYPE_MX28EVK
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_ARCH_MISC_INIT
+
+/*
+ * SPL
+ */
+#define CONFIG_SPL
+#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
+#define CONFIG_SPL_START_S_PATH	"arch/arm/cpu/arm926ejs/mx28"
+#define CONFIG_SPL_LDSCRIPT	"arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+
+/*
+ * U-Boot Commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+
+/*
+ * Memory configurations
+ */
+#define CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
+#define PHYS_SDRAM_1			0x40000000	/* Base address */
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* Max 1 GB RAM */
+#define CONFIG_STACKSIZE		(128 * 1024)	/* 128 KB stack */
+#define CONFIG_SYS_MALLOC_LEN		0x00400000	/* 4 MB for malloc */
+#define CONFIG_SYS_MEMTEST_START	0x40000000	/* Memtest start adr */
+#define CONFIG_SYS_MEMTEST_END		0x40400000	/* 4 MB RAM test */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+/* Point initial SP in SRAM so SPL can use it too. */
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0x00002000
+#define CONFIG_SYS_INIT_RAM_SIZE	(128 * 1024)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/*
+ * We need to sacrifice first 4 bytes of RAM here to avoid triggering some
+ * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
+ * binary. In case there was more of this mess, 0x100 bytes are skipped.
+ */
+#define CONFIG_SYS_TEXT_BASE	0x40000100
+
+#define CONFIG_ENV_OVERWRITE
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT	"MX28EVK U-Boot > "
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
+#define CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+						/* Print buffer size */
+#define CONFIG_SYS_MAXARGS	32		/* Max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+						/* Boot argument buffer size */
+#define CONFIG_VERSION_VARIABLE	/* U-BOOT version */
+#define CONFIG_AUTO_COMPLETE		/* Command auto complete */
+#define CONFIG_CMDLINE_EDITING		/* Command history etc */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+/*
+ * Serial Driver
+ */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK		24000000
+#define CONFIG_PL01x_PORTS		{ (void *)MXS_UARTDBG_BASE }
+#define CONFIG_CONS_INDEX		0
+#define CONFIG_BAUDRATE			115200	/* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * MMC Driver
+ */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET	(256 * 1024)
+#define CONFIG_ENV_SIZE	(16 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_CMD_SAVEENV
+#ifdef	CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MXS_MMC
+#endif
+
+/*
+ * Ethernet on SOC (FEC)
+ */
+#ifdef	CONFIG_CMD_NET
+#define CONFIG_NET_MULTI
+#define CONFIG_ETHPRIME	"FEC0"
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_MULTI
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+#define CONFIG_FEC_XCV_TYPE	RMII
+#define CONFIG_MX28_FEC_MAC_IN_OCOTP
+#endif
+
+/*
+ * Boot Linux
+ */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTFILE	"uImage"
+#define CONFIG_BOOTCOMMAND	"run bootcmd_net"
+#define CONFIG_LOADADDR	0x42000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/*
+ * Extra Environments
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"console_fsl=console=ttyAM0" \
+	"console_mainline=console=ttyAMA0" \
+	"netargs=setenv bootargs console=${console_mainline}" \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot}\0" \
+	"bootcmd_net=echo Booting from net ...; " \
+		"run netargs; " \
+		"dhcp ${uimage}; bootm\0" \
+
+#endif /* __CONFIG_H */
...	...	@@ -642,6 +642,7 @@
642	642	Fabio Estevam <fabio.estevam@freescale.com>
643	643
644	644	mx25pdk i.MX25
	645	+ mx28evk i.MX28
645	646	mx31pdk i.MX31
646	647	mx53ard i.MX53
647	648	mx53smd i.MX53
	1	+#
	2	+# (C) Copyright 2000-2006
	3	+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+#
	5	+# See file CREDITS for list of people who contributed to this
	6	+# project.
	7	+#
	8	+# This program is free software; you can redistribute it and/or
	9	+# modify it under the terms of the GNU General Public License as
	10	+# published by the Free Software Foundation; either version 2 of
	11	+# the License, or (at your option) any later version.
	12	+#
	13	+# This program is distributed in the hope that it will be useful,
	14	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+# GNU General Public License for more details.
	17	+#
	18	+# You should have received a copy of the GNU General Public License
	19	+# along with this program; if not, write to the Free Software
	20	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+# MA 02111-1307 USA
	22	+#
	23	+
	24	+include $(TOPDIR)/config.mk
	25	+
	26	+LIB = $(obj)lib$(BOARD).o
	27	+
	28	+ifndef CONFIG_SPL_BUILD
	29	+COBJS := mx28evk.o
	30	+else
	31	+COBJS := iomux.o
	32	+endif
	33	+
	34	+SRCS := $(COBJS:.o=.c)
	35	+OBJS := $(addprefix $(obj),$(COBJS))
	36	+
	37	+$(LIB): $(obj).depend $(OBJS)
	38	+ $(call cmd_link_o_target, $(OBJS))
	39	+
	40	+all: $(ALL)
	41	+
	42	+#########################################################################
	43	+
	44	+# defines $(obj).depend target
	45	+include $(SRCTREE)/rules.mk
	46	+
	47	+sinclude $(obj).depend
	48	+
	49	+#########################################################################
	1	+/*
	2	+ * Freescale MX28EVK IOMUX setup
	3	+ *
	4	+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
	5	+ * on behalf of DENX Software Engineering GmbH
	6	+ *
	7	+ * See file CREDITS for list of people who contributed to this
	8	+ * project.
	9	+ *
	10	+ * This program is free software; you can redistribute it and/or
	11	+ * modify it under the terms of the GNU General Public License as
	12	+ * published by the Free Software Foundation; either version 2 of
	13	+ * the License, or (at your option) any later version.
	14	+ *
	15	+ * This program is distributed in the hope that it will be useful,
	16	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	+ * GNU General Public License for more details.
	19	+ */
	20	+
	21	+#include <common.h>
	22	+#include <config.h>
	23	+#include <asm/io.h>
	24	+#include <asm/arch/iomux-mx28.h>
	25	+#include <asm/arch/imx-regs.h>
	26	+#include <asm/arch/sys_proto.h>
	27	+
	28	+#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 \| MXS_PAD_8MA \| MXS_PAD_PULLUP)
	29	+#define MUX_CONFIG_ENET (MXS_PAD_3V3 \| MXS_PAD_8MA \| MXS_PAD_PULLUP)
	30	+#define MUX_CONFIG_EMI (MXS_PAD_3V3 \| MXS_PAD_12MA \| MXS_PAD_NOPULL)
	31	+
	32	+const iomux_cfg_t iomux_setup[] = {
	33	+ /* DUART */
	34	+ MX28_PAD_PWM0__DUART_RX,
	35	+ MX28_PAD_PWM1__DUART_TX,
	36	+
	37	+ /* MMC0 */
	38	+ MX28_PAD_SSP0_DATA0__SSP0_D0 \| MUX_CONFIG_SSP0,
	39	+ MX28_PAD_SSP0_DATA1__SSP0_D1 \| MUX_CONFIG_SSP0,
	40	+ MX28_PAD_SSP0_DATA2__SSP0_D2 \| MUX_CONFIG_SSP0,
	41	+ MX28_PAD_SSP0_DATA3__SSP0_D3 \| MUX_CONFIG_SSP0,
	42	+ MX28_PAD_SSP0_DATA4__SSP0_D4 \| MUX_CONFIG_SSP0,
	43	+ MX28_PAD_SSP0_DATA5__SSP0_D5 \| MUX_CONFIG_SSP0,
	44	+ MX28_PAD_SSP0_DATA6__SSP0_D6 \| MUX_CONFIG_SSP0,
	45	+ MX28_PAD_SSP0_DATA7__SSP0_D7 \| MUX_CONFIG_SSP0,
	46	+ MX28_PAD_SSP0_CMD__SSP0_CMD \| MUX_CONFIG_SSP0,
	47	+ MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT \|
	48	+ (MXS_PAD_8MA \| MXS_PAD_3V3 \| MXS_PAD_NOPULL),
	49	+ MX28_PAD_SSP0_SCK__SSP0_SCK \|
	50	+ (MXS_PAD_12MA \| MXS_PAD_3V3 \| MXS_PAD_NOPULL),
	51	+ /* write protect */
	52	+ MX28_PAD_SSP1_SCK__GPIO_2_12,
	53	+ /* MMC0 slot power enable */
	54	+ MX28_PAD_PWM3__GPIO_3_28 \|
	55	+ (MXS_PAD_12MA \| MXS_PAD_3V3 \| MXS_PAD_PULLUP),
	56	+
	57	+ /* FEC0 */
	58	+ MX28_PAD_ENET0_MDC__ENET0_MDC \| MUX_CONFIG_ENET,
	59	+ MX28_PAD_ENET0_MDIO__ENET0_MDIO \| MUX_CONFIG_ENET,
	60	+ MX28_PAD_ENET0_RX_EN__ENET0_RX_EN \| MUX_CONFIG_ENET,
	61	+ MX28_PAD_ENET0_TX_EN__ENET0_TX_EN \| MUX_CONFIG_ENET,
	62	+ MX28_PAD_ENET0_RXD0__ENET0_RXD0 \| MUX_CONFIG_ENET,
	63	+ MX28_PAD_ENET0_RXD1__ENET0_RXD1 \| MUX_CONFIG_ENET,
	64	+ MX28_PAD_ENET0_TXD0__ENET0_TXD0 \| MUX_CONFIG_ENET,
	65	+ MX28_PAD_ENET0_TXD1__ENET0_TXD1 \| MUX_CONFIG_ENET,
	66	+ MX28_PAD_ENET_CLK__CLKCTRL_ENET \| MUX_CONFIG_ENET,
	67	+ /* FEC0 Enable */
	68	+ MX28_PAD_SSP1_DATA3__GPIO_2_15 \|
	69	+ (MXS_PAD_12MA \| MXS_PAD_3V3),
	70	+ /* FEC0 Reset */
	71	+ MX28_PAD_ENET0_RX_CLK__GPIO_4_13 \|
	72	+ (MXS_PAD_12MA \| MXS_PAD_3V3 \| MXS_PAD_PULLUP),
	73	+
	74	+ /* FEC1 */
	75	+ MX28_PAD_ENET0_COL__ENET1_TX_EN \| MUX_CONFIG_ENET,
	76	+ MX28_PAD_ENET0_CRS__ENET1_RX_EN \| MUX_CONFIG_ENET,
	77	+ MX28_PAD_ENET0_RXD2__ENET1_RXD0 \| MUX_CONFIG_ENET,
	78	+ MX28_PAD_ENET0_RXD3__ENET1_RXD1 \| MUX_CONFIG_ENET,
	79	+ MX28_PAD_ENET0_TXD2__ENET1_TXD0 \| MUX_CONFIG_ENET,
	80	+ MX28_PAD_ENET0_TXD3__ENET1_TXD1 \| MUX_CONFIG_ENET,
	81	+
	82	+ /* EMI */
	83	+ MX28_PAD_EMI_D00__EMI_DATA0 \| MUX_CONFIG_EMI,
	84	+ MX28_PAD_EMI_D01__EMI_DATA1 \| MUX_CONFIG_EMI,
	85	+ MX28_PAD_EMI_D02__EMI_DATA2 \| MUX_CONFIG_EMI,
	86	+ MX28_PAD_EMI_D03__EMI_DATA3 \| MUX_CONFIG_EMI,
	87	+ MX28_PAD_EMI_D04__EMI_DATA4 \| MUX_CONFIG_EMI,
	88	+ MX28_PAD_EMI_D05__EMI_DATA5 \| MUX_CONFIG_EMI,
	89	+ MX28_PAD_EMI_D06__EMI_DATA6 \| MUX_CONFIG_EMI,
	90	+ MX28_PAD_EMI_D07__EMI_DATA7 \| MUX_CONFIG_EMI,
	91	+ MX28_PAD_EMI_D08__EMI_DATA8 \| MUX_CONFIG_EMI,
	92	+ MX28_PAD_EMI_D09__EMI_DATA9 \| MUX_CONFIG_EMI,
	93	+ MX28_PAD_EMI_D10__EMI_DATA10 \| MUX_CONFIG_EMI,
	94	+ MX28_PAD_EMI_D11__EMI_DATA11 \| MUX_CONFIG_EMI,
	95	+ MX28_PAD_EMI_D12__EMI_DATA12 \| MUX_CONFIG_EMI,
	96	+ MX28_PAD_EMI_D13__EMI_DATA13 \| MUX_CONFIG_EMI,
	97	+ MX28_PAD_EMI_D14__EMI_DATA14 \| MUX_CONFIG_EMI,
	98	+ MX28_PAD_EMI_D15__EMI_DATA15 \| MUX_CONFIG_EMI,
	99	+ MX28_PAD_EMI_ODT0__EMI_ODT0 \| MUX_CONFIG_EMI,
	100	+ MX28_PAD_EMI_DQM0__EMI_DQM0 \| MUX_CONFIG_EMI,
	101	+ MX28_PAD_EMI_ODT1__EMI_ODT1 \| MUX_CONFIG_EMI,
	102	+ MX28_PAD_EMI_DQM1__EMI_DQM1 \| MUX_CONFIG_EMI,
	103	+ MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK \| MUX_CONFIG_EMI,
	104	+ MX28_PAD_EMI_CLK__EMI_CLK \| MUX_CONFIG_EMI,
	105	+ MX28_PAD_EMI_DQS0__EMI_DQS0 \| MUX_CONFIG_EMI,
	106	+ MX28_PAD_EMI_DQS1__EMI_DQS1 \| MUX_CONFIG_EMI,
	107	+ MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN \| MUX_CONFIG_EMI,
	108	+
	109	+ MX28_PAD_EMI_A00__EMI_ADDR0 \| MUX_CONFIG_EMI,
	110	+ MX28_PAD_EMI_A01__EMI_ADDR1 \| MUX_CONFIG_EMI,
	111	+ MX28_PAD_EMI_A02__EMI_ADDR2 \| MUX_CONFIG_EMI,
	112	+ MX28_PAD_EMI_A03__EMI_ADDR3 \| MUX_CONFIG_EMI,
	113	+ MX28_PAD_EMI_A04__EMI_ADDR4 \| MUX_CONFIG_EMI,
	114	+ MX28_PAD_EMI_A05__EMI_ADDR5 \| MUX_CONFIG_EMI,
	115	+ MX28_PAD_EMI_A06__EMI_ADDR6 \| MUX_CONFIG_EMI,
	116	+ MX28_PAD_EMI_A07__EMI_ADDR7 \| MUX_CONFIG_EMI,
	117	+ MX28_PAD_EMI_A08__EMI_ADDR8 \| MUX_CONFIG_EMI,
	118	+ MX28_PAD_EMI_A09__EMI_ADDR9 \| MUX_CONFIG_EMI,
	119	+ MX28_PAD_EMI_A10__EMI_ADDR10 \| MUX_CONFIG_EMI,
	120	+ MX28_PAD_EMI_A11__EMI_ADDR11 \| MUX_CONFIG_EMI,
	121	+ MX28_PAD_EMI_A12__EMI_ADDR12 \| MUX_CONFIG_EMI,
	122	+ MX28_PAD_EMI_A13__EMI_ADDR13 \| MUX_CONFIG_EMI,
	123	+ MX28_PAD_EMI_A14__EMI_ADDR14 \| MUX_CONFIG_EMI,
	124	+ MX28_PAD_EMI_BA0__EMI_BA0 \| MUX_CONFIG_EMI,
	125	+ MX28_PAD_EMI_BA1__EMI_BA1 \| MUX_CONFIG_EMI,
	126	+ MX28_PAD_EMI_BA2__EMI_BA2 \| MUX_CONFIG_EMI,
	127	+ MX28_PAD_EMI_CASN__EMI_CASN \| MUX_CONFIG_EMI,
	128	+ MX28_PAD_EMI_RASN__EMI_RASN \| MUX_CONFIG_EMI,
	129	+ MX28_PAD_EMI_WEN__EMI_WEN \| MUX_CONFIG_EMI,
	130	+ MX28_PAD_EMI_CE0N__EMI_CE0N \| MUX_CONFIG_EMI,
	131	+ MX28_PAD_EMI_CE1N__EMI_CE1N \| MUX_CONFIG_EMI,
	132	+ MX28_PAD_EMI_CKE__EMI_CKE \| MUX_CONFIG_EMI,
	133	+};
	134	+
	135	+void board_init_ll(void)
	136	+{
	137	+ mx28_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
	138	+}
	1	+/*
	2	+ * Freescale MX28EVK board
	3	+ *
	4	+ * (C) Copyright 2011 Freescale Semiconductor, Inc.
	5	+ *
	6	+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
	7	+ *
	8	+ * Based on m28evk.c:
	9	+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
	10	+ * on behalf of DENX Software Engineering GmbH
	11	+ *
	12	+ * See file CREDITS for list of people who contributed to this
	13	+ * project.
	14	+ *
	15	+ * This program is free software; you can redistribute it and/or
	16	+ * modify it under the terms of the GNU General Public License as
	17	+ * published by the Free Software Foundation; either version 2 of
	18	+ * the License, or (at your option) any later version.
	19	+ *
	20	+ * This program is distributed in the hope that it will be useful,
	21	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	22	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	23	+ * GNU General Public License for more details.
	24	+ */
	25	+
	26	+#include <common.h>
	27	+#include <asm/gpio.h>
	28	+#include <asm/io.h>
	29	+#include <asm/arch/imx-regs.h>
	30	+#include <asm/arch/iomux-mx28.h>
	31	+#include <asm/arch/clock.h>
	32	+#include <asm/arch/sys_proto.h>
	33	+#include <linux/mii.h>
	34	+#include <miiphy.h>
	35	+#include <netdev.h>
	36	+#include <errno.h>
	37	+
	38	+DECLARE_GLOBAL_DATA_PTR;
	39	+
	40	+/*
	41	+ * Functions
	42	+ */
	43	+int board_early_init_f(void)
	44	+{
	45	+ /* IO0 clock at 480MHz */
	46	+ mx28_set_ioclk(MXC_IOCLK0, 480000);
	47	+ /* IO1 clock at 480MHz */
	48	+ mx28_set_ioclk(MXC_IOCLK1, 480000);
	49	+
	50	+ /* SSP0 clock at 96MHz */
	51	+ mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
	52	+ /* SSP2 clock at 96MHz */
	53	+ mx28_set_sspclk(MXC_SSPCLK2, 96000, 0);
	54	+
	55	+ return 0;
	56	+}
	57	+
	58	+int dram_init(void)
	59	+{
	60	+ return mx28_dram_init();
	61	+}
	62	+
	63	+int board_init(void)
	64	+{
	65	+ /* Adress of boot parameters */
	66	+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
	67	+
	68	+ return 0;
	69	+}
	70	+
	71	+#ifdef CONFIG_CMD_MMC
	72	+static int mx28evk_mmc_wp(int id)
	73	+{
	74	+ if (id != 0) {
	75	+ printf("MXS MMC: Invalid card selected (card id = %d)\n", id);
	76	+ return 1;
	77	+ }
	78	+
	79	+ return gpio_get_value(MX28_PAD_SSP1_SCK__GPIO_2_12);
	80	+}
	81	+
	82	+int board_mmc_init(bd_t *bis)
	83	+{
	84	+ /* Configure WP as input */
	85	+ gpio_direction_input(MX28_PAD_SSP1_SCK__GPIO_2_12);
	86	+
	87	+ /* Configure MMC0 Power Enable */
	88	+ gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
	89	+
	90	+ return mxsmmc_initialize(bis, 0, mx28evk_mmc_wp);
	91	+}
	92	+#endif
	93	+
	94	+#ifdef CONFIG_CMD_NET
	95	+
	96	+#define MII_OPMODE_STRAP_OVERRIDE 0x16
	97	+#define MII_PHY_CTRL1 0x1e
	98	+#define MII_PHY_CTRL2 0x1f
	99	+
	100	+int fecmxc_mii_postcall(int phy)
	101	+{
	102	+ miiphy_write("FEC1", phy, MII_BMCR, 0x9000);
	103	+ miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202);
	104	+ if (phy == 3)
	105	+ miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8180);
	106	+ return 0;
	107	+}
	108	+
	109	+int board_eth_init(bd_t *bis)
	110	+{
	111	+ struct mx28_clkctrl_regs *clkctrl_regs =
	112	+ (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
	113	+ struct eth_device *dev;
	114	+ int ret;
	115	+
	116	+ ret = cpu_eth_init(bis);
	117	+
	118	+ /* MX28EVK uses ENET_CLK PAD to drive FEC clock */
	119	+ writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK \| CLKCTRL_ENET_CLK_OUT_EN,
	120	+ &clkctrl_regs->hw_clkctrl_enet);
	121	+
	122	+ /* Power-on FECs */
	123	+ gpio_direction_output(MX28_PAD_SSP1_DATA3__GPIO_2_15, 0);
	124	+
	125	+ /* Reset FEC PHYs */
	126	+ gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
	127	+ udelay(200);
	128	+ gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
	129	+
	130	+ ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
	131	+ if (ret) {
	132	+ puts("FEC MXS: Unable to init FEC0\n");
	133	+ return ret;
	134	+ }
	135	+
	136	+ ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE);
	137	+ if (ret) {
	138	+ puts("FEC MXS: Unable to init FEC1\n");
	139	+ return ret;
	140	+ }
	141	+
	142	+ dev = eth_get_dev_by_name("FEC0");
	143	+ if (!dev) {
	144	+ puts("FEC MXS: Unable to get FEC0 device entry\n");
	145	+ return -EINVAL;
	146	+ }
	147	+
	148	+ ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
	149	+ if (ret) {
	150	+ puts("FEC MXS: Unable to register FEC0 mii postcall\n");
	151	+ return ret;
	152	+ }
	153	+
	154	+ dev = eth_get_dev_by_name("FEC1");
	155	+ if (!dev) {
	156	+ puts("FEC MXS: Unable to get FEC1 device entry\n");
	157	+ return -EINVAL;
	158	+ }
	159	+
	160	+ ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
	161	+ if (ret) {
	162	+ puts("FEC MXS: Unable to register FEC1 mii postcall\n");
	163	+ return ret;
	164	+ }
	165	+
	166	+ return ret;
	167	+}
	168	+
	169	+#endif
	1	+sources {
	2	+ u_boot_spl="spl/u-boot-spl.bin";
	3	+ u_boot="u-boot.bin";
	4	+}
	5	+
	6	+section (0) {
	7	+ load u_boot_spl > 0x0000;
	8	+ load ivt (entry = 0x0014) > 0x8000;
	9	+ hab call 0x8000;
	10	+
	11	+ load u_boot > 0x40000100;
	12	+ load ivt (entry = 0x40000100) > 0x8000;
	13	+ hab call 0x8000;
	14	+}
...	...	@@ -160,6 +160,7 @@
160	160	imx27lite arm arm926ejs imx27lite logicpd mx27
161	161	magnesium arm arm926ejs imx27lite logicpd mx27
162	162	m28evk arm arm926ejs - denx mx28
	163	+mx28evk arm arm926ejs - freescale mx28
163	164	nhk8815 arm arm926ejs nhk8815 st nomadik
164	165	nhk8815_onenand arm arm926ejs nhk8815 st nomadik nhk8815:BOOT_ONENAND
165	166	omap1610h2 arm arm926ejs omap1610inn ti omap omap1610inn:CS3_BOOT
	1	+/*
	2	+ * (C) Copyright 2011 Freescale Semiconductor, Inc.
	3	+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
	4	+ *
	5	+ * Based on m28evk.h:
	6	+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
	7	+ * on behalf of DENX Software Engineering GmbH
	8	+ *
	9	+ * This program is free software; you can redistribute it and/or
	10	+ * modify it under the terms of the GNU General Public License as
	11	+ * published by the Free Software Foundation; either version 2 of
	12	+ * the License, or (at your option) any later version.
	13	+ *
	14	+ * This program is distributed in the hope that it will be useful,
	15	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	+ * GNU General Public License for more details.
	18	+ */
	19	+#ifndef __CONFIG_H
	20	+#define __CONFIG_H
	21	+
	22	+#include <asm/arch/regs-base.h>
	23	+
	24	+/*
	25	+ * SoC configurations
	26	+ */
	27	+#define CONFIG_MX28 /* i.MX28 SoC */
	28	+#define CONFIG_MXS_GPIO /* GPIO control */
	29	+#define CONFIG_SYS_HZ 1000 /* Ticks per second */
	30	+
	31	+#define CONFIG_MACH_TYPE MACH_TYPE_MX28EVK
	32	+
	33	+#define CONFIG_SYS_NO_FLASH
	34	+#define CONFIG_SYS_ICACHE_OFF
	35	+#define CONFIG_SYS_DCACHE_OFF
	36	+#define CONFIG_BOARD_EARLY_INIT_F
	37	+#define CONFIG_ARCH_CPU_INIT
	38	+#define CONFIG_ARCH_MISC_INIT
	39	+
	40	+/*
	41	+ * SPL
	42	+ */
	43	+#define CONFIG_SPL
	44	+#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
	45	+#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mx28"
	46	+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds"
	47	+#define CONFIG_SPL_LIBCOMMON_SUPPORT
	48	+#define CONFIG_SPL_LIBGENERIC_SUPPORT
	49	+
	50	+/*
	51	+ * U-Boot Commands
	52	+ */
	53	+#include <config_cmd_default.h>
	54	+#define CONFIG_DISPLAY_CPUINFO
	55	+#define CONFIG_DOS_PARTITION
	56	+#define CONFIG_CMD_FAT
	57	+
	58	+#define CONFIG_CMD_CACHE
	59	+#define CONFIG_CMD_DHCP
	60	+#define CONFIG_CMD_GPIO
	61	+#define CONFIG_CMD_MII
	62	+#define CONFIG_CMD_MMC
	63	+#define CONFIG_CMD_NET
	64	+#define CONFIG_CMD_NFS
	65	+#define CONFIG_CMD_PING
	66	+
	67	+/*
	68	+ * Memory configurations
	69	+ */
	70	+#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
	71	+#define PHYS_SDRAM_1 0x40000000 /* Base address */
	72	+#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */
	73	+#define CONFIG_STACKSIZE (128 * 1024) /* 128 KB stack */
	74	+#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
	75	+#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
	76	+#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
	77	+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	78	+/* Point initial SP in SRAM so SPL can use it too. */
	79	+
	80	+#define CONFIG_SYS_INIT_RAM_ADDR 0x00002000
	81	+#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024)
	82	+
	83	+#define CONFIG_SYS_INIT_SP_OFFSET \
	84	+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	85	+#define CONFIG_SYS_INIT_SP_ADDR \
	86	+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	87	+
	88	+/*
	89	+ * We need to sacrifice first 4 bytes of RAM here to avoid triggering some
	90	+ * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
	91	+ * binary. In case there was more of this mess, 0x100 bytes are skipped.
	92	+ */
	93	+#define CONFIG_SYS_TEXT_BASE 0x40000100
	94	+
	95	+#define CONFIG_ENV_OVERWRITE
	96	+/*
	97	+ * U-Boot general configurations
	98	+ */
	99	+#define CONFIG_SYS_LONGHELP
	100	+#define CONFIG_SYS_PROMPT "MX28EVK U-Boot > "
	101	+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
	102	+#define CONFIG_SYS_PBSIZE \
	103	+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	104	+ /* Print buffer size */
	105	+#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
	106	+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	107	+ /* Boot argument buffer size */
	108	+#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
	109	+#define CONFIG_AUTO_COMPLETE /* Command auto complete */
	110	+#define CONFIG_CMDLINE_EDITING /* Command history etc */
	111	+#define CONFIG_SYS_HUSH_PARSER
	112	+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
	113	+
	114	+/*
	115	+ * Serial Driver
	116	+ */
	117	+#define CONFIG_PL011_SERIAL
	118	+#define CONFIG_PL011_CLOCK 24000000
	119	+#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
	120	+#define CONFIG_CONS_INDEX 0
	121	+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
	122	+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	123	+
	124	+/*
	125	+ * MMC Driver
	126	+ */
	127	+#define CONFIG_ENV_IS_IN_MMC
	128	+#define CONFIG_ENV_OFFSET (256 * 1024)
	129	+#define CONFIG_ENV_SIZE (16 * 1024)
	130	+#define CONFIG_SYS_MMC_ENV_DEV 0
	131	+#define CONFIG_CMD_SAVEENV
	132	+#ifdef CONFIG_CMD_MMC
	133	+#define CONFIG_MMC
	134	+#define CONFIG_GENERIC_MMC
	135	+#define CONFIG_MXS_MMC
	136	+#endif
	137	+
	138	+/*
	139	+ * Ethernet on SOC (FEC)
	140	+ */
	141	+#ifdef CONFIG_CMD_NET
	142	+#define CONFIG_NET_MULTI
	143	+#define CONFIG_ETHPRIME "FEC0"
	144	+#define CONFIG_FEC_MXC
	145	+#define CONFIG_FEC_MXC_MULTI
	146	+#define CONFIG_MII
	147	+#define CONFIG_DISCOVER_PHY
	148	+#define CONFIG_FEC_XCV_TYPE RMII
	149	+#define CONFIG_MX28_FEC_MAC_IN_OCOTP
	150	+#endif
	151	+
	152	+/*
	153	+ * Boot Linux
	154	+ */
	155	+#define CONFIG_CMDLINE_TAG
	156	+#define CONFIG_SETUP_MEMORY_TAGS
	157	+#define CONFIG_BOOTDELAY 3
	158	+#define CONFIG_BOOTFILE "uImage"
	159	+#define CONFIG_BOOTCOMMAND "run bootcmd_net"
	160	+#define CONFIG_LOADADDR 0x42000000
	161	+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
	162	+
	163	+/*
	164	+ * Extra Environments
	165	+ */
	166	+#define CONFIG_EXTRA_ENV_SETTINGS \
	167	+ "console_fsl=console=ttyAM0" \
	168	+ "console_mainline=console=ttyAMA0" \
	169	+ "netargs=setenv bootargs console=${console_mainline}" \
	170	+ "root=/dev/nfs " \
	171	+ "ip=dhcp nfsroot=${serverip}:${nfsroot}\0" \
	172	+ "bootcmd_net=echo Booting from net ...; " \
	173	+ "run netargs; " \
	174	+ "dhcp ${uimage}; bootm\0" \
	175	+
	176	+#endif /* __CONFIG_H */