sbc8548: relocate fixed ddr init code to ddr.c file

Nothing to see here, just a relocation of the fixed ddr init sequence to live in the actual ddr.c file itself. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

sbc8548: relocate fixed ddr init code to ddr.c file
Nothing to see here, just a relocation of the fixed ddr init sequence to live in the actual ddr.c file itself. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Paul Gortmaker · Kumar Gala
1 parent 7e44f2b710
Showing 3 changed files with 49 additions and 44 deletions Side-by-side Diff
board/sbc8548/ddr.c
board/sbc8548/sbc8548.c
include/configs/sbc8548.h
@@ -54,4 +54,52 @@
 	 */
 	popts->half_strength_driver_enable = 0;
 }
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*
+ *  fixed_sdram init -- doesn't use serial presence detect.
+ *  Assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
+ */
+phys_size_t fixed_sdram(void)
+{
+	volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+
+	out_be32(&ddr->cs0_bnds,	0x0000007f);
+	out_be32(&ddr->cs1_bnds,	0x008000ff);
+	out_be32(&ddr->cs2_bnds,	0x00000000);
+	out_be32(&ddr->cs3_bnds,	0x00000000);
+
+	out_be32(&ddr->cs0_config,	0x80010101);
+	out_be32(&ddr->cs1_config,	0x80010101);
+	out_be32(&ddr->cs2_config,	0x00000000);
+	out_be32(&ddr->cs3_config,	0x00000000);
+
+	out_be32(&ddr->timing_cfg_3,	0x00000000);
+	out_be32(&ddr->timing_cfg_0,	0x00220802);
+	out_be32(&ddr->timing_cfg_1,	0x38377322);
+	out_be32(&ddr->timing_cfg_2,	0x0fa044C7);
+
+	out_be32(&ddr->sdram_cfg,	0x4300C000);
+	out_be32(&ddr->sdram_cfg_2,	0x24401000);
+
+	out_be32(&ddr->sdram_mode,	0x23C00542);
+	out_be32(&ddr->sdram_mode_2,	0x00000000);
+
+	out_be32(&ddr->sdram_interval,	0x05080100);
+	out_be32(&ddr->sdram_md_cntl,	0x00000000);
+	out_be32(&ddr->sdram_data_init,	0x00000000);
+	out_be32(&ddr->sdram_clk_cntl,	0x03800000);
+	asm("sync;isync;msync");
+	udelay(500);
+
+	#ifdef CONFIG_DDR_ECC
+	  /* Enable ECC checking */
+	  out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000);
+	#else
+	  out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
+	#endif
+
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+#endif
@@ -219,50 +219,6 @@
 }
 #endif
  
-#if !defined(CONFIG_SPD_EEPROM)
-#define CONFIG_SYS_DDR_CONTROL 0xc300c000
-/*************************************************************************
- *  fixed_sdram init -- doesn't use serial presence detect.
- *  assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
- ************************************************************************/
-phys_size_t fixed_sdram(void)
-{
-	volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
-
-	out_be32(&ddr->cs0_bnds, 0x0000007f);
-	out_be32(&ddr->cs1_bnds, 0x008000ff);
-	out_be32(&ddr->cs2_bnds, 0x00000000);
-	out_be32(&ddr->cs3_bnds, 0x00000000);
-	out_be32(&ddr->cs0_config, 0x80010101);
-	out_be32(&ddr->cs1_config, 0x80010101);
-	out_be32(&ddr->cs2_config, 0x00000000);
-	out_be32(&ddr->cs3_config, 0x00000000);
-	out_be32(&ddr->timing_cfg_3, 0x00000000);
-	out_be32(&ddr->timing_cfg_0, 0x00220802);
-	out_be32(&ddr->timing_cfg_1, 0x38377322);
-	out_be32(&ddr->timing_cfg_2, 0x0fa044C7);
-	out_be32(&ddr->sdram_cfg, 0x4300C000);
-	out_be32(&ddr->sdram_cfg_2, 0x24401000);
-	out_be32(&ddr->sdram_mode, 0x23C00542);
-	out_be32(&ddr->sdram_mode_2, 0x00000000);
-	out_be32(&ddr->sdram_interval, 0x05080100);
-	out_be32(&ddr->sdram_md_cntl, 0x00000000);
-	out_be32(&ddr->sdram_data_init, 0x00000000);
-	out_be32(&ddr->sdram_clk_cntl, 0x03800000);
-	asm("sync;isync;msync");
-	udelay(500);
-
-	#if defined (CONFIG_DDR_ECC)
-	  /* Enable ECC checking */
-	  out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000);
-	#else
-	  out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
-	#endif
-
-	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-}
-#endif
-
 #ifdef CONFIG_PCI1
 static struct pci_controller pci1_hose;
 #endif	/* CONFIG_PCI1 */
@@ -148,6 +148,7 @@
  */
 #ifndef CONFIG_SPD_EEPROM
 	#define CONFIG_SYS_SDRAM_SIZE	256		/* DDR is 256MB */
+	#define CONFIG_SYS_DDR_CONTROL	0xc300c000
 #endif
  
 #undef CONFIG_CLOCKS_IN_MHZ
...	...	@@ -54,4 +54,52 @@
54	54	*/
55	55	popts->half_strength_driver_enable = 0;
56	56	}
	57	+
	58	+#if !defined(CONFIG_SPD_EEPROM)
	59	+/*
	60	+ * fixed_sdram init -- doesn't use serial presence detect.
	61	+ * Assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
	62	+ */
	63	+phys_size_t fixed_sdram(void)
	64	+{
	65	+ volatile ccsr_ddr_t ddr = (void )(CONFIG_SYS_MPC85xx_DDR_ADDR);
	66	+
	67	+ out_be32(&ddr->cs0_bnds, 0x0000007f);
	68	+ out_be32(&ddr->cs1_bnds, 0x008000ff);
	69	+ out_be32(&ddr->cs2_bnds, 0x00000000);
	70	+ out_be32(&ddr->cs3_bnds, 0x00000000);
	71	+
	72	+ out_be32(&ddr->cs0_config, 0x80010101);
	73	+ out_be32(&ddr->cs1_config, 0x80010101);
	74	+ out_be32(&ddr->cs2_config, 0x00000000);
	75	+ out_be32(&ddr->cs3_config, 0x00000000);
	76	+
	77	+ out_be32(&ddr->timing_cfg_3, 0x00000000);
	78	+ out_be32(&ddr->timing_cfg_0, 0x00220802);
	79	+ out_be32(&ddr->timing_cfg_1, 0x38377322);
	80	+ out_be32(&ddr->timing_cfg_2, 0x0fa044C7);
	81	+
	82	+ out_be32(&ddr->sdram_cfg, 0x4300C000);
	83	+ out_be32(&ddr->sdram_cfg_2, 0x24401000);
	84	+
	85	+ out_be32(&ddr->sdram_mode, 0x23C00542);
	86	+ out_be32(&ddr->sdram_mode_2, 0x00000000);
	87	+
	88	+ out_be32(&ddr->sdram_interval, 0x05080100);
	89	+ out_be32(&ddr->sdram_md_cntl, 0x00000000);
	90	+ out_be32(&ddr->sdram_data_init, 0x00000000);
	91	+ out_be32(&ddr->sdram_clk_cntl, 0x03800000);
	92	+ asm("sync;isync;msync");
	93	+ udelay(500);
	94	+
	95	+ #ifdef CONFIG_DDR_ECC
	96	+ /* Enable ECC checking */
	97	+ out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL \| 0x20000000);
	98	+ #else
	99	+ out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
	100	+ #endif
	101	+
	102	+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
	103	+}
	104	+#endif
...	...	@@ -219,50 +219,6 @@
219	219	}
220	220	#endif
221	221
222		-#if !defined(CONFIG_SPD_EEPROM)
223		-#define CONFIG_SYS_DDR_CONTROL 0xc300c000
224		-/*************************************************************************
225		- * fixed_sdram init -- doesn't use serial presence detect.
226		- * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
227		- ************************************************************************/
228		-phys_size_t fixed_sdram(void)
229		-{
230		- volatile ccsr_ddr_t ddr = (void )(CONFIG_SYS_MPC85xx_DDR_ADDR);
231		-
232		- out_be32(&ddr->cs0_bnds, 0x0000007f);
233		- out_be32(&ddr->cs1_bnds, 0x008000ff);
234		- out_be32(&ddr->cs2_bnds, 0x00000000);
235		- out_be32(&ddr->cs3_bnds, 0x00000000);
236		- out_be32(&ddr->cs0_config, 0x80010101);
237		- out_be32(&ddr->cs1_config, 0x80010101);
238		- out_be32(&ddr->cs2_config, 0x00000000);
239		- out_be32(&ddr->cs3_config, 0x00000000);
240		- out_be32(&ddr->timing_cfg_3, 0x00000000);
241		- out_be32(&ddr->timing_cfg_0, 0x00220802);
242		- out_be32(&ddr->timing_cfg_1, 0x38377322);
243		- out_be32(&ddr->timing_cfg_2, 0x0fa044C7);
244		- out_be32(&ddr->sdram_cfg, 0x4300C000);
245		- out_be32(&ddr->sdram_cfg_2, 0x24401000);
246		- out_be32(&ddr->sdram_mode, 0x23C00542);
247		- out_be32(&ddr->sdram_mode_2, 0x00000000);
248		- out_be32(&ddr->sdram_interval, 0x05080100);
249		- out_be32(&ddr->sdram_md_cntl, 0x00000000);
250		- out_be32(&ddr->sdram_data_init, 0x00000000);
251		- out_be32(&ddr->sdram_clk_cntl, 0x03800000);
252		- asm("sync;isync;msync");
253		- udelay(500);
254		-
255		- #if defined (CONFIG_DDR_ECC)
256		- /* Enable ECC checking */
257		- out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL \| 0x20000000);
258		- #else
259		- out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
260		- #endif
261		-
262		- return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
263		-}
264		-#endif
265		-
266	222	#ifdef CONFIG_PCI1
267	223	static struct pci_controller pci1_hose;
268	224	#endif /* CONFIG_PCI1 */
...	...	@@ -148,6 +148,7 @@
148	148	*/
149	149	#ifndef CONFIG_SPD_EEPROM
150	150	#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
	151	+ #define CONFIG_SYS_DDR_CONTROL 0xc300c000
151	152	#endif
152	153
153	154	#undef CONFIG_CLOCKS_IN_MHZ