Eric Lee / smarc-uboot

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Commit 2aa20c43e464b8e5e554b86c51334d789833f254

Authored by Bartosz Golaszewski
Committed by Tom Rini
1 parent 899dd71e9f
Exists in smarc_8mq_lf_v2020.04 and in 9 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

twister: remove board 

This board still doesn't select CONFIG_DM and seems to be umaintained.
As it makes progress on modernizing several DaVinci drivers more
difficult and the maintainer has not expressed interest in updating
it, this patch proposes to remove it.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Acked-by: Stefano Babic <sbabic@denx.de>

Showing 9 changed files with 0 additions and 678 deletions Side-by-side Diff

arch/arm/include/asm/mach-types.h
Diff comments   View file @ 2aa20c4
... ... @@ -629,7 +629,6 @@
629 629 #define MACH_TYPE_ECIA 623
630 630 #define MACH_TYPE_CM4008 624
631 631 #define MACH_TYPE_P2001 625
632   -#define MACH_TYPE_TWISTER 626
633 632 #define MACH_TYPE_MUDSHARK 627
634 633 #define MACH_TYPE_HB2 628
635 634 #define MACH_TYPE_IQ80332 629
arch/arm/mach-omap2/omap3/Kconfig
Diff comments   View file @ 2aa20c4
... ... @@ -133,11 +133,6 @@
133 133 select OMAP3_GPIO_5
134 134 select OMAP3_GPIO_6
135 135  
136   -config TARGET_TWISTER
137   - bool "Twister"
138   - select OMAP3_GPIO_2
139   - select OMAP3_GPIO_5 if USB_EHCI_HCD
140   -
141 136 config TARGET_OMAP3_CAIRO
142 137 bool "QUIPOS CAIRO"
143 138 select DM
... ... @@ -198,7 +193,6 @@
198 193 source "board/logicpd/omap3som/Kconfig"
199 194 source "board/nokia/rx51/Kconfig"
200 195 source "board/technexion/tao3530/Kconfig"
201   -source "board/technexion/twister/Kconfig"
202 196 source "board/quipos/cairo/Kconfig"
203 197 source "board/lg/sniper/Kconfig"
204 198  
board/technexion/twister/Kconfig
View file @ 2aa20c4
1   -if TARGET_TWISTER
2   -
3   -config SYS_BOARD
4   - default "twister"
5   -
6   -config SYS_VENDOR
7   - default "technexion"
8   -
9   -config SYS_CONFIG_NAME
10   - default "twister"
11   -
12   -endif
board/technexion/twister/MAINTAINERS
View file @ 2aa20c4
1   -TWISTER BOARD
2   -M: Stefano Babic <sbabic@denx.de>
3   -S: Maintained
4   -F: board/technexion/twister/
5   -F: include/configs/twister.h
6   -F: configs/twister_defconfig
board/technexion/twister/Makefile
View file @ 2aa20c4
1   -# SPDX-License-Identifier: GPL-2.0+
2   -#
3   -# Copyright (C) 2011 Ilya Yanok, Emcraft Systems
4   -#
5   -# Based on ti/evm/Makefile
6   -
7   -obj-y := twister.o
board/technexion/twister/twister.c
View file @ 2aa20c4
1   -// SPDX-License-Identifier: GPL-2.0+
2   -/*
3   - * Copyright (C) 2011
4   - * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
5   - *
6   - * Copyright (C) 2009 TechNexion Ltd.
7   - */
8   -
9   -#include <common.h>
10   -#include <netdev.h>
11   -#include <asm/io.h>
12   -#include <asm/arch/mem.h>
13   -#include <asm/arch/mux.h>
14   -#include <asm/arch/sys_proto.h>
15   -#include <asm/omap_gpio.h>
16   -#include <asm/arch/mmc_host_def.h>
17   -#include <i2c.h>
18   -#include <spl.h>
19   -#include <mmc.h>
20   -#include <asm/gpio.h>
21   -#include <usb.h>
22   -#include <asm/ehci-omap.h>
23   -#include "twister.h"
24   -
25   -DECLARE_GLOBAL_DATA_PTR;
26   -
27   -/* Timing definitions for Ethernet Controller */
28   -static const u32 gpmc_smc911[] = {
29   - NET_GPMC_CONFIG1,
30   - NET_GPMC_CONFIG2,
31   - NET_GPMC_CONFIG3,
32   - NET_GPMC_CONFIG4,
33   - NET_GPMC_CONFIG5,
34   - NET_GPMC_CONFIG6,
35   -};
36   -
37   -static const u32 gpmc_XR16L2751[] = {
38   - XR16L2751_GPMC_CONFIG1,
39   - XR16L2751_GPMC_CONFIG2,
40   - XR16L2751_GPMC_CONFIG3,
41   - XR16L2751_GPMC_CONFIG4,
42   - XR16L2751_GPMC_CONFIG5,
43   - XR16L2751_GPMC_CONFIG6,
44   -};
45   -
46   -#ifdef CONFIG_USB_EHCI_OMAP
47   -static struct omap_usbhs_board_data usbhs_bdata = {
48   - .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
49   - .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
50   - .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
51   -};
52   -
53   -int ehci_hcd_init(int index, enum usb_init_type init,
54   - struct ehci_hccr **hccr, struct ehci_hcor **hcor)
55   -{
56   - return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
57   -}
58   -
59   -int ehci_hcd_stop(int index)
60   -{
61   - return omap_ehci_hcd_stop();
62   -}
63   -#endif
64   -
65   -int board_init(void)
66   -{
67   - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
68   -
69   - /* boot param addr */
70   - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
71   -
72   - /* Chip select 1 and 3 are used for XR16L2751 UART controller */
73   - enable_gpmc_cs_config(gpmc_XR16L2751, &gpmc_cfg->cs[1],
74   - XR16L2751_UART1_BASE, GPMC_SIZE_16M);
75   -
76   - enable_gpmc_cs_config(gpmc_XR16L2751, &gpmc_cfg->cs[3],
77   - XR16L2751_UART2_BASE, GPMC_SIZE_16M);
78   -
79   - gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB_PHY1_RESET");
80   - gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, 1);
81   -
82   - return 0;
83   -}
84   -
85   -#ifndef CONFIG_SPL_BUILD
86   -int misc_init_r(void)
87   -{
88   - char *eth_addr;
89   - struct tam3517_module_info info;
90   - int ret;
91   -
92   - omap_die_id_display();
93   -
94   - eth_addr = env_get("ethaddr");
95   - if (eth_addr)
96   - return 0;
97   -
98   - TAM3517_READ_EEPROM(&info, ret);
99   - if (!ret)
100   - TAM3517_READ_MAC_FROM_EEPROM(&info);
101   -
102   - return 0;
103   -}
104   -#endif
105   -
106   -/*
107   - * Routine: set_muxconf_regs
108   - * Description: Setting up the configuration Mux registers specific to the
109   - * hardware. Many pins need to be moved from protect to primary
110   - * mode.
111   - */
112   -void set_muxconf_regs(void)
113   -{
114   - MUX_TWISTER();
115   -}
116   -
117   -int board_eth_init(bd_t *bis)
118   -{
119   -#ifdef CONFIG_DRIVER_TI_EMAC
120   - davinci_emac_initialize();
121   -#endif
122   - /* init cs for extern lan */
123   - enable_gpmc_cs_config(gpmc_smc911, &gpmc_cfg->cs[5],
124   - CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
125   -#ifdef CONFIG_SMC911X
126   - return smc911x_initialize(0, CONFIG_SMC911X_BASE);
127   -#else
128   - return 0;
129   -#endif
130   -}
131   -
132   -#if defined(CONFIG_MMC_OMAP_HS)
133   -int board_mmc_init(bd_t *bis)
134   -{
135   - return omap_mmc_init(0, 0, 0, -1, -1);
136   -}
137   -#endif
138   -
139   -#ifdef CONFIG_SPL_OS_BOOT
140   -/*
141   - * Do board specific preparation before SPL
142   - * Linux boot
143   - */
144   -void spl_board_prepare_for_linux(void)
145   -{
146   - /* init cs for extern lan */
147   - enable_gpmc_cs_config(gpmc_smc911, &gpmc_cfg->cs[5],
148   - CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
149   -}
150   -int spl_start_uboot(void)
151   -{
152   - int val = 0;
153   - if (!gpio_request(SPL_OS_BOOT_KEY, "U-Boot key")) {
154   - gpio_direction_input(SPL_OS_BOOT_KEY);
155   - val = gpio_get_value(SPL_OS_BOOT_KEY);
156   - gpio_free(SPL_OS_BOOT_KEY);
157   - }
158   - return val;
159   -}
160   -#endif
board/technexion/twister/twister.h
View file @ 2aa20c4
1   -/* SPDX-License-Identifier: GPL-2.0+ */
2   -/*
3   - * Copyright (C) 2011
4   - * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
5   - *
6   - * Copyright (C) 2010 TechNexion Ltd.
7   - */
8   -
9   -#ifndef _TAM3517_H_
10   -#define _TAM3517_H_
11   -
12   -const omap3_sysinfo sysinfo = {
13   - DDR_DISCRETE,
14   - "TAM3517 TWISTER Board",
15   - "NAND",
16   -};
17   -
18   -#define XR16L2751_GPMC_CONFIG1 0x00000000
19   -#define XR16L2751_GPMC_CONFIG2 0x001e1e01
20   -#define XR16L2751_GPMC_CONFIG3 0x00080300
21   -#define XR16L2751_GPMC_CONFIG4 0x1c091c09
22   -#define XR16L2751_GPMC_CONFIG5 0x04181f1f
23   -#define XR16L2751_GPMC_CONFIG6 0x00000FCF
24   -
25   -#define XR16L2751_UART1_BASE 0x21000000
26   -#define XR16L2751_UART2_BASE 0x23000000
27   -
28   -/* GPIO used to select between U-Boot and kernel */
29   -#define SPL_OS_BOOT_KEY 55
30   -
31   -/*
32   - * IEN - Input Enable
33   - * IDIS - Input Disable
34   - * PTD - Pull type Down
35   - * PTU - Pull type Up
36   - * DIS - Pull type selection is inactive
37   - * EN - Pull type selection is active
38   - * M0 - Mode 0
39   - * The commented string gives the final mux configuration for that pin
40   - */
41   -#define MUX_TWISTER() \
42   - /* SDRC */\
43   - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
44   - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
45   - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
46   - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
47   - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
48   - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
49   - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
50   - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
51   - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
52   - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
53   - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
54   - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
55   - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
56   - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
57   - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
58   - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
59   - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
60   - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
61   - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
62   - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
63   - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
64   - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
65   - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
66   - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
67   - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
68   - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
69   - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
70   - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
71   - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
72   - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
73   - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
74   - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
75   - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
76   - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
77   - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
78   - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
79   - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
80   - MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
81   - MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
82   - MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \
83   - MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \
84   - MUX_VAL(CP(SDRC_CKE0), (M0)) \
85   - MUX_VAL(CP(SDRC_CKE1), (M0)) \
86   - MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \
87   - /*sdrc_strben_dly0*/\
88   - MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \
89   - /*sdrc_strben_dly1*/\
90   - /* GPMC */\
91   - MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
92   - MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
93   - MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
94   - MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
95   - MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
96   - MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
97   - MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
98   - MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
99   - MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
100   - MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
101   - MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
102   - MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
103   - MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
104   - MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
105   - MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
106   - MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
107   - MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
108   - MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
109   - MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
110   - MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
111   - MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
112   - MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
113   - MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
114   - MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
115   - MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
116   - MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
117   - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
118   - MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M0)) \
119   - MUX_VAL(CP(GPMC_NCS2), (IDIS | PTD | EN | M2)) /*PWM9*/\
120   - MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M0)) \
121   - MUX_VAL(CP(GPMC_NCS4), (IEN | PTD | EN | M4)) \
122   - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) \
123   - MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | EN | M3)) /*PWM11*/ \
124   - MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | EN | M4)) /*GPIO_58*/ \
125   - MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \
126   - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
127   - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
128   - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
129   - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
130   - MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \
131   - MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \
132   - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \
133   - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) \
134   - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
135   - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \
136   - /* DSS */\
137   - MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
138   - MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
139   - MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
140   - MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
141   - MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \
142   - MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \
143   - MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \
144   - MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \
145   - MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \
146   - MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \
147   - MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \
148   - MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \
149   - MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \
150   - MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \
151   - MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \
152   - MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \
153   - MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \
154   - MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \
155   - MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \
156   - MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \
157   - MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \
158   - MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \
159   - MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
160   - MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
161   - MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
162   - MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
163   - MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
164   - MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
165   - /* CAMERA */\
166   - MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \
167   - MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \
168   - MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \
169   - MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \
170   - MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
171   - MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \
172   - MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \
173   - MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \
174   - MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \
175   - MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \
176   - MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \
177   - MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \
178   - MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \
179   - MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \
180   - MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \
181   - MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \
182   - MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \
183   - MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \
184   - MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
185   - MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \
186   - MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \
187   - MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \
188   - MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \
189   - MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \
190   - /* MMC */\
191   - MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
192   - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
193   - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \
194   - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
195   - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
196   - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
197   - MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
198   - /* CardDetect */\
199   - MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \
200   - MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
201   - MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
202   - \
203   - MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) \
204   - MUX_VAL(CP(MMC2_CMD), (IEN | PTU | DIS | M0)) \
205   - MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | DIS | M0)) \
206   - MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | DIS | M0)) \
207   - MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | DIS | M0)) \
208   - MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | DIS | M0)) \
209   - MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | EN | M4)) \
210   - MUX_VAL(CP(MMC2_DAT5), (IDIS | PTU | EN | M4)) \
211   - MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) \
212   - MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) \
213   - /* McBSP */\
214   - MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
215   - MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
216   - MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
217   - MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
218   - MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
219   - MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
220   - MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
221   - \
222   - MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | EN | M4)) /*GPIO_116*/ \
223   - MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | EN | M4)) \
224   - MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | EN | M4)) \
225   - MUX_VAL(CP(MCBSP2_DX), (IEN | PTD | EN | M4)) \
226   - \
227   - MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \
228   - MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) \
229   - MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \
230   - MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4)) \
231   - \
232   - MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_152*/\
233   - MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\
234   - MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\
235   - MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M4)) /*GPIO_155*/\
236   - /* UART */\
237   - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
238   - MUX_VAL(CP(UART1_RTS), (IEN | PTU | EN | M4)) \
239   - MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M4)) \
240   - \
241   - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
242   - MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
243   - MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
244   - MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
245   - MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \
246   - \
247   - MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | DIS | M4)) /*GPIO_163*/ \
248   - MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | DIS | M4)) /*GPIO_164*/\
249   - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
250   - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
251   - /* I2C */\
252   - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
253   - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
254   - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
255   - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
256   - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
257   - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
258   - MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
259   - MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
260   - /* McSPI */\
261   - MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
262   - MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
263   - MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
264   - MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
265   - MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\
266   - MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M4)) /*GPIO_176*/\
267   - MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M4)) \
268   - \
269   - MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \
270   - MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \
271   - MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \
272   - MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \
273   - MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M4)) \
274   - /* CCDC */\
275   - MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \
276   - MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1)) \
277   - MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \
278   - MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \
279   - MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1)) \
280   - MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \
281   - MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0)) \
282   - MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \
283   - MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \
284   - MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \
285   - MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \
286   - MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \
287   - MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \
288   - /* RMII */\
289   - MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
290   - MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
291   - MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \
292   - MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
293   - MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
294   - MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
295   - MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
296   - MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
297   - MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
298   - MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
299   - /* HECC */\
300   - MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \
301   - MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \
302   - /* HSUSB */\
303   - MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
304   - MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \
305   - MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
306   - MUX_VAL(CP(HSUSB0_NXT), (IEN | PTU | DIS | M0)) \
307   - MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
308   - MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
309   - MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
310   - MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
311   - MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
312   - MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
313   - MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
314   - MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
315   - MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
316   - /* HDQ */\
317   - MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \
318   - /* Control and debug */\
319   - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \
320   - MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
321   - MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \
322   - MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \
323   - /* - GPIO30 */\
324   - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
325   - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
326   - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
327   - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
328   - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
329   - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
330   - MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
331   - /* - VIO_1V8*/\
332   - MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \
333   - MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \
334   - \
335   - MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
336   - MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \
337   - MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
338   - /* JTAG */\
339   - MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \
340   - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
341   - MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
342   - MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \
343   - MUX_VAL(CP(JTAG_EMU0), (IDIS | PTD | EN | M4)) /*GPIO_11*/ \
344   - MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | EN | M4)) /*GPIO_31*/ \
345   - /* ETK (ES2 onwards) */\
346   - MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \
347   - /* hsusb1_stp */ \
348   - MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \
349   - /* hsusb1_clk */\
350   - MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M3)) \
351   - MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | EN | M3)) \
352   - MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M3)) \
353   - MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M3)) \
354   - MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M3)) \
355   - MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M3)) \
356   - MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M3)) \
357   - MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M3)) \
358   - MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \
359   - /* hsusb1_dir */\
360   - MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \
361   - /* hsusb1_nxt */\
362   - MUX_VAL(CP(ETK_D10_ES2), (IEN | PTU | EN | M4)) \
363   - MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M4)) \
364   - MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M4)) \
365   - MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M4)) \
366   - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \
367   - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \
368   - /* Die to Die */\
369   - MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
370   - MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
371   - MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
372   - MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
373   - MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
374   - MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
375   - MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
376   - MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
377   - MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
378   - MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
379   - MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
380   - MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
381   - MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
382   - MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
383   - MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
384   - MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
385   - MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
386   - MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
387   - MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
388   - MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
389   - MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
390   - MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
391   - MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
392   - MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
393   - MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
394   - MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
395   - MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
396   - MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
397   - MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
398   - MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \
399   -
400   -#endif
configs/twister_defconfig
View file @ 2aa20c4
1   -CONFIG_ARM=y
2   -# CONFIG_SYS_THUMB_BUILD is not set
3   -CONFIG_ARCH_OMAP2PLUS=y
4   -CONFIG_SYS_TEXT_BASE=0x80008000
5   -CONFIG_TARGET_TWISTER=y
6   -CONFIG_EMIF4=y
7   -CONFIG_NR_DRAM_BANKS=2
8   -CONFIG_SPL=y
9   -CONFIG_BOOTDELAY=10
10   -CONFIG_SPL_TEXT_BASE=0x40200000
11   -# CONFIG_SPL_FS_EXT4 is not set
12   -CONFIG_SPL_OS_BOOT=y
13   -CONFIG_HUSH_PARSER=y
14   -CONFIG_SYS_PROMPT="twister => "
15   -CONFIG_CMD_SPL=y
16   -CONFIG_CMD_SPL_NAND_OFS=0x00800000
17   -CONFIG_CMD_SPL_WRITE_SIZE=0x400
18   -CONFIG_CMD_EEPROM=y
19   -# CONFIG_CMD_FLASH is not set
20   -CONFIG_CMD_GPIO=y
21   -CONFIG_CMD_I2C=y
22   -CONFIG_CMD_MMC=y
23   -CONFIG_CMD_NAND=y
24   -CONFIG_CMD_USB=y
25   -# CONFIG_CMD_SETEXPR is not set
26   -CONFIG_CMD_DHCP=y
27   -CONFIG_CMD_MII=y
28   -CONFIG_CMD_PING=y
29   -CONFIG_CMD_CACHE=y
30   -CONFIG_CMD_EXT2=y
31   -CONFIG_CMD_FAT=y
32   -CONFIG_CMD_MTDPARTS=y
33   -CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
34   -CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1m(u-boot),256k(env1),256k(env2),6m(kernel),-(rootfs)"
35   -CONFIG_CMD_UBI=y
36   -CONFIG_ENV_IS_IN_NAND=y
37   -CONFIG_SYS_OMAP24_I2C_SPEED=400000
38   -CONFIG_MMC_OMAP_HS=y
39   -CONFIG_NAND=y
40   -CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
41   -CONFIG_SPL_NAND_SIMPLE=y
42   -CONFIG_MII=y
43   -CONFIG_SMC911X=y
44   -CONFIG_SMC911X_BASE=0x2C000000
45   -CONFIG_DRIVER_TI_EMAC=y
46   -CONFIG_SYS_NS16550=y
47   -CONFIG_USB=y
48   -CONFIG_USB_EHCI_HCD=y
49   -CONFIG_USB_ULPI_VIEWPORT_OMAP=y
50   -CONFIG_USB_ULPI=y
51   -CONFIG_USB_STORAGE=y
52   -CONFIG_OF_LIBFDT=y
include/configs/twister.h
View file @ 2aa20c4
1   -/* SPDX-License-Identifier: GPL-2.0+ */
2   -/*
3   - * Copyright (C) 2011
4   - * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
5   - *
6   - * Copyright (C) 2009 TechNexion Ltd.
7   - *
8   - * Configuration for the Technexion twister board.
9   - */
10   -
11   -#ifndef __CONFIG_H
12   -#define __CONFIG_H
13   -
14   -#include "tam3517-common.h"
15   -
16   -#define CONFIG_MACH_TYPE MACH_TYPE_TAM3517
17   -
18   -#define CONFIG_TAM3517_SW3_SETTINGS
19   -#define CONFIG_XR16L2751
20   -
21   -
22   -#define CONFIG_BOOTFILE "uImage"
23   -
24   -#define CONFIG_HOSTNAME "twister"
25   -
26   -#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_TAM3517_SETTINGS \
27   - "bootcmd=run nandboot\0"
28   -
29   -/* SPL OS boot options */
30   -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000
31   -
32   -#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100)
33   -
34   -#endif /* __CONFIG_H */