arm: mvebu: Add Armada A38x DB-88F6820-GP board support

This patch adds support for the Marvell DB-88F6820-GP Armada A38x evaluation board. Supported peripherals are: - UART - Ethernet (mvneta) - I2C - SPI (including SPI NOR flash) Please note that this board support right now only supports the main U-Boot. Without the bin_hdr integration (DDR training etc). This will be added in a few days / weeks to complete this board port. But till then this U-Boot version can be run on the target via the original Marvell U-Boot via this command: tftpboot 4000000 db-88f6820-gp/u-boot.bin;go 4000000 Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com> Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>

arm: mvebu: Add Armada A38x DB-88F6820-GP board support
This patch adds support for the Marvell DB-88F6820-GP Armada A38x evaluation board. Supported peripherals are: - UART - Ethernet (mvneta) - I2C - SPI (including SPI NOR flash) Please note that this board support right now only supports the main U-Boot. Without the bin_hdr integration (DDR training etc). This will be added in a few days / weeks to complete this board port. But till then this U-Boot version can be run on the target via the original Marvell U-Boot via this command: tftpboot 4000000 db-88f6820-gp/u-boot.bin;go 4000000 Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com> Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Stefan Roese · Luka Perkov
1 parent 60b75324ea
Showing 8 changed files with 233 additions and 0 deletions Side-by-side Diff
arch/arm/Kconfig
board/Marvell/db-88f6820-gp/Kconfig
board/Marvell/db-88f6820-gp/Makefile
board/Marvell/db-88f6820-gp/binary.0
board/Marvell/db-88f6820-gp/db-88f6820-gp.c
board/Marvell/db-88f6820-gp/kwbimage.cfg
configs/db-88f6820-gp_defconfig
include/configs/db-88f6820-gp.h
@@ -102,6 +102,11 @@
 	bool "Marvell Kirkwood"
 	select CPU_ARM926EJS
  
+config TARGET_DB_88F6820_GP
+	bool "Support DB-88F6820-GP"
+	select CPU_V7
+	select SUPPORT_SPL
+
 config TARGET_DB_MV784MP_GP
 	bool "Support db-mv784mp-gp"
 	select CPU_V7
@@ -850,6 +855,7 @@
 source "board/BuR/tseries/Kconfig"
 source "board/CarMediaLab/flea3/Kconfig"
 source "board/Marvell/aspenite/Kconfig"
+source "board/Marvell/db-88f6820-gp/Kconfig"
 source "board/Marvell/db-mv784mp-gp/Kconfig"
 source "board/Marvell/gplugd/Kconfig"
 source "board/altera/socfpga/Kconfig"
+if TARGET_DB_88F6820_GP
+
+config SYS_BOARD
+	default "db-88f6820-gp"
+
+config SYS_VENDOR
+	default "Marvell"
+
+config SYS_SOC
+	default "mvebu"
+
+config SYS_CONFIG_NAME
+	default "db-88f6820-gp"
+
+endif
+#
+# Copyright (C) 2015 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= db-88f6820-gp.o
+--------
+WARNING:
+--------
+This file should contain the bin_hdr generated by the original Marvell
+U-Boot implementation. As this is currently not included in this
+U-Boot version, we have added this placeholder, so that the U-Boot
+image can be generated without errors.
+
+If you have a known to be working bin_hdr for your board, then you
+just need to replace this text file here with the binary header
+and recompile U-Boot.
+
+In a few weeks, mainline U-Boot will get support to generate the
+bin_hdr with the DDR training code itself. By implementing this code
+as SPL U-Boot. Then this file will not be needed any more and will
+get removed.
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define BIT(nr)				(1UL << (nr))
+
+#define ETH_PHY_CTRL_REG		0
+#define ETH_PHY_CTRL_POWER_DOWN_BIT	11
+#define ETH_PHY_CTRL_POWER_DOWN_MASK	(1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
+
+/*
+ * Those values and defines are taken from the Marvell U-Boot version
+ * "u-boot-2013.01-2014_T3.0"
+ */
+#define DB_GP_88F68XX_GPP_OUT_ENA_LOW					\
+	(~(BIT(1)  | BIT(4)  | BIT(6)  | BIT(7)  | BIT(8)  | BIT(9)  |	\
+	   BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) |	\
+	   BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
+#define DB_GP_88F68XX_GPP_OUT_ENA_MID					\
+	(~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) |	\
+	   BIT(16) | BIT(17) | BIT(18)))
+
+#define DB_GP_88F68XX_GPP_OUT_VAL_LOW	0x0
+#define DB_GP_88F68XX_GPP_OUT_VAL_MID	0x0
+#define DB_GP_88F68XX_GPP_POL_LOW	0x0
+#define DB_GP_88F68XX_GPP_POL_MID	0x0
+
+/* IO expander on Marvell GP board includes e.g. fan enabling */
+struct marvell_io_exp {
+	u8 chip;
+	u8 addr;
+	u8 val;
+};
+
+static struct marvell_io_exp io_exp[] = {
+	{ 0x20, 6, 0x20 }, /* Configuration registers: Bit on --> Input bits */
+	{ 0x20, 7, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
+	{ 0x20, 2, 0x1D }, /* Output Data, register#0 */
+	{ 0x20, 3, 0x18 }, /* Output Data, register#1 */
+	{ 0x21, 6, 0xC3 }, /* Configuration registers: Bit on --> Input bits  */
+	{ 0x21, 7, 0x31 }, /* Configuration registers: Bit on --> Input bits  */
+	{ 0x21, 2, 0x08 }, /* Output Data, register#0 */
+	{ 0x21, 3, 0xC0 }  /* Output Data, register#1 */
+};
+
+int board_early_init_f(void)
+{
+	/* Configure MPP */
+	writel(0x11111111, MVEBU_MPP_BASE + 0x00);
+	writel(0x11111111, MVEBU_MPP_BASE + 0x04);
+	writel(0x11244011, MVEBU_MPP_BASE + 0x08);
+	writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
+	writel(0x22200002, MVEBU_MPP_BASE + 0x10);
+	writel(0x30042022, MVEBU_MPP_BASE + 0x14);
+	writel(0x55550555, MVEBU_MPP_BASE + 0x18);
+	writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
+
+	/* Set GPP Out value */
+	writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+	writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+
+	/* Set GPP Polarity */
+	writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+	writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
+
+	/* Set GPP Out Enable */
+	writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+	writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	int i;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	/* Init I2C IO expanders */
+	for (i = 0; i < ARRAY_SIZE(io_exp); i++)
+		i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Marvell DB-88F6820-GP\n");
+
+	return 0;
+}
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+
+# Armada XP uses version 1 image format
+VERSION		1
+
+# Boot Media configurations
+BOOT_FROM	spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY board/Marvell/db-88f6820-gp/binary.0 0000005b 00000068
+CONFIG_ARM=y
+CONFIG_TARGET_DB_88F6820_GP=y
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_DB_88F6820_GP_H
+#define _CONFIG_DB_88F6820_GP_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_ARMADA_XP		/* SOC Family Name */
+#define CONFIG_DB_88F6820_GP		/* Board target name for DDR training */
+
+#define CONFIG_SYS_L2_PL310
+
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+#define	CONFIG_SYS_TEXT_BASE	0x04000000
+#define CONFIG_SYS_TCLK		250000000	/* 250MHz */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_TFTPPUT
+#define CONFIG_CMD_TIME
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MVTWSI
+#define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
+#define CONFIG_SYS_I2C_SLAVE		0x0
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* SPI NOR flash default params, used by sf commands */
+#define CONFIG_SF_DEFAULT_SPEED		1000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
+#define CONFIG_SPI_FLASH_STMICRO
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
+#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE		(256 << 10) /* 256KiB sectors */
+
+#define CONFIG_PHY_MARVELL		/* there is a marvell phy */
+#define CONFIG_PHY_ADDR			{ 1, 0 }
+#define CONFIG_SYS_NETA_INTERFACE_TYPE	PHY_INTERFACE_MODE_RGMII
+#define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup */
+#define CONFIG_SYS_ALT_MEMTEST
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+#endif /* _CONFIG_DB_88F6820_GP_H */
...	...	@@ -102,6 +102,11 @@
102	102	bool "Marvell Kirkwood"
103	103	select CPU_ARM926EJS
104	104
	105	+config TARGET_DB_88F6820_GP
	106	+ bool "Support DB-88F6820-GP"
	107	+ select CPU_V7
	108	+ select SUPPORT_SPL
	109	+
105	110	config TARGET_DB_MV784MP_GP
106	111	bool "Support db-mv784mp-gp"
107	112	select CPU_V7
...	...	@@ -850,6 +855,7 @@
850	855	source "board/BuR/tseries/Kconfig"
851	856	source "board/CarMediaLab/flea3/Kconfig"
852	857	source "board/Marvell/aspenite/Kconfig"
	858	+source "board/Marvell/db-88f6820-gp/Kconfig"
853	859	source "board/Marvell/db-mv784mp-gp/Kconfig"
854	860	source "board/Marvell/gplugd/Kconfig"
855	861	source "board/altera/socfpga/Kconfig"
	1	+if TARGET_DB_88F6820_GP
	2	+
	3	+config SYS_BOARD
	4	+ default "db-88f6820-gp"
	5	+
	6	+config SYS_VENDOR
	7	+ default "Marvell"
	8	+
	9	+config SYS_SOC
	10	+ default "mvebu"
	11	+
	12	+config SYS_CONFIG_NAME
	13	+ default "db-88f6820-gp"
	14	+
	15	+endif
	1	+#
	2	+# Copyright (C) 2015 Stefan Roese <sr@denx.de>
	3	+#
	4	+# SPDX-License-Identifier: GPL-2.0+
	5	+#
	6	+
	7	+obj-y := db-88f6820-gp.o
	1	+--------
	2	+WARNING:
	3	+--------
	4	+This file should contain the bin_hdr generated by the original Marvell
	5	+U-Boot implementation. As this is currently not included in this
	6	+U-Boot version, we have added this placeholder, so that the U-Boot
	7	+image can be generated without errors.
	8	+
	9	+If you have a known to be working bin_hdr for your board, then you
	10	+just need to replace this text file here with the binary header
	11	+and recompile U-Boot.
	12	+
	13	+In a few weeks, mainline U-Boot will get support to generate the
	14	+bin_hdr with the DDR training code itself. By implementing this code
	15	+as SPL U-Boot. Then this file will not be needed any more and will
	16	+get removed.
	1	+/*
	2	+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
	3	+ *
	4	+ * SPDX-License-Identifier: GPL-2.0+
	5	+ */
	6	+
	7	+#include <common.h>
	8	+#include <i2c.h>
	9	+#include <miiphy.h>
	10	+#include <asm/io.h>
	11	+#include <asm/arch/cpu.h>
	12	+#include <asm/arch/soc.h>
	13	+
	14	+DECLARE_GLOBAL_DATA_PTR;
	15	+
	16	+#define BIT(nr) (1UL << (nr))
	17	+
	18	+#define ETH_PHY_CTRL_REG 0
	19	+#define ETH_PHY_CTRL_POWER_DOWN_BIT 11
	20	+#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
	21	+
	22	+/*
	23	+ * Those values and defines are taken from the Marvell U-Boot version
	24	+ * "u-boot-2013.01-2014_T3.0"
	25	+ */
	26	+#define DB_GP_88F68XX_GPP_OUT_ENA_LOW \
	27	+ (~(BIT(1) \| BIT(4) \| BIT(6) \| BIT(7) \| BIT(8) \| BIT(9) \| \
	28	+ BIT(10) \| BIT(11) \| BIT(19) \| BIT(22) \| BIT(23) \| BIT(25) \| \
	29	+ BIT(26) \| BIT(27) \| BIT(29) \| BIT(30) \| BIT(31)))
	30	+#define DB_GP_88F68XX_GPP_OUT_ENA_MID \
	31	+ (~(BIT(0) \| BIT(1) \| BIT(2) \| BIT(3) \| BIT(4) \| BIT(15) \| \
	32	+ BIT(16) \| BIT(17) \| BIT(18)))
	33	+
	34	+#define DB_GP_88F68XX_GPP_OUT_VAL_LOW 0x0
	35	+#define DB_GP_88F68XX_GPP_OUT_VAL_MID 0x0
	36	+#define DB_GP_88F68XX_GPP_POL_LOW 0x0
	37	+#define DB_GP_88F68XX_GPP_POL_MID 0x0
	38	+
	39	+/* IO expander on Marvell GP board includes e.g. fan enabling */
	40	+struct marvell_io_exp {
	41	+ u8 chip;
	42	+ u8 addr;
	43	+ u8 val;
	44	+};
	45	+
	46	+static struct marvell_io_exp io_exp[] = {
	47	+ { 0x20, 6, 0x20 }, /* Configuration registers: Bit on --> Input bits */
	48	+ { 0x20, 7, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
	49	+ { 0x20, 2, 0x1D }, /* Output Data, register#0 */
	50	+ { 0x20, 3, 0x18 }, /* Output Data, register#1 */
	51	+ { 0x21, 6, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
	52	+ { 0x21, 7, 0x31 }, /* Configuration registers: Bit on --> Input bits */
	53	+ { 0x21, 2, 0x08 }, /* Output Data, register#0 */
	54	+ { 0x21, 3, 0xC0 } /* Output Data, register#1 */
	55	+};
	56	+
	57	+int board_early_init_f(void)
	58	+{
	59	+ /* Configure MPP */
	60	+ writel(0x11111111, MVEBU_MPP_BASE + 0x00);
	61	+ writel(0x11111111, MVEBU_MPP_BASE + 0x04);
	62	+ writel(0x11244011, MVEBU_MPP_BASE + 0x08);
	63	+ writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
	64	+ writel(0x22200002, MVEBU_MPP_BASE + 0x10);
	65	+ writel(0x30042022, MVEBU_MPP_BASE + 0x14);
	66	+ writel(0x55550555, MVEBU_MPP_BASE + 0x18);
	67	+ writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
	68	+
	69	+ /* Set GPP Out value */
	70	+ writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
	71	+ writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
	72	+
	73	+ /* Set GPP Polarity */
	74	+ writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
	75	+ writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
	76	+
	77	+ /* Set GPP Out Enable */
	78	+ writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
	79	+ writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
	80	+
	81	+ return 0;
	82	+}
	83	+
	84	+int board_init(void)
	85	+{
	86	+ int i;
	87	+
	88	+ /* adress of boot parameters */
	89	+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
	90	+
	91	+ /* Init I2C IO expanders */
	92	+ for (i = 0; i < ARRAY_SIZE(io_exp); i++)
	93	+ i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1);
	94	+
	95	+ return 0;
	96	+}
	97	+
	98	+int checkboard(void)
	99	+{
	100	+ puts("Board: Marvell DB-88F6820-GP\n");
	101	+
	102	+ return 0;
	103	+}
	1	+#
	2	+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
	3	+#
	4	+
	5	+# Armada XP uses version 1 image format
	6	+VERSION 1
	7	+
	8	+# Boot Media configurations
	9	+BOOT_FROM spi
	10	+
	11	+# Binary Header (bin_hdr) with DDR3 training code
	12	+BINARY board/Marvell/db-88f6820-gp/binary.0 0000005b 00000068
	1	+/*
	2	+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
	3	+ *
	4	+ * SPDX-License-Identifier: GPL-2.0+
	5	+ */
	6	+
	7	+#ifndef _CONFIG_DB_88F6820_GP_H
	8	+#define _CONFIG_DB_88F6820_GP_H
	9	+
	10	+/*
	11	+ * High Level Configuration Options (easy to change)
	12	+ */
	13	+#define CONFIG_ARMADA_XP /* SOC Family Name */
	14	+#define CONFIG_DB_88F6820_GP /* Board target name for DDR training */
	15	+
	16	+#define CONFIG_SYS_L2_PL310
	17	+
	18	+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
	19	+#define CONFIG_SYS_GENERIC_BOARD
	20	+#define CONFIG_DISPLAY_BOARDINFO_LATE
	21	+
	22	+#define CONFIG_SYS_TEXT_BASE 0x04000000
	23	+#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
	24	+
	25	+/*
	26	+ * Commands configuration
	27	+ */
	28	+#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
	29	+#include <config_cmd_default.h>
	30	+#define CONFIG_CMD_CACHE
	31	+#define CONFIG_CMD_DHCP
	32	+#define CONFIG_CMD_ENV
	33	+#define CONFIG_CMD_I2C
	34	+#define CONFIG_CMD_PING
	35	+#define CONFIG_CMD_SF
	36	+#define CONFIG_CMD_SPI
	37	+#define CONFIG_CMD_TFTPPUT
	38	+#define CONFIG_CMD_TIME
	39	+
	40	+/* I2C */
	41	+#define CONFIG_SYS_I2C
	42	+#define CONFIG_SYS_I2C_MVTWSI
	43	+#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
	44	+#define CONFIG_SYS_I2C_SLAVE 0x0
	45	+#define CONFIG_SYS_I2C_SPEED 100000
	46	+
	47	+/* SPI NOR flash default params, used by sf commands */
	48	+#define CONFIG_SF_DEFAULT_SPEED 1000000
	49	+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
	50	+#define CONFIG_SPI_FLASH_STMICRO
	51	+
	52	+/* Environment in SPI NOR flash */
	53	+#define CONFIG_ENV_IS_IN_SPI_FLASH
	54	+#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
	55	+#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
	56	+#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
	57	+
	58	+#define CONFIG_PHY_MARVELL /* there is a marvell phy */
	59	+#define CONFIG_PHY_ADDR { 1, 0 }
	60	+#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII
	61	+#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
	62	+
	63	+#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
	64	+#define CONFIG_SYS_ALT_MEMTEST
	65	+
	66	+/*
	67	+ * mv-common.h should be defined after CMD configs since it used them
	68	+ * to enable certain macros
	69	+ */
	70	+#include "mv-common.h"
	71	+
	72	+#endif /* _CONFIG_DB_88F6820_GP_H */