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Commit 2bd7460e9283ec98565189b3cdbcfb2bcdcdd635

Authored by Anton Vorontsov
Committed by Kim Phillips
1 parent 453316a2a1
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

83xx: initialize serdes for MPC837XRDB boards 

On the MPC8377ERDB: 2 SATA and 2 PCI-E.
On the MPC8378ERDB: 2 PCI-E
On the MPC8379ERDB: 4 SATA

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>

Showing 2 changed files with 43 additions and 0 deletions Inline Diff

board/freescale/mpc837xerdb/mpc837xerdb.c
Diff comments   View file @ 2bd7460
1 /* 1 /*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 * Kevin Lam <kevin.lam@freescale.com> 3 * Kevin Lam <kevin.lam@freescale.com>
4 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com> 4 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
5 * 5 *
6 * See file CREDITS for list of people who contributed to this 6 * See file CREDITS for list of people who contributed to this
7 * project. 7 * project.
8 * 8 *
9 * This program is free software; you can redistribute it and/or 9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as 10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of 11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version. 12 * the License, or (at your option) any later version.
13 */ 13 */
14 14
15 #include <common.h> 15 #include <common.h>
16 #include <i2c.h> 16 #include <i2c.h>
17 #include <asm/io.h> 17 #include <asm/io.h>
18 #include <asm/fsl_serdes.h>
18 #include <spd_sdram.h> 19 #include <spd_sdram.h>
19 #include <vsc7385.h> 20 #include <vsc7385.h>
20 21
21 22
22 #if defined(CFG_DRAM_TEST) 23 #if defined(CFG_DRAM_TEST)
23 int 24 int
24 testdram(void) 25 testdram(void)
25 { 26 {
26 uint *pstart = (uint *) CFG_MEMTEST_START; 27 uint *pstart = (uint *) CFG_MEMTEST_START;
27 uint *pend = (uint *) CFG_MEMTEST_END; 28 uint *pend = (uint *) CFG_MEMTEST_END;
28 uint *p; 29 uint *p;
29 30
30 printf("Testing DRAM from 0x%08x to 0x%08x\n", 31 printf("Testing DRAM from 0x%08x to 0x%08x\n",
31 CFG_MEMTEST_START, 32 CFG_MEMTEST_START,
32 CFG_MEMTEST_END); 33 CFG_MEMTEST_END);
33 34
34 printf("DRAM test phase 1:\n"); 35 printf("DRAM test phase 1:\n");
35 for (p = pstart; p < pend; p++) 36 for (p = pstart; p < pend; p++)
36 *p = 0xaaaaaaaa; 37 *p = 0xaaaaaaaa;
37 38
38 for (p = pstart; p < pend; p++) { 39 for (p = pstart; p < pend; p++) {
39 if (*p != 0xaaaaaaaa) { 40 if (*p != 0xaaaaaaaa) {
40 printf("DRAM test fails at: %08x\n", (uint) p); 41 printf("DRAM test fails at: %08x\n", (uint) p);
41 return 1; 42 return 1;
42 } 43 }
43 } 44 }
44 45
45 printf("DRAM test phase 2:\n"); 46 printf("DRAM test phase 2:\n");
46 for (p = pstart; p < pend; p++) 47 for (p = pstart; p < pend; p++)
47 *p = 0x55555555; 48 *p = 0x55555555;
48 49
49 for (p = pstart; p < pend; p++) { 50 for (p = pstart; p < pend; p++) {
50 if (*p != 0x55555555) { 51 if (*p != 0x55555555) {
51 printf("DRAM test fails at: %08x\n", (uint) p); 52 printf("DRAM test fails at: %08x\n", (uint) p);
52 return 1; 53 return 1;
53 } 54 }
54 } 55 }
55 56
56 printf("DRAM test passed.\n"); 57 printf("DRAM test passed.\n");
57 return 0; 58 return 0;
58 } 59 }
59 #endif 60 #endif
60 61
61 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) 62 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
62 void ddr_enable_ecc(unsigned int dram_size); 63 void ddr_enable_ecc(unsigned int dram_size);
63 #endif 64 #endif
64 int fixed_sdram(void); 65 int fixed_sdram(void);
65 66
66 long int initdram(int board_type) 67 long int initdram(int board_type)
67 { 68 {
68 immap_t *im = (immap_t *) CFG_IMMR; 69 immap_t *im = (immap_t *) CFG_IMMR;
69 u32 msize = 0; 70 u32 msize = 0;
70 71
71 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) 72 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
72 return -1; 73 return -1;
73 74
74 #if defined(CONFIG_SPD_EEPROM) 75 #if defined(CONFIG_SPD_EEPROM)
75 msize = spd_sdram(); 76 msize = spd_sdram();
76 #else 77 #else
77 msize = fixed_sdram(); 78 msize = fixed_sdram();
78 #endif 79 #endif
79 80
80 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) 81 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
81 /* Initialize DDR ECC byte */ 82 /* Initialize DDR ECC byte */
82 ddr_enable_ecc(msize * 1024 * 1024); 83 ddr_enable_ecc(msize * 1024 * 1024);
83 #endif 84 #endif
84 /* return total bus DDR size(bytes) */ 85 /* return total bus DDR size(bytes) */
85 return (msize * 1024 * 1024); 86 return (msize * 1024 * 1024);
86 } 87 }
87 88
88 #if !defined(CONFIG_SPD_EEPROM) 89 #if !defined(CONFIG_SPD_EEPROM)
89 /************************************************************************* 90 /*************************************************************************
90 * fixed sdram init -- doesn't use serial presence detect. 91 * fixed sdram init -- doesn't use serial presence detect.
91 ************************************************************************/ 92 ************************************************************************/
92 int fixed_sdram(void) 93 int fixed_sdram(void)
93 { 94 {
94 immap_t *im = (immap_t *) CFG_IMMR; 95 immap_t *im = (immap_t *) CFG_IMMR;
95 u32 msize = CFG_DDR_SIZE * 1024 * 1024; 96 u32 msize = CFG_DDR_SIZE * 1024 * 1024;
96 u32 msize_log2 = __ilog2(msize); 97 u32 msize_log2 = __ilog2(msize);
97 98
98 im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12; 99 im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
99 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); 100 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
100 101
101 im->sysconf.ddrcdr = CFG_DDRCDR_VALUE; 102 im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
102 udelay(50000); 103 udelay(50000);
103 104
104 im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL; 105 im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
105 udelay(1000); 106 udelay(1000);
106 107
107 im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; 108 im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
108 im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; 109 im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
109 udelay(1000); 110 udelay(1000);
110 111
111 im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; 112 im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
112 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; 113 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
113 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; 114 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
114 im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; 115 im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
115 im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; 116 im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
116 im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; 117 im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
117 im->ddr.sdram_mode = CFG_DDR_MODE; 118 im->ddr.sdram_mode = CFG_DDR_MODE;
118 im->ddr.sdram_mode2 = CFG_DDR_MODE2; 119 im->ddr.sdram_mode2 = CFG_DDR_MODE2;
119 im->ddr.sdram_interval = CFG_DDR_INTERVAL; 120 im->ddr.sdram_interval = CFG_DDR_INTERVAL;
120 sync(); 121 sync();
121 udelay(1000); 122 udelay(1000);
122 123
123 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 124 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
124 udelay(2000); 125 udelay(2000);
125 return CFG_DDR_SIZE; 126 return CFG_DDR_SIZE;
126 } 127 }
127 #endif /*!CFG_SPD_EEPROM */ 128 #endif /*!CFG_SPD_EEPROM */
128 129
129 int checkboard(void) 130 int checkboard(void)
130 { 131 {
131 puts("Board: Freescale MPC837xERDB\n"); 132 puts("Board: Freescale MPC837xERDB\n");
133 return 0;
134 }
135
136 int board_early_init_f(void)
137 {
138 #ifdef CONFIG_FSL_SERDES
139 immap_t *immr = (immap_t *)CFG_IMMR;
140 u32 spridr = in_be32(&immr->sysconf.spridr);
141
142 /* we check only part num, and don't look for CPU revisions */
143 switch (spridr >> 16) {
144 case SPR_8379E_REV10 >> 16:
145 case SPR_8379_REV10 >> 16:
146 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
147 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
148 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
149 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
150 break;
151 case SPR_8378E_REV10 >> 16:
152 case SPR_8378_REV10 >> 16:
153 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
154 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
155 break;
156 case SPR_8377E_REV10 >> 16:
157 case SPR_8377_REV10 >> 16:
158 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
159 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
160 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
161 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
162 break;
163 default:
164 printf("serdes not configured: unknown CPU part number: "
165 "%04x\n", spridr >> 16);
166 break;
167 }
168 #endif /* CONFIG_FSL_SERDES */
132 return 0; 169 return 0;
133 } 170 }
134 171
135 /* 172 /*
136 * Miscellaneous late-boot configurations 173 * Miscellaneous late-boot configurations
137 * 174 *
138 * If a VSC7385 microcode image is present, then upload it. 175 * If a VSC7385 microcode image is present, then upload it.
139 */ 176 */
140 int misc_init_r(void) 177 int misc_init_r(void)
141 { 178 {
142 int rc = 0; 179 int rc = 0;
143 180
144 #ifdef CONFIG_VSC7385_IMAGE 181 #ifdef CONFIG_VSC7385_IMAGE
145 if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, 182 if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
146 CONFIG_VSC7385_IMAGE_SIZE)) { 183 CONFIG_VSC7385_IMAGE_SIZE)) {
147 puts("Failure uploading VSC7385 microcode.\n"); 184 puts("Failure uploading VSC7385 microcode.\n");
148 rc = 1; 185 rc = 1;
149 } 186 }
150 #endif 187 #endif
151 188
152 return rc; 189 return rc;
153 } 190 }
154 191
155 #if defined(CONFIG_OF_BOARD_SETUP) 192 #if defined(CONFIG_OF_BOARD_SETUP)
156 193
157 void ft_board_setup(void *blob, bd_t *bd) 194 void ft_board_setup(void *blob, bd_t *bd)
158 { 195 {
159 #ifdef CONFIG_PCI 196 #ifdef CONFIG_PCI
160 ft_pci_setup(blob, bd); 197 ft_pci_setup(blob, bd);
161 #endif 198 #endif
162 ft_cpu_setup(blob, bd); 199 ft_cpu_setup(blob, bd);
163 } 200 }
164 #endif /* CONFIG_OF_BOARD_SETUP */ 201 #endif /* CONFIG_OF_BOARD_SETUP */
165 202
include/configs/MPC837XERDB.h
Diff comments   View file @ 2bd7460
1 /* 1 /*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 * Kevin Lam <kevin.lam@freescale.com> 3 * Kevin Lam <kevin.lam@freescale.com>
4 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com> 4 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
5 * 5 *
6 * This program is free software; you can redistribute it and/or 6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as 7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of 8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version. 9 * the License, or (at your option) any later version.
10 * 10 *
11 * This program is distributed in the hope that it will be useful, 11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 * 15 *
16 * You should have received a copy of the GNU General Public License 16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software 17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA 19 * MA 02111-1307 USA
20 */ 20 */
21 21
22 #ifndef __CONFIG_H 22 #ifndef __CONFIG_H
23 #define __CONFIG_H 23 #define __CONFIG_H
24 24
25 /* 25 /*
26 * High Level Configuration Options 26 * High Level Configuration Options
27 */ 27 */
28 #define CONFIG_E300 1 /* E300 family */ 28 #define CONFIG_E300 1 /* E300 family */
29 #define CONFIG_MPC83XX 1 /* MPC83XX family */ 29 #define CONFIG_MPC83XX 1 /* MPC83XX family */
30 #define CONFIG_MPC837X 1 /* MPC837X CPU specific */ 30 #define CONFIG_MPC837X 1 /* MPC837X CPU specific */
31 #define CONFIG_MPC837XERDB 1 31 #define CONFIG_MPC837XERDB 1
32 32
33 #define CONFIG_PCI 1 33 #define CONFIG_PCI 1
34 34
35 #define CONFIG_BOARD_EARLY_INIT_F
35 #define CONFIG_MISC_INIT_R 36 #define CONFIG_MISC_INIT_R
36 37
37 /* 38 /*
38 * On-board devices 39 * On-board devices
39 */ 40 */
40 #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ 41 #define CONFIG_TSEC_ENET /* TSEC Ethernet support */
41 #define CONFIG_VSC7385_ENET 42 #define CONFIG_VSC7385_ENET
42 43
43 /* 44 /*
44 * System Clock Setup 45 * System Clock Setup
45 */ 46 */
46 #ifdef CONFIG_PCISLAVE 47 #ifdef CONFIG_PCISLAVE
47 #define CONFIG_83XX_PCICLK 66666667 /* in HZ */ 48 #define CONFIG_83XX_PCICLK 66666667 /* in HZ */
48 #else 49 #else
49 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 50 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */
50 #define CONFIG_83XX_GENERIC_PCI 1 51 #define CONFIG_83XX_GENERIC_PCI 1
51 #endif 52 #endif
52 53
53 #ifndef CONFIG_SYS_CLK_FREQ 54 #ifndef CONFIG_SYS_CLK_FREQ
54 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 55 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
55 #endif 56 #endif
56 57
57 /* 58 /*
58 * Hardware Reset Configuration Word 59 * Hardware Reset Configuration Word
59 */ 60 */
60 #define CFG_HRCW_LOW (\ 61 #define CFG_HRCW_LOW (\
61 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 62 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
62 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 63 HRCWL_DDR_TO_SCB_CLK_1X1 |\
63 HRCWL_SVCOD_DIV_2 |\ 64 HRCWL_SVCOD_DIV_2 |\
64 HRCWL_CSB_TO_CLKIN_5X1 |\ 65 HRCWL_CSB_TO_CLKIN_5X1 |\
65 HRCWL_CORE_TO_CSB_2X1) 66 HRCWL_CORE_TO_CSB_2X1)
66 67
67 #ifdef CONFIG_PCISLAVE 68 #ifdef CONFIG_PCISLAVE
68 #define CFG_HRCW_HIGH (\ 69 #define CFG_HRCW_HIGH (\
69 HRCWH_PCI_AGENT |\ 70 HRCWH_PCI_AGENT |\
70 HRCWH_PCI1_ARBITER_DISABLE |\ 71 HRCWH_PCI1_ARBITER_DISABLE |\
71 HRCWH_CORE_ENABLE |\ 72 HRCWH_CORE_ENABLE |\
72 HRCWH_FROM_0XFFF00100 |\ 73 HRCWH_FROM_0XFFF00100 |\
73 HRCWH_BOOTSEQ_DISABLE |\ 74 HRCWH_BOOTSEQ_DISABLE |\
74 HRCWH_SW_WATCHDOG_DISABLE |\ 75 HRCWH_SW_WATCHDOG_DISABLE |\
75 HRCWH_ROM_LOC_LOCAL_16BIT |\ 76 HRCWH_ROM_LOC_LOCAL_16BIT |\
76 HRCWH_RL_EXT_LEGACY |\ 77 HRCWH_RL_EXT_LEGACY |\
77 HRCWH_TSEC1M_IN_RGMII |\ 78 HRCWH_TSEC1M_IN_RGMII |\
78 HRCWH_TSEC2M_IN_RGMII |\ 79 HRCWH_TSEC2M_IN_RGMII |\
79 HRCWH_BIG_ENDIAN |\ 80 HRCWH_BIG_ENDIAN |\
80 HRCWH_LDP_CLEAR) 81 HRCWH_LDP_CLEAR)
81 #else 82 #else
82 #define CFG_HRCW_HIGH (\ 83 #define CFG_HRCW_HIGH (\
83 HRCWH_PCI_HOST |\ 84 HRCWH_PCI_HOST |\
84 HRCWH_PCI1_ARBITER_ENABLE |\ 85 HRCWH_PCI1_ARBITER_ENABLE |\
85 HRCWH_CORE_ENABLE |\ 86 HRCWH_CORE_ENABLE |\
86 HRCWH_FROM_0X00000100 |\ 87 HRCWH_FROM_0X00000100 |\
87 HRCWH_BOOTSEQ_DISABLE |\ 88 HRCWH_BOOTSEQ_DISABLE |\
88 HRCWH_SW_WATCHDOG_DISABLE |\ 89 HRCWH_SW_WATCHDOG_DISABLE |\
89 HRCWH_ROM_LOC_LOCAL_16BIT |\ 90 HRCWH_ROM_LOC_LOCAL_16BIT |\
90 HRCWH_RL_EXT_LEGACY |\ 91 HRCWH_RL_EXT_LEGACY |\
91 HRCWH_TSEC1M_IN_RGMII |\ 92 HRCWH_TSEC1M_IN_RGMII |\
92 HRCWH_TSEC2M_IN_RGMII |\ 93 HRCWH_TSEC2M_IN_RGMII |\
93 HRCWH_BIG_ENDIAN |\ 94 HRCWH_BIG_ENDIAN |\
94 HRCWH_LDP_CLEAR) 95 HRCWH_LDP_CLEAR)
95 #endif 96 #endif
96 97
97 /* System performance - define the value i.e. CFG_XXX 98 /* System performance - define the value i.e. CFG_XXX
98 */ 99 */
99 100
100 /* Arbiter Configuration Register */ 101 /* Arbiter Configuration Register */
101 #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 102 #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
102 #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 103 #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
103 104
104 /* System Priority Control Regsiter */ 105 /* System Priority Control Regsiter */
105 #define CFG_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */ 106 #define CFG_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */
106 107
107 /* System Clock Configuration Register */ 108 /* System Clock Configuration Register */
108 #define CFG_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */ 109 #define CFG_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
109 #define CFG_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */ 110 #define CFG_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
110 #define CFG_SCCR_SATACM SCCR_SATACM_1 /* SATA1-4 clock mode (0-3) */ 111 #define CFG_SCCR_SATACM SCCR_SATACM_1 /* SATA1-4 clock mode (0-3) */
111 112
112 /* 113 /*
113 * System IO Config 114 * System IO Config
114 */ 115 */
115 #define CFG_SICRH 0x08200000 116 #define CFG_SICRH 0x08200000
116 #define CFG_SICRL 0x00000000 117 #define CFG_SICRL 0x00000000
117 118
118 /* 119 /*
119 * Output Buffer Impedance 120 * Output Buffer Impedance
120 */ 121 */
121 #define CFG_OBIR 0x30100000 122 #define CFG_OBIR 0x30100000
122 123
123 /* 124 /*
124 * IMMR new address 125 * IMMR new address
125 */ 126 */
126 #define CFG_IMMR 0xE0000000 127 #define CFG_IMMR 0xE0000000
127 128
128 /* 129 /*
129 * Device configurations 130 * Device configurations
130 */ 131 */
131 132
132 /* Vitesse 7385 */ 133 /* Vitesse 7385 */
133 134
134 #ifdef CONFIG_VSC7385_ENET 135 #ifdef CONFIG_VSC7385_ENET
135 136
136 #define CONFIG_TSEC2 137 #define CONFIG_TSEC2
137 138
138 /* The flash address and size of the VSC7385 firmware image */ 139 /* The flash address and size of the VSC7385 firmware image */
139 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 140 #define CONFIG_VSC7385_IMAGE 0xFE7FE000
140 #define CONFIG_VSC7385_IMAGE_SIZE 8192 141 #define CONFIG_VSC7385_IMAGE_SIZE 8192
141 142
142 #endif 143 #endif
143 144
144 /* 145 /*
145 * DDR Setup 146 * DDR Setup
146 */ 147 */
147 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ 148 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory */
148 #define CFG_SDRAM_BASE CFG_DDR_BASE 149 #define CFG_SDRAM_BASE CFG_DDR_BASE
149 #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE 150 #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
150 #define CFG_DDR_SDRAM_CLK_CNTL 0x03000000 151 #define CFG_DDR_SDRAM_CLK_CNTL 0x03000000
151 #define CFG_83XX_DDR_USES_CS0 152 #define CFG_83XX_DDR_USES_CS0
152 153
153 #define CFG_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) 154 #define CFG_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
154 155
155 #undef CONFIG_DDR_ECC /* support DDR ECC function */ 156 #undef CONFIG_DDR_ECC /* support DDR ECC function */
156 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ 157 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
157 158
158 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ 159 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
159 160
160 /* 161 /*
161 * Manually set up DDR parameters 162 * Manually set up DDR parameters
162 */ 163 */
163 #define CFG_DDR_SIZE 256 /* MB */ 164 #define CFG_DDR_SIZE 256 /* MB */
164 #define CFG_DDR_CS0_BNDS 0x0000000f 165 #define CFG_DDR_CS0_BNDS 0x0000000f
165 #define CFG_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ODT_WR_ACS \ 166 #define CFG_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ODT_WR_ACS \
166 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 167 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
167 168
168 #define CFG_DDR_TIMING_3 0x00000000 169 #define CFG_DDR_TIMING_3 0x00000000
169 #define CFG_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 170 #define CFG_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
170 | (0 << TIMING_CFG0_WRT_SHIFT) \ 171 | (0 << TIMING_CFG0_WRT_SHIFT) \
171 | (0 << TIMING_CFG0_RRT_SHIFT) \ 172 | (0 << TIMING_CFG0_RRT_SHIFT) \
172 | (0 << TIMING_CFG0_WWT_SHIFT) \ 173 | (0 << TIMING_CFG0_WWT_SHIFT) \
173 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 174 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
174 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 175 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
175 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 176 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
176 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 177 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
177 /* 0x00220802 */ 178 /* 0x00220802 */
178 /* 0x00260802 */ /* DDR400 */ 179 /* 0x00260802 */ /* DDR400 */
179 #define CFG_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 180 #define CFG_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
180 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 181 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
181 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 182 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
182 | (7 << TIMING_CFG1_CASLAT_SHIFT) \ 183 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
183 | (13 << TIMING_CFG1_REFREC_SHIFT) \ 184 | (13 << TIMING_CFG1_REFREC_SHIFT) \
184 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 185 | (3 << TIMING_CFG1_WRREC_SHIFT) \
185 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 186 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
186 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 187 | (2 << TIMING_CFG1_WRTORD_SHIFT))
187 /* 0x3935d322 */ 188 /* 0x3935d322 */
188 /* 0x3937d322 */ 189 /* 0x3937d322 */
189 #define CFG_DDR_TIMING_2 0x02984cc8 190 #define CFG_DDR_TIMING_2 0x02984cc8
190 191
191 #define CFG_DDR_INTERVAL ((1545 << SDRAM_INTERVAL_REFINT_SHIFT) \ 192 #define CFG_DDR_INTERVAL ((1545 << SDRAM_INTERVAL_REFINT_SHIFT) \
192 | (256 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 193 | (256 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
193 /* 0x06090100 */ 194 /* 0x06090100 */
194 195
195 #if defined(CONFIG_DDR_2T_TIMING) 196 #if defined(CONFIG_DDR_2T_TIMING)
196 #define CFG_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 197 #define CFG_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
197 | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \ 198 | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
198 | SDRAM_CFG_2T_EN \ 199 | SDRAM_CFG_2T_EN \
199 | SDRAM_CFG_DBW_32) 200 | SDRAM_CFG_DBW_32)
200 #else 201 #else
201 #define CFG_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 202 #define CFG_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
202 | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT) 203 | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT)
203 /* 0x43000000 */ 204 /* 0x43000000 */
204 #endif 205 #endif
205 #define CFG_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ 206 #define CFG_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
206 #define CFG_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ 207 #define CFG_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
207 | (0x0442 << SDRAM_MODE_SD_SHIFT)) 208 | (0x0442 << SDRAM_MODE_SD_SHIFT))
208 /* 0x04400442 */ /* DDR400 */ 209 /* 0x04400442 */ /* DDR400 */
209 #define CFG_DDR_MODE2 0x00000000; 210 #define CFG_DDR_MODE2 0x00000000;
210 211
211 /* 212 /*
212 * Memory test 213 * Memory test
213 */ 214 */
214 #undef CFG_DRAM_TEST /* memory test, takes time */ 215 #undef CFG_DRAM_TEST /* memory test, takes time */
215 #define CFG_MEMTEST_START 0x00040000 /* memtest region */ 216 #define CFG_MEMTEST_START 0x00040000 /* memtest region */
216 #define CFG_MEMTEST_END 0x0ef70010 217 #define CFG_MEMTEST_END 0x0ef70010
217 218
218 /* 219 /*
219 * The reserved memory 220 * The reserved memory
220 */ 221 */
221 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 222 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
222 223
223 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 224 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
224 #define CFG_RAMBOOT 225 #define CFG_RAMBOOT
225 #else 226 #else
226 #undef CFG_RAMBOOT 227 #undef CFG_RAMBOOT
227 #endif 228 #endif
228 229
229 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 230 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
230 #define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 231 #define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
231 232
232 /* 233 /*
233 * Initial RAM Base Address Setup 234 * Initial RAM Base Address Setup
234 */ 235 */
235 #define CFG_INIT_RAM_LOCK 1 236 #define CFG_INIT_RAM_LOCK 1
236 #define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 237 #define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
237 #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ 238 #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */
238 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 239 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
239 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 240 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
240 241
241 /* 242 /*
242 * Local Bus Configuration & Clock Setup 243 * Local Bus Configuration & Clock Setup
243 */ 244 */
244 #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) 245 #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8)
245 #define CFG_LBC_LBCR 0x00000000 246 #define CFG_LBC_LBCR 0x00000000
246 247
247 /* 248 /*
248 * FLASH on the Local Bus 249 * FLASH on the Local Bus
249 */ 250 */
250 #define CFG_FLASH_CFI /* use the Common Flash Interface */ 251 #define CFG_FLASH_CFI /* use the Common Flash Interface */
251 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ 252 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
252 #define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ 253 #define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
253 #define CFG_FLASH_SIZE 8 /* max FLASH size is 32M */ 254 #define CFG_FLASH_SIZE 8 /* max FLASH size is 32M */
254 255
255 #define CFG_FLASH_EMPTY_INFO /* display empty sectors */ 256 #define CFG_FLASH_EMPTY_INFO /* display empty sectors */
256 #define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 257 #define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
257 258
258 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ 259 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
259 #define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ 260 #define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */
260 261
261 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ 262 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \
262 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ 263 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
263 BR_V) /* valid */ 264 BR_V) /* valid */
264 #define CFG_OR0_PRELIM (0xFF800000 /* 8 MByte */ \ 265 #define CFG_OR0_PRELIM (0xFF800000 /* 8 MByte */ \
265 | OR_GPCM_XACS \ 266 | OR_GPCM_XACS \
266 | OR_GPCM_SCY_9 \ 267 | OR_GPCM_SCY_9 \
267 | OR_GPCM_EHTR \ 268 | OR_GPCM_EHTR \
268 | OR_GPCM_EAD) 269 | OR_GPCM_EAD)
269 /* 0xFF806FF7 TODO SLOW 8 MB flash size */ 270 /* 0xFF806FF7 TODO SLOW 8 MB flash size */
270 271
271 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 272 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */
272 #define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ 273 #define CFG_MAX_FLASH_SECT 256 /* max sectors per device */
273 274
274 #undef CFG_FLASH_CHECKSUM 275 #undef CFG_FLASH_CHECKSUM
275 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 276 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
276 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 277 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
277 278
278 /* 279 /*
279 * NAND Flash on the Local Bus 280 * NAND Flash on the Local Bus
280 */ 281 */
281 #define CFG_NAND_BASE 0xE0600000 /* 0xE0600000 */ 282 #define CFG_NAND_BASE 0xE0600000 /* 0xE0600000 */
282 #define CFG_BR1_PRELIM (CFG_NAND_BASE | \ 283 #define CFG_BR1_PRELIM (CFG_NAND_BASE | \
283 (2 << BR_DECC_SHIFT) | /* Use HW ECC */ \ 284 (2 << BR_DECC_SHIFT) | /* Use HW ECC */ \
284 BR_PS_8 | /* Port Size = 8 bit */ \ 285 BR_PS_8 | /* Port Size = 8 bit */ \
285 BR_MS_FCM | /* MSEL = FCM */ \ 286 BR_MS_FCM | /* MSEL = FCM */ \
286 BR_V) /* valid */ 287 BR_V) /* valid */
287 #define CFG_OR1_PRELIM (0xFFFF8000 | /* length 32K */ \ 288 #define CFG_OR1_PRELIM (0xFFFF8000 | /* length 32K */ \
288 OR_FCM_CSCT | \ 289 OR_FCM_CSCT | \
289 OR_FCM_CST | \ 290 OR_FCM_CST | \
290 OR_FCM_CHT | \ 291 OR_FCM_CHT | \
291 OR_FCM_SCY_1 | \ 292 OR_FCM_SCY_1 | \
292 OR_FCM_TRLX | \ 293 OR_FCM_TRLX | \
293 OR_FCM_EHTR) 294 OR_FCM_EHTR)
294 #define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE 295 #define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE
295 #define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ 296 #define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
296 297
297 /* Vitesse 7385 */ 298 /* Vitesse 7385 */
298 299
299 #define CFG_VSC7385_BASE 0xF0000000 300 #define CFG_VSC7385_BASE 0xF0000000
300 301
301 #ifdef CONFIG_VSC7385_ENET 302 #ifdef CONFIG_VSC7385_ENET
302 303
303 #define CFG_BR2_PRELIM 0xf0000801 /* Base address */ 304 #define CFG_BR2_PRELIM 0xf0000801 /* Base address */
304 #define CFG_OR2_PRELIM 0xfffe09ff /* 128K bytes*/ 305 #define CFG_OR2_PRELIM 0xfffe09ff /* 128K bytes*/
305 #define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE /* Access Base */ 306 #define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE /* Access Base */
306 #define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access Size 128K */ 307 #define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access Size 128K */
307 308
308 #endif 309 #endif
309 310
310 /* 311 /*
311 * Serial Port 312 * Serial Port
312 */ 313 */
313 #define CONFIG_CONS_INDEX 1 314 #define CONFIG_CONS_INDEX 1
314 #undef CONFIG_SERIAL_SOFTWARE_FIFO 315 #undef CONFIG_SERIAL_SOFTWARE_FIFO
315 #define CFG_NS16550 316 #define CFG_NS16550
316 #define CFG_NS16550_SERIAL 317 #define CFG_NS16550_SERIAL
317 #define CFG_NS16550_REG_SIZE 1 318 #define CFG_NS16550_REG_SIZE 1
318 #define CFG_NS16550_CLK get_bus_freq(0) 319 #define CFG_NS16550_CLK get_bus_freq(0)
319 320
320 #define CFG_BAUDRATE_TABLE \ 321 #define CFG_BAUDRATE_TABLE \
321 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 322 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
322 323
323 #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) 324 #define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
324 #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) 325 #define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
326
327 /* SERDES */
328 #define CONFIG_FSL_SERDES
329 #define CONFIG_FSL_SERDES1 0xe3000
330 #define CONFIG_FSL_SERDES2 0xe3100
325 331
326 /* Use the HUSH parser */ 332 /* Use the HUSH parser */
327 #define CFG_HUSH_PARSER 333 #define CFG_HUSH_PARSER
328 #ifdef CFG_HUSH_PARSER 334 #ifdef CFG_HUSH_PARSER
329 #define CFG_PROMPT_HUSH_PS2 "> " 335 #define CFG_PROMPT_HUSH_PS2 "> "
330 #endif 336 #endif
331 337
332 /* Pass open firmware flat tree */ 338 /* Pass open firmware flat tree */
333 #define CONFIG_OF_LIBFDT 1 339 #define CONFIG_OF_LIBFDT 1
334 #define CONFIG_OF_BOARD_SETUP 1 340 #define CONFIG_OF_BOARD_SETUP 1
335 341
336 /* I2C */ 342 /* I2C */
337 #define CONFIG_HARD_I2C /* I2C with hardware support */ 343 #define CONFIG_HARD_I2C /* I2C with hardware support */
338 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 344 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
339 #define CONFIG_FSL_I2C 345 #define CONFIG_FSL_I2C
340 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 346 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
341 #define CFG_I2C_SLAVE 0x7F 347 #define CFG_I2C_SLAVE 0x7F
342 #define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */ 348 #define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */
343 #define CFG_I2C_OFFSET 0x3000 349 #define CFG_I2C_OFFSET 0x3000
344 #define CFG_I2C2_OFFSET 0x3100 350 #define CFG_I2C2_OFFSET 0x3100
345 351
346 /* 352 /*
347 * Config on-board RTC 353 * Config on-board RTC
348 */ 354 */
349 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 355 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
350 #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 356 #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
351 357
352 /* 358 /*
353 * General PCI 359 * General PCI
354 * Addresses are mapped 1-1. 360 * Addresses are mapped 1-1.
355 */ 361 */
356 #define CFG_PCI_MEM_BASE 0x80000000 362 #define CFG_PCI_MEM_BASE 0x80000000
357 #define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE 363 #define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE
358 #define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */ 364 #define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */
359 #define CFG_PCI_MMIO_BASE 0x90000000 365 #define CFG_PCI_MMIO_BASE 0x90000000
360 #define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE 366 #define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE
361 #define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ 367 #define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */
362 #define CFG_PCI_IO_BASE 0xE0300000 368 #define CFG_PCI_IO_BASE 0xE0300000
363 #define CFG_PCI_IO_PHYS 0xE0300000 369 #define CFG_PCI_IO_PHYS 0xE0300000
364 #define CFG_PCI_IO_SIZE 0x100000 /* 1M */ 370 #define CFG_PCI_IO_SIZE 0x100000 /* 1M */
365 371
366 #define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE 372 #define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE
367 #define CFG_PCI_SLV_MEM_BUS 0x00000000 373 #define CFG_PCI_SLV_MEM_BUS 0x00000000
368 #define CFG_PCI_SLV_MEM_SIZE 0x80000000 374 #define CFG_PCI_SLV_MEM_SIZE 0x80000000
369 375
370 #ifdef CONFIG_PCI 376 #ifdef CONFIG_PCI
371 #define CONFIG_NET_MULTI 377 #define CONFIG_NET_MULTI
372 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 378 #define CONFIG_PCI_PNP /* do pci plug-and-play */
373 379
374 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 380 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
375 #define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 381 #define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
376 #endif /* CONFIG_PCI */ 382 #endif /* CONFIG_PCI */
377 383
378 /* 384 /*
379 * TSEC 385 * TSEC
380 */ 386 */
381 #ifdef CONFIG_TSEC_ENET 387 #ifdef CONFIG_TSEC_ENET
382 388
383 #define CONFIG_NET_MULTI 389 #define CONFIG_NET_MULTI
384 #define CONFIG_GMII /* MII PHY management */ 390 #define CONFIG_GMII /* MII PHY management */
385 391
386 #define CONFIG_TSEC1 392 #define CONFIG_TSEC1
387 393
388 #ifdef CONFIG_TSEC1 394 #ifdef CONFIG_TSEC1
389 #define CONFIG_HAS_ETH0 395 #define CONFIG_HAS_ETH0
390 #define CONFIG_TSEC1_NAME "TSEC0" 396 #define CONFIG_TSEC1_NAME "TSEC0"
391 #define CFG_TSEC1_OFFSET 0x24000 397 #define CFG_TSEC1_OFFSET 0x24000
392 #define TSEC1_PHY_ADDR 2 398 #define TSEC1_PHY_ADDR 2
393 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 399 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
394 #define TSEC1_PHYIDX 0 400 #define TSEC1_PHYIDX 0
395 #endif 401 #endif
396 402
397 #ifdef CONFIG_TSEC2 403 #ifdef CONFIG_TSEC2
398 #define CONFIG_HAS_ETH1 404 #define CONFIG_HAS_ETH1
399 #define CONFIG_TSEC2_NAME "TSEC1" 405 #define CONFIG_TSEC2_NAME "TSEC1"
400 #define CFG_TSEC2_OFFSET 0x25000 406 #define CFG_TSEC2_OFFSET 0x25000
401 #define TSEC2_PHY_ADDR 0x1c 407 #define TSEC2_PHY_ADDR 0x1c
402 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 408 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
403 #define TSEC2_PHYIDX 0 409 #define TSEC2_PHYIDX 0
404 #endif 410 #endif
405 411
406 /* Options are: TSEC[0-1] */ 412 /* Options are: TSEC[0-1] */
407 #define CONFIG_ETHPRIME "TSEC0" 413 #define CONFIG_ETHPRIME "TSEC0"
408 414
409 #endif 415 #endif
410 416
411 /* 417 /*
412 * Environment 418 * Environment
413 */ 419 */
414 #ifndef CFG_RAMBOOT 420 #ifndef CFG_RAMBOOT
415 #define CFG_ENV_IS_IN_FLASH 1 421 #define CFG_ENV_IS_IN_FLASH 1
416 #define CFG_ENV_ADDR (CFG_MONITOR_BASE+CFG_MONITOR_LEN) 422 #define CFG_ENV_ADDR (CFG_MONITOR_BASE+CFG_MONITOR_LEN)
417 #define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */ 423 #define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */
418 #define CFG_ENV_SIZE 0x4000 424 #define CFG_ENV_SIZE 0x4000
419 #else 425 #else
420 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 426 #define CFG_NO_FLASH 1 /* Flash is not usable now */
421 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 427 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
422 #define CFG_ENV_ADDR (CFG_MONITOR_BASE-0x1000) 428 #define CFG_ENV_ADDR (CFG_MONITOR_BASE-0x1000)
423 #define CFG_ENV_SIZE 0x2000 429 #define CFG_ENV_SIZE 0x2000
424 #endif 430 #endif
425 431
426 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 432 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
427 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 433 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
428 434
429 /* 435 /*
430 * BOOTP options 436 * BOOTP options
431 */ 437 */
432 #define CONFIG_BOOTP_BOOTFILESIZE 438 #define CONFIG_BOOTP_BOOTFILESIZE
433 #define CONFIG_BOOTP_BOOTPATH 439 #define CONFIG_BOOTP_BOOTPATH
434 #define CONFIG_BOOTP_GATEWAY 440 #define CONFIG_BOOTP_GATEWAY
435 #define CONFIG_BOOTP_HOSTNAME 441 #define CONFIG_BOOTP_HOSTNAME
436 442
437 443
438 /* 444 /*
439 * Command line configuration. 445 * Command line configuration.
440 */ 446 */
441 #include <config_cmd_default.h> 447 #include <config_cmd_default.h>
442 448
443 #define CONFIG_CMD_PING 449 #define CONFIG_CMD_PING
444 #define CONFIG_CMD_I2C 450 #define CONFIG_CMD_I2C
445 #define CONFIG_CMD_MII 451 #define CONFIG_CMD_MII
446 #define CONFIG_CMD_DATE 452 #define CONFIG_CMD_DATE
447 453
448 #if defined(CONFIG_PCI) 454 #if defined(CONFIG_PCI)
449 #define CONFIG_CMD_PCI 455 #define CONFIG_CMD_PCI
450 #endif 456 #endif
451 457
452 #if defined(CFG_RAMBOOT) 458 #if defined(CFG_RAMBOOT)
453 #undef CONFIG_CMD_ENV 459 #undef CONFIG_CMD_ENV
454 #undef CONFIG_CMD_LOADS 460 #undef CONFIG_CMD_LOADS
455 #endif 461 #endif
456 462
457 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 463 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
458 464
459 #undef CONFIG_WATCHDOG /* watchdog disabled */ 465 #undef CONFIG_WATCHDOG /* watchdog disabled */
460 466
461 /* 467 /*
462 * Miscellaneous configurable options 468 * Miscellaneous configurable options
463 */ 469 */
464 #define CFG_LONGHELP /* undef to save memory */ 470 #define CFG_LONGHELP /* undef to save memory */
465 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 471 #define CFG_LOAD_ADDR 0x2000000 /* default load address */
466 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 472 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
467 473
468 #if defined(CONFIG_CMD_KGDB) 474 #if defined(CONFIG_CMD_KGDB)
469 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 475 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
470 #else 476 #else
471 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 477 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
472 #endif 478 #endif
473 479
474 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 480 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
475 #define CFG_MAXARGS 16 /* max number of command args */ 481 #define CFG_MAXARGS 16 /* max number of command args */
476 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 482 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
477 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 483 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
478 484
479 /* 485 /*
480 * For booting Linux, the board info and command line data 486 * For booting Linux, the board info and command line data
481 * have to be in the first 8 MB of memory, since this is 487 * have to be in the first 8 MB of memory, since this is
482 * the maximum mapped by the Linux kernel during initialization. 488 * the maximum mapped by the Linux kernel during initialization.
483 */ 489 */
484 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 490 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
485 491
486 /* 492 /*
487 * Core HID Setup 493 * Core HID Setup
488 */ 494 */
489 #define CFG_HID0_INIT 0x000000000 495 #define CFG_HID0_INIT 0x000000000
490 #define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK 496 #define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
491 #define CFG_HID2 HID2_HBE 497 #define CFG_HID2 HID2_HBE
492 498
493 /* 499 /*
494 * MMU Setup 500 * MMU Setup
495 */ 501 */
496 502
497 /* DDR: cache cacheable */ 503 /* DDR: cache cacheable */
498 #define CFG_SDRAM_LOWER CFG_SDRAM_BASE 504 #define CFG_SDRAM_LOWER CFG_SDRAM_BASE
499 #define CFG_SDRAM_UPPER (CFG_SDRAM_BASE + 0x10000000) 505 #define CFG_SDRAM_UPPER (CFG_SDRAM_BASE + 0x10000000)
500 506
501 #define CFG_IBAT0L (CFG_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE) 507 #define CFG_IBAT0L (CFG_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE)
502 #define CFG_IBAT0U (CFG_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP) 508 #define CFG_IBAT0U (CFG_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP)
503 #define CFG_DBAT0L CFG_IBAT0L 509 #define CFG_DBAT0L CFG_IBAT0L
504 #define CFG_DBAT0U CFG_IBAT0U 510 #define CFG_DBAT0U CFG_IBAT0U
505 511
506 #define CFG_IBAT1L (CFG_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE) 512 #define CFG_IBAT1L (CFG_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE)
507 #define CFG_IBAT1U (CFG_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP) 513 #define CFG_IBAT1U (CFG_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP)
508 #define CFG_DBAT1L CFG_IBAT1L 514 #define CFG_DBAT1L CFG_IBAT1L
509 #define CFG_DBAT1U CFG_IBAT1U 515 #define CFG_DBAT1U CFG_IBAT1U
510 516
511 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 517 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
512 #define CFG_IBAT2L (CFG_IMMR | BATL_PP_10 | \ 518 #define CFG_IBAT2L (CFG_IMMR | BATL_PP_10 | \
513 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 519 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
514 #define CFG_IBAT2U (CFG_IMMR | BATU_BL_8M | BATU_VS | BATU_VP) 520 #define CFG_IBAT2U (CFG_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
515 #define CFG_DBAT2L CFG_IBAT2L 521 #define CFG_DBAT2L CFG_IBAT2L
516 #define CFG_DBAT2U CFG_IBAT2U 522 #define CFG_DBAT2U CFG_IBAT2U
517 523
518 /* L2 Switch: cache-inhibit and guarded */ 524 /* L2 Switch: cache-inhibit and guarded */
519 #define CFG_IBAT3L (CFG_VSC7385_BASE | BATL_PP_10 | \ 525 #define CFG_IBAT3L (CFG_VSC7385_BASE | BATL_PP_10 | \
520 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 526 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
521 #define CFG_IBAT3U (CFG_VSC7385_BASE | BATU_BL_128K | BATU_VS | BATU_VP) 527 #define CFG_IBAT3U (CFG_VSC7385_BASE | BATU_BL_128K | BATU_VS | BATU_VP)
522 #define CFG_DBAT3L CFG_IBAT3L 528 #define CFG_DBAT3L CFG_IBAT3L
523 #define CFG_DBAT3U CFG_IBAT3U 529 #define CFG_DBAT3U CFG_IBAT3U
524 530
525 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 531 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
526 #define CFG_IBAT4L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 532 #define CFG_IBAT4L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
527 #define CFG_IBAT4U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) 533 #define CFG_IBAT4U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
528 #define CFG_DBAT4L (CFG_FLASH_BASE | BATL_PP_10 | \ 534 #define CFG_DBAT4L (CFG_FLASH_BASE | BATL_PP_10 | \
529 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 535 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
530 #define CFG_DBAT4U CFG_IBAT4U 536 #define CFG_DBAT4U CFG_IBAT4U
531 537
532 /* Stack in dcache: cacheable, no memory coherence */ 538 /* Stack in dcache: cacheable, no memory coherence */
533 #define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10) 539 #define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10)
534 #define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 540 #define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
535 #define CFG_DBAT5L CFG_IBAT5L 541 #define CFG_DBAT5L CFG_IBAT5L
536 #define CFG_DBAT5U CFG_IBAT5U 542 #define CFG_DBAT5U CFG_IBAT5U
537 543
538 #ifdef CONFIG_PCI 544 #ifdef CONFIG_PCI
539 /* PCI MEM space: cacheable */ 545 /* PCI MEM space: cacheable */
540 #define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) 546 #define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
541 #define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 547 #define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
542 #define CFG_DBAT6L CFG_IBAT6L 548 #define CFG_DBAT6L CFG_IBAT6L
543 #define CFG_DBAT6U CFG_IBAT6U 549 #define CFG_DBAT6U CFG_IBAT6U
544 /* PCI MMIO space: cache-inhibit and guarded */ 550 /* PCI MMIO space: cache-inhibit and guarded */
545 #define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \ 551 #define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
546 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 552 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
547 #define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 553 #define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
548 #define CFG_DBAT7L CFG_IBAT7L 554 #define CFG_DBAT7L CFG_IBAT7L
549 #define CFG_DBAT7U CFG_IBAT7U 555 #define CFG_DBAT7U CFG_IBAT7U
550 #else 556 #else
551 #define CFG_IBAT6L (0) 557 #define CFG_IBAT6L (0)
552 #define CFG_IBAT6U (0) 558 #define CFG_IBAT6U (0)
553 #define CFG_IBAT7L (0) 559 #define CFG_IBAT7L (0)
554 #define CFG_IBAT7U (0) 560 #define CFG_IBAT7U (0)
555 #define CFG_DBAT6L CFG_IBAT6L 561 #define CFG_DBAT6L CFG_IBAT6L
556 #define CFG_DBAT6U CFG_IBAT6U 562 #define CFG_DBAT6U CFG_IBAT6U
557 #define CFG_DBAT7L CFG_IBAT7L 563 #define CFG_DBAT7L CFG_IBAT7L
558 #define CFG_DBAT7U CFG_IBAT7U 564 #define CFG_DBAT7U CFG_IBAT7U
559 #endif 565 #endif
560 566
561 /* 567 /*
562 * Internal Definitions 568 * Internal Definitions
563 * 569 *
564 * Boot Flags 570 * Boot Flags
565 */ 571 */
566 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 572 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
567 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 573 #define BOOTFLAG_WARM 0x02 /* Software reboot */
568 574
569 #if defined(CONFIG_CMD_KGDB) 575 #if defined(CONFIG_CMD_KGDB)
570 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 576 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
571 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 577 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
572 #endif 578 #endif
573 579
574 /* 580 /*
575 * Environment Configuration 581 * Environment Configuration
576 */ 582 */
577 #define CONFIG_ENV_OVERWRITE 583 #define CONFIG_ENV_OVERWRITE
578 584
579 #ifdef CONFIG_HAS_ETH0 585 #ifdef CONFIG_HAS_ETH0
580 #define CONFIG_ETHADDR 00:04:9f:ef:04:01 586 #define CONFIG_ETHADDR 00:04:9f:ef:04:01
581 #endif 587 #endif
582 588
583 #ifdef CONFIG_HAS_ETH1 589 #ifdef CONFIG_HAS_ETH1
584 #define CONFIG_ETH1ADDR 00:04:9f:ef:04:02 590 #define CONFIG_ETH1ADDR 00:04:9f:ef:04:02
585 #endif 591 #endif
586 592
587 #define CONFIG_IPADDR 10.0.0.2 593 #define CONFIG_IPADDR 10.0.0.2
588 #define CONFIG_SERVERIP 10.0.0.1 594 #define CONFIG_SERVERIP 10.0.0.1
589 #define CONFIG_GATEWAYIP 10.0.0.1 595 #define CONFIG_GATEWAYIP 10.0.0.1
590 #define CONFIG_NETMASK 255.0.0.0 596 #define CONFIG_NETMASK 255.0.0.0
591 #define CONFIG_NETDEV eth1 597 #define CONFIG_NETDEV eth1
592 598
593 #define CONFIG_HOSTNAME mpc837x_rdb 599 #define CONFIG_HOSTNAME mpc837x_rdb
594 #define CONFIG_ROOTPATH /nfsroot 600 #define CONFIG_ROOTPATH /nfsroot
595 #define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot 601 #define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot
596 #define CONFIG_BOOTFILE uImage 602 #define CONFIG_BOOTFILE uImage
597 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 603 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
598 #define CONFIG_FDTFILE mpc8379_rdb.dtb 604 #define CONFIG_FDTFILE mpc8379_rdb.dtb
599 605
600 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 606 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
601 #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ 607 #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
602 #define CONFIG_BAUDRATE 115200 608 #define CONFIG_BAUDRATE 115200
603 609
604 #define XMK_STR(x) #x 610 #define XMK_STR(x) #x
605 #define MK_STR(x) XMK_STR(x) 611 #define MK_STR(x) XMK_STR(x)
606 612
607 #define CONFIG_EXTRA_ENV_SETTINGS \ 613 #define CONFIG_EXTRA_ENV_SETTINGS \
608 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 614 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
609 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 615 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
610 "tftpflash=tftp $loadaddr $uboot;" \ 616 "tftpflash=tftp $loadaddr $uboot;" \
611 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 617 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
612 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 618 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
613 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 619 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
614 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 620 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
615 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 621 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
616 "fdtaddr=400000\0" \ 622 "fdtaddr=400000\0" \
617 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ 623 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
618 "ramdiskaddr=1000000\0" \ 624 "ramdiskaddr=1000000\0" \
619 "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \ 625 "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \
620 "console=ttyS0\0" \ 626 "console=ttyS0\0" \
621 "setbootargs=setenv bootargs " \ 627 "setbootargs=setenv bootargs " \
622 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 628 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
623 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 629 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
624 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 630 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
625 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 631 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
626 632
627 #define CONFIG_NFSBOOTCOMMAND \ 633 #define CONFIG_NFSBOOTCOMMAND \
628 "setenv rootdev /dev/nfs;" \ 634 "setenv rootdev /dev/nfs;" \
629 "run setbootargs;" \ 635 "run setbootargs;" \
630 "run setipargs;" \ 636 "run setipargs;" \
631 "tftp $loadaddr $bootfile;" \ 637 "tftp $loadaddr $bootfile;" \
632 "tftp $fdtaddr $fdtfile;" \ 638 "tftp $fdtaddr $fdtfile;" \
633 "bootm $loadaddr - $fdtaddr" 639 "bootm $loadaddr - $fdtaddr"
634 640
635 #define CONFIG_RAMBOOTCOMMAND \ 641 #define CONFIG_RAMBOOTCOMMAND \
636 "setenv rootdev /dev/ram;" \ 642 "setenv rootdev /dev/ram;" \
637 "run setbootargs;" \ 643 "run setbootargs;" \
638 "tftp $ramdiskaddr $ramdiskfile;" \ 644 "tftp $ramdiskaddr $ramdiskfile;" \
639 "tftp $loadaddr $bootfile;" \ 645 "tftp $loadaddr $bootfile;" \
640 "tftp $fdtaddr $fdtfile;" \ 646 "tftp $fdtaddr $fdtfile;" \
641 "bootm $loadaddr $ramdiskaddr $fdtaddr" 647 "bootm $loadaddr $ramdiskaddr $fdtaddr"
642 648
643 #undef MK_STR 649 #undef MK_STR
644 #undef XMK_STR 650 #undef XMK_STR
645 651
646 #endif /* __CONFIG_H */ 652 #endif /* __CONFIG_H */
647 653