driver:i2c:s3c24x0: adapt driver to new i2c

This patch adapts the s3c24x0 driver to the new i2c framework. Config file is modified for all the boards that use the driver. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> CC: Minkyu Kang <mk7.kang@samsung.com> CC: Heiko Schocher <hs@denx.de> CC: Inderpal Singh <inderpal.singh@linaro.org> CC: David Müller <d.mueller@elsoft.ch> CC: Chander Kashyap <k.chander@samsung.com> CC: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Reviewed-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>

driver:i2c:s3c24x0: adapt driver to new i2c
This patch adapts the s3c24x0 driver to the new i2c framework. Config file is modified for all the boards that use the driver. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> CC: Minkyu Kang <mk7.kang@samsung.com> CC: Heiko Schocher <hs@denx.de> CC: Inderpal Singh <inderpal.singh@linaro.org> CC: David Müller <d.mueller@elsoft.ch> CC: Chander Kashyap <k.chander@samsung.com> CC: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Reviewed-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Piotr Wilczek · Heiko Schocher
1 parent f44483b57c
Showing 10 changed files with 170 additions and 121 deletions Side-by-side Diff
board/samsung/smdk5250/exynos5-dt.c
board/samsung/trats/trats.c
board/samsung/trats2/trats2.c
drivers/i2c/Makefile
drivers/i2c/s3c24x0_i2c.c
include/configs/VCMA9.h
include/configs/arndale.h
include/configs/exynos5250-dt.h
include/configs/trats.h
include/configs/trats2.h
@@ -150,8 +150,6 @@
  
 	set_ps_hold_ctrl();
  
-	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
 	if (pmic_init(I2C_PMIC))
 		return -1;
  
@@ -57,15 +57,18 @@
  
 void i2c_init_board(void)
 {
-	struct exynos4_gpio_part1 *gpio1 =
-		(struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
+	int err;
 	struct exynos4_gpio_part2 *gpio2 =
 		(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
  
-	/* I2C_5 -> PMIC -> Adapter 0 */
-	s5p_gpio_direction_output(&gpio1->b, 7, 1);
-	s5p_gpio_direction_output(&gpio1->b, 6, 1);
-	/* I2C_9 -> FG -> Adapter 1 */
+	/* I2C_5 -> PMIC */
+	err = exynos_pinmux_config(PERIPH_ID_I2C5, PINMUX_FLAG_NONE);
+	if (err) {
+		debug("I2C%d not configured\n", (I2C_5));
+		return;
+	}
+
+	/* I2C_8 -> FG */
 	s5p_gpio_direction_output(&gpio2->y4, 0, 1);
 	s5p_gpio_direction_output(&gpio2->y4, 1, 1);
 }
  
@@ -290,10 +293,10 @@
 	 * The FUEL_GAUGE is marked as I2C9 on the schematic, but connected
 	 * to logical I2C adapter 1
 	 */
-	ret = pmic_init(I2C_0);
+	ret = pmic_init(I2C_5);
 	ret |= pmic_init_max8997();
-	ret |= power_fg_init(I2C_1);
-	ret |= power_muic_init(I2C_0);
+	ret |= power_fg_init(I2C_8);
+	ret |= power_muic_init(I2C_5);
 	ret |= power_bat_init(0);
 	if (ret)
 		return ret;
@@ -115,12 +115,17 @@
 #ifdef CONFIG_SYS_I2C_INIT_BOARD
 static void board_init_i2c(void)
 {
+	int err;
+
 	gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE;
 	gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
  
 	/* I2C_7 */
-	s5p_gpio_direction_output(&gpio1->d0, 2, 1);
-	s5p_gpio_direction_output(&gpio1->d0, 3, 1);
+	err = exynos_pinmux_config(PERIPH_ID_I2C7, PINMUX_FLAG_NONE);
+	if (err) {
+		debug("I2C%d not configured\n", (I2C_7));
+		return;
+	}
  
 	/* I2C_8 */
 	s5p_gpio_direction_output(&gpio1->f1, 4, 1);
@@ -132,6 +137,24 @@
 }
 #endif
  
+#ifdef CONFIG_SYS_I2C_SOFT
+int get_soft_i2c_scl_pin(void)
+{
+	if (I2C_ADAP_HWNR)
+		return exynos4x12_gpio_part2_get_nr(m2, 1); /* I2C9 */
+	else
+		return exynos4x12_gpio_part1_get_nr(f1, 4); /* I2C8 */
+}
+
+int get_soft_i2c_sda_pin(void)
+{
+	if (I2C_ADAP_HWNR)
+		return exynos4x12_gpio_part2_get_nr(m2, 0); /* I2C9 */
+	else
+		return exynos4x12_gpio_part1_get_nr(f1, 5); /* I2C8 */
+}
+#endif
+
 int board_early_init_f(void)
 {
 	check_hw_revision();
  
@@ -167,11 +190,11 @@
 #ifdef CONFIG_SYS_I2C_INIT_BOARD
 	board_init_i2c();
 #endif
-	pmic_init(I2C_0);		/* I2C adapter 0 - bus name I2C_5 */
+	pmic_init(I2C_7);		/* I2C adapter 7 - bus name s3c24x0_7 */
 	pmic_init_max77686();
-	pmic_init_max77693(I2C_2);	/* I2C adapter 2 - bus name I2C_10 */
-	power_muic_init(I2C_2);		/* I2C adapter 2 - bus name I2C_10 */
-	power_fg_init(I2C_1);		/* I2C adapter 1 - bus name I2C_9 */
+	pmic_init_max77693(I2C_9);	/* I2C adapter 9 - bus name soft1 */
+	power_muic_init(I2C_9);		/* I2C adapter 9 - bus name soft1 */
+	power_fg_init(I2C_8);		/* I2C adapter 8 - bus name soft0 */
 	power_bat_init(0);
  
 	p_chrg = pmic_get("MAX77693_PMIC");
@@ -12,7 +12,6 @@
 obj-$(CONFIG_I2C_MV) += mv_i2c.o
 obj-$(CONFIG_I2C_MXS) += mxs_i2c.o
 obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
-obj-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o
 obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
 obj-$(CONFIG_U8500_I2C) += u8500_i2c.o
 obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
@@ -24,6 +23,7 @@
 obj-$(CONFIG_SYS_I2C_OMAP34XX) += omap24xx_i2c.o
 obj-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
 obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o
+obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o
 obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
 obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
 obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
@@ -23,8 +23,6 @@
 #include <i2c.h>
 #include "s3c24x0_i2c.h"
  
-#ifdef CONFIG_HARD_I2C
-
 #define	I2C_WRITE	0
 #define I2C_READ	1
  
@@ -127,7 +125,6 @@
  * For SPL boot some boards need i2c before SDRAM is initialised so force
  * variables to live in SRAM
  */
-static unsigned int g_current_bus __attribute__((section(".data")));
 static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM]
 			__attribute__((section(".data")));
  
  
  
@@ -254,17 +251,17 @@
 	writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
 }
  
-static struct s3c24x0_i2c *get_base_i2c(void)
+static struct s3c24x0_i2c *get_base_i2c(int bus)
 {
 #ifdef CONFIG_EXYNOS4
 	struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
 							+ (EXYNOS4_I2C_SPACING
-							* g_current_bus));
+							* bus));
 	return i2c;
 #elif defined CONFIG_EXYNOS5
 	struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
 							+ (EXYNOS5_I2C_SPACING
-							* g_current_bus));
+							* bus));
 	return i2c;
 #else
 	return s3c24x0_get_base_i2c();
@@ -298,7 +295,6 @@
 	writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
 }
  
-#ifdef CONFIG_I2C_MULTI_BUS
 static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus)
 {
 	struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
@@ -330,7 +326,6 @@
 	}
 	return -1;
 }
-#endif
  
 static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus)
 {
  
  
  
@@ -401,49 +396,18 @@
 	hsi2c_ch_init(i2c_bus);
 }
  
-/*
- * MULTI BUS I2C support
- */
-
-#ifdef CONFIG_I2C_MULTI_BUS
-int i2c_set_bus_num(unsigned int bus)
+static void s3c24x0_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
 {
-	struct s3c24x0_i2c_bus *i2c_bus;
-
-	i2c_bus = get_bus(bus);
-	if (!i2c_bus)
-		return -1;
-	g_current_bus = bus;
-
-	if (i2c_bus->is_highspeed) {
-		if (hsi2c_get_clk_details(i2c_bus))
-			return -1;
-		hsi2c_ch_init(i2c_bus);
-	} else {
-		i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
-						CONFIG_SYS_I2C_SLAVE);
-	}
-
-	return 0;
-}
-
-unsigned int i2c_get_bus_num(void)
-{
-	return g_current_bus;
-}
-#endif
-
-void i2c_init(int speed, int slaveadd)
-{
 	struct s3c24x0_i2c *i2c;
+	struct s3c24x0_i2c_bus *bus;
+
 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
 	struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
 #endif
 	ulong start_time = get_timer(0);
  
 	/* By default i2c channel 0 is the current bus */
-	g_current_bus = 0;
-	i2c = get_base_i2c();
+	i2c = get_base_i2c(adap->hwadapnr);
  
 	/*
 	 * In case the previous transfer is still going, wait to give it a
@@ -505,6 +469,10 @@
 	}
 #endif /* #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) */
 	i2c_ch_init(i2c, speed, slaveadd);
+
+	bus = &i2c_bus[adap->hwadapnr];
+	bus->active = true;
+	bus->regs = i2c;
 }
  
 /*
@@ -728,6 +696,29 @@
 	return rv;
 }
  
+static unsigned int s3c24x0_i2c_set_bus_speed(struct i2c_adapter *adap,
+					  unsigned int speed)
+{
+	struct s3c24x0_i2c_bus *i2c_bus;
+
+	i2c_bus = get_bus(adap->hwadapnr);
+	if (!i2c_bus)
+		return -1;
+
+	i2c_bus->clock_frequency = speed;
+
+	if (i2c_bus->is_highspeed) {
+		if (hsi2c_get_clk_details(i2c_bus))
+			return -1;
+		hsi2c_ch_init(i2c_bus);
+	} else {
+		i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
+			    CONFIG_SYS_I2C_S3C24X0_SLAVE);
+	}
+
+	return 0;
+}
+
 /*
  * cmd_type is 0 for write, 1 for read.
  *
  
@@ -840,13 +831,13 @@
 	return result;
 }
  
-int i2c_probe(uchar chip)
+static int s3c24x0_i2c_probe(struct i2c_adapter *adap, uchar chip)
 {
 	struct s3c24x0_i2c_bus *i2c_bus;
 	uchar buf[1];
 	int ret;
  
-	i2c_bus = get_bus(g_current_bus);
+	i2c_bus = get_bus(adap->hwadapnr);
 	if (!i2c_bus)
 		return -1;
 	buf[0] = 0;
  
@@ -864,11 +855,11 @@
 				I2C_READ, chip << 1, 0, 0, buf, 1);
 	}
  
-
 	return ret != I2C_OK;
 }
  
-int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int s3c24x0_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
+			    int alen, uchar *buffer, int len)
 {
 	struct s3c24x0_i2c_bus *i2c_bus;
 	uchar xaddr[4];
@@ -902,7 +893,7 @@
 		chip |= ((addr >> (alen * 8)) &
 			 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 #endif
-	i2c_bus = get_bus(g_current_bus);
+	i2c_bus = get_bus(adap->hwadapnr);
 	if (!i2c_bus)
 		return -1;
  
@@ -922,7 +913,8 @@
 	return 0;
 }
  
-int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int s3c24x0_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
+			 int alen, uchar *buffer, int len)
 {
 	struct s3c24x0_i2c_bus *i2c_bus;
 	uchar xaddr[4];
@@ -955,7 +947,7 @@
 		chip |= ((addr >> (alen * 8)) &
 			 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 #endif
-	i2c_bus = get_bus(g_current_bus);
+	i2c_bus = get_bus(adap->hwadapnr);
 	if (!i2c_bus)
 		return -1;
  
@@ -1001,8 +993,8 @@
  
 		bus->id = pinmux_decode_periph_id(blob, node);
 		bus->clock_frequency = fdtdec_get_int(blob, node,
-						      "clock-frequency",
-						      CONFIG_SYS_I2C_SPEED);
+						"clock-frequency",
+						CONFIG_SYS_I2C_S3C24X0_SPEED);
 		bus->node = node;
 		bus->bus_num = i;
 		exynos_pinmux_config(bus->id, 0);
@@ -1044,7 +1036,6 @@
 	return -1;
 }
  
-#ifdef CONFIG_I2C_MULTI_BUS
 int i2c_reset_port_fdt(const void *blob, int node)
 {
 	struct s3c24x0_i2c_bus *i2c_bus;
  
  
@@ -1068,13 +1059,62 @@
 		hsi2c_ch_init(i2c_bus);
 	} else {
 		i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
-						CONFIG_SYS_I2C_SLAVE);
+			    CONFIG_SYS_I2C_S3C24X0_SLAVE);
 	}
  
 	return 0;
 }
 #endif
-#endif
  
-#endif /* CONFIG_HARD_I2C */
+/*
+ * Register s3c24x0 i2c adapters
+ */
+U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_0, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			 s3c24x0_i2c_read, s3c24x0_i2c_write,
+			 s3c24x0_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_S3C24X0_SPEED,
+			 CONFIG_SYS_I2C_S3C24X0_SLAVE,
+			 0)
+U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_1, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			 s3c24x0_i2c_read, s3c24x0_i2c_write,
+			 s3c24x0_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_S3C24X0_SPEED,
+			 CONFIG_SYS_I2C_S3C24X0_SLAVE,
+			 1)
+U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_2, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			 s3c24x0_i2c_read, s3c24x0_i2c_write,
+			 s3c24x0_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_S3C24X0_SPEED,
+			 CONFIG_SYS_I2C_S3C24X0_SLAVE,
+			 2)
+U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_3, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			 s3c24x0_i2c_read, s3c24x0_i2c_write,
+			 s3c24x0_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_S3C24X0_SPEED,
+			 CONFIG_SYS_I2C_S3C24X0_SLAVE,
+			 3)
+U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_4, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			 s3c24x0_i2c_read, s3c24x0_i2c_write,
+			 s3c24x0_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_S3C24X0_SPEED,
+			 CONFIG_SYS_I2C_S3C24X0_SLAVE,
+			 4)
+U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_5, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			 s3c24x0_i2c_read, s3c24x0_i2c_write,
+			 s3c24x0_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_S3C24X0_SPEED,
+			 CONFIG_SYS_I2C_S3C24X0_SLAVE,
+			 5)
+U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_6, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			 s3c24x0_i2c_read, s3c24x0_i2c_write,
+			 s3c24x0_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_S3C24X0_SPEED,
+			 CONFIG_SYS_I2C_S3C24X0_SLAVE,
+			 6)
+U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_7, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			 s3c24x0_i2c_read, s3c24x0_i2c_write,
+			 s3c24x0_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_S3C24X0_SPEED,
+			 CONFIG_SYS_I2C_S3C24X0_SLAVE,
+			 7)
@@ -73,12 +73,12 @@
  * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at
  * address 0x50 with 16bit addressing
  */
-#define CONFIG_HARD_I2C				/* I2C with hardware support */
-#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed */
-#define CONFIG_SYS_I2C_SLAVE		0x7F	/* I2C slave addr */
+#define CONFIG_SYS_I2C
  
 /* we use the built-in I2C controller */
-#define CONFIG_DRIVER_S3C24X0_I2C
+#define CONFIG_SYS_I2C_S3C24X0
+#define CONFIG_SYS_I2C_S3C24X0_SPEED    100000	/* I2C speed */
+#define CONFIG_SYS_I2C_S3C24X0_SLAVE    0x7F	/* I2C slave addr */
  
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
@@ -214,13 +214,12 @@
  
 /* I2C */
 #define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C
 #define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C_SPEED	100000		/* 100 Kbps */
-#define CONFIG_DRIVER_S3C24X0_I2C
-#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_S3C24X0_SPEED	100000		/* 100 Kbps */
+#define CONFIG_SYS_I2C_S3C24X0
 #define CONFIG_MAX_I2C_NUM	8
-#define CONFIG_SYS_I2C_SLAVE    0x0
+#define CONFIG_SYS_I2C_S3C24X0_SLAVE    0x0
 #define CONFIG_I2C_EDID
  
 /* PMIC */
@@ -249,13 +249,13 @@
  
 /* I2C */
 #define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C
 #define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C_SPEED	100000		/* 100 Kbps */
-#define CONFIG_DRIVER_S3C24X0_I2C
+#define CONFIG_SYS_I2C_S3C24X0_SPEED	100000		/* 100 Kbps */
+#define CONFIG_SYS_I2C_S3C24X0
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_MAX_I2C_NUM	8
-#define CONFIG_SYS_I2C_SLAVE    0x0
+#define CONFIG_SYS_I2C_S3C24X0_SLAVE    0x0
 #define CONFIG_I2C_EDID
  
 /* PMIC */
@@ -16,6 +16,7 @@
  */
 #define CONFIG_SAMSUNG		/* in a SAMSUNG core */
 #define CONFIG_S5P		/* which is in a S5P Family */
+#define CONFIG_EXYNOS4		/* which is in a EXYNOS4XXX */
 #define CONFIG_EXYNOS4210	/* which is in a EXYNOS4210 */
 #define CONFIG_TRATS		/* working with TRATS */
 #define CONFIG_TIZEN		/* TIZEN lib */
  
  
  
  
@@ -268,31 +269,21 @@
 #define CONFIG_SYS_CACHELINE_SIZE       32
  
 #define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_S3C24X0
+#define CONFIG_SYS_I2C_S3C24X0_SPEED	100000
+#define CONFIG_SYS_I2C_S3C24X0_SLAVE	0xFE
+#define CONFIG_MAX_I2C_NUM		8
 #define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
 #define CONFIG_SYS_I2C_SOFT_SPEED	50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
-#define I2C_SOFT_DECLARATIONS2
-#define CONFIG_SYS_I2C_SOFT_SPEED_2     50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE_2     0x7F
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
 #define CONFIG_SOFT_I2C_READ_REPEATED_START
 #define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SOFT_I2C_MULTI_BUS
-#define CONFIG_SYS_MAX_I2C_BUS	15
  
 #include <asm/arch/gpio.h>
  
-/* I2C PMIC */
-#define CONFIG_SOFT_I2C_I2C5_SCL exynos4_gpio_part1_get_nr(b, 7)
-#define CONFIG_SOFT_I2C_I2C5_SDA exynos4_gpio_part1_get_nr(b, 6)
-
 /* I2C FG */
-#define CONFIG_SOFT_I2C_I2C9_SCL exynos4_gpio_part2_get_nr(y4, 1)
-#define CONFIG_SOFT_I2C_I2C9_SDA exynos4_gpio_part2_get_nr(y4, 0)
-
-#define CONFIG_SOFT_I2C_GPIO_SCL get_multi_scl_pin()
-#define CONFIG_SOFT_I2C_GPIO_SDA get_multi_sda_pin()
-#define I2C_INIT multi_i2c_init()
+#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part2_get_nr(y4, 1)
+#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part2_get_nr(y4, 0)
  
 #define CONFIG_POWER
 #define CONFIG_POWER_I2C
@@ -260,30 +260,25 @@
 #include <asm/arch/gpio.h>
  
 #define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_S3C24X0
+#define CONFIG_SYS_I2C_S3C24X0_SPEED	100000
+#define CONFIG_SYS_I2C_S3C24X0_SLAVE	0
+#define CONFIG_MAX_I2C_NUM		8
+#define CONFIG_SYS_I2C_SOFT
 #define CONFIG_SYS_I2C_SOFT_SPEED	50000
 #define CONFIG_SYS_I2C_SOFT_SLAVE	0x00
 #define I2C_SOFT_DECLARATIONS2
 #define CONFIG_SYS_I2C_SOFT_SPEED_2     50000
 #define CONFIG_SYS_I2C_SOFT_SLAVE_2     0x00
-#define I2C_SOFT_DECLARATIONS3
-#define CONFIG_SYS_I2C_SOFT_SPEED_3     50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE_3     0x00
 #define CONFIG_SOFT_I2C_READ_REPEATED_START
 #define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SOFT_I2C_MULTI_BUS
-#define CONFIG_SYS_MAX_I2C_BUS		15
  
-#define CONFIG_SOFT_I2C_I2C5_SCL exynos4x12_gpio_part1_get_nr(d0, 3)
-#define CONFIG_SOFT_I2C_I2C5_SDA exynos4x12_gpio_part1_get_nr(d0, 2)
-#define CONFIG_SOFT_I2C_I2C9_SCL exynos4x12_gpio_part1_get_nr(f1, 4)
-#define CONFIG_SOFT_I2C_I2C9_SDA exynos4x12_gpio_part1_get_nr(f1, 5)
-#define CONFIG_SOFT_I2C_I2C10_SCL exynos4x12_gpio_part2_get_nr(m2, 1)
-#define CONFIG_SOFT_I2C_I2C10_SDA exynos4x12_gpio_part2_get_nr(m2, 0)
-#define CONFIG_SOFT_I2C_GPIO_SCL get_multi_scl_pin()
-#define CONFIG_SOFT_I2C_GPIO_SDA get_multi_sda_pin()
-#define I2C_INIT multi_i2c_init()
+#ifndef __ASSEMBLY__
+int get_soft_i2c_scl_pin(void);
+int get_soft_i2c_sda_pin(void);
+#endif
+#define CONFIG_SOFT_I2C_GPIO_SCL	get_soft_i2c_scl_pin()
+#define CONFIG_SOFT_I2C_GPIO_SDA	get_soft_i2c_sda_pin()
  
 /* POWER */
 #define CONFIG_POWER
...	...	@@ -150,8 +150,6 @@
150	150
151	151	set_ps_hold_ctrl();
152	152
153		- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
154		-
155	153	if (pmic_init(I2C_PMIC))
156	154	return -1;
157	155
...	...	@@ -57,15 +57,18 @@
57	57
58	58	void i2c_init_board(void)
59	59	{
60		- struct exynos4_gpio_part1 *gpio1 =
61		- (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
	60	+ int err;
62	61	struct exynos4_gpio_part2 *gpio2 =
63	62	(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
64	63
65		- /* I2C_5 -> PMIC -> Adapter 0 */
66		- s5p_gpio_direction_output(&gpio1->b, 7, 1);
67		- s5p_gpio_direction_output(&gpio1->b, 6, 1);
68		- /* I2C_9 -> FG -> Adapter 1 */
	64	+ /* I2C_5 -> PMIC */
	65	+ err = exynos_pinmux_config(PERIPH_ID_I2C5, PINMUX_FLAG_NONE);
	66	+ if (err) {
	67	+ debug("I2C%d not configured\n", (I2C_5));
	68	+ return;
	69	+ }
	70	+
	71	+ /* I2C_8 -> FG */
69	72	s5p_gpio_direction_output(&gpio2->y4, 0, 1);
70	73	s5p_gpio_direction_output(&gpio2->y4, 1, 1);
71	74	}
72	75
...	...	@@ -290,10 +293,10 @@
290	293	* The FUEL_GAUGE is marked as I2C9 on the schematic, but connected
291	294	* to logical I2C adapter 1
292	295	*/
293		- ret = pmic_init(I2C_0);
	296	+ ret = pmic_init(I2C_5);
294	297	ret \|= pmic_init_max8997();
295		- ret \|= power_fg_init(I2C_1);
296		- ret \|= power_muic_init(I2C_0);
	298	+ ret \|= power_fg_init(I2C_8);
	299	+ ret \|= power_muic_init(I2C_5);
297	300	ret \|= power_bat_init(0);
298	301	if (ret)
299	302	return ret;
...	...	@@ -115,12 +115,17 @@
115	115	#ifdef CONFIG_SYS_I2C_INIT_BOARD
116	116	static void board_init_i2c(void)
117	117	{
	118	+ int err;
	119	+
118	120	gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE;
119	121	gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
120	122
121	123	/* I2C_7 */
122		- s5p_gpio_direction_output(&gpio1->d0, 2, 1);
123		- s5p_gpio_direction_output(&gpio1->d0, 3, 1);
	124	+ err = exynos_pinmux_config(PERIPH_ID_I2C7, PINMUX_FLAG_NONE);
	125	+ if (err) {
	126	+ debug("I2C%d not configured\n", (I2C_7));
	127	+ return;
	128	+ }
124	129
125	130	/* I2C_8 */
126	131	s5p_gpio_direction_output(&gpio1->f1, 4, 1);
...	...	@@ -132,6 +137,24 @@
132	137	}
133	138	#endif
134	139
	140	+#ifdef CONFIG_SYS_I2C_SOFT
	141	+int get_soft_i2c_scl_pin(void)
	142	+{
	143	+ if (I2C_ADAP_HWNR)
	144	+ return exynos4x12_gpio_part2_get_nr(m2, 1); /* I2C9 */
	145	+ else
	146	+ return exynos4x12_gpio_part1_get_nr(f1, 4); /* I2C8 */
	147	+}
	148	+
	149	+int get_soft_i2c_sda_pin(void)
	150	+{
	151	+ if (I2C_ADAP_HWNR)
	152	+ return exynos4x12_gpio_part2_get_nr(m2, 0); /* I2C9 */
	153	+ else
	154	+ return exynos4x12_gpio_part1_get_nr(f1, 5); /* I2C8 */
	155	+}
	156	+#endif
	157	+
135	158	int board_early_init_f(void)
136	159	{
137	160	check_hw_revision();
138	161
...	...	@@ -167,11 +190,11 @@
167	190	#ifdef CONFIG_SYS_I2C_INIT_BOARD
168	191	board_init_i2c();
169	192	#endif
170		- pmic_init(I2C_0); /* I2C adapter 0 - bus name I2C_5 */
	193	+ pmic_init(I2C_7); /* I2C adapter 7 - bus name s3c24x0_7 */
171	194	pmic_init_max77686();
172		- pmic_init_max77693(I2C_2); /* I2C adapter 2 - bus name I2C_10 */
173		- power_muic_init(I2C_2); /* I2C adapter 2 - bus name I2C_10 */
174		- power_fg_init(I2C_1); /* I2C adapter 1 - bus name I2C_9 */
	195	+ pmic_init_max77693(I2C_9); /* I2C adapter 9 - bus name soft1 */
	196	+ power_muic_init(I2C_9); /* I2C adapter 9 - bus name soft1 */
	197	+ power_fg_init(I2C_8); /* I2C adapter 8 - bus name soft0 */
175	198	power_bat_init(0);
176	199
177	200	p_chrg = pmic_get("MAX77693_PMIC");
...	...	@@ -12,7 +12,6 @@
12	12	obj-$(CONFIG_I2C_MV) += mv_i2c.o
13	13	obj-$(CONFIG_I2C_MXS) += mxs_i2c.o
14	14	obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
15		-obj-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o
16	15	obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
17	16	obj-$(CONFIG_U8500_I2C) += u8500_i2c.o
18	17	obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
...	...	@@ -24,6 +23,7 @@
24	23	obj-$(CONFIG_SYS_I2C_OMAP34XX) += omap24xx_i2c.o
25	24	obj-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
26	25	obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o
	26	+obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o
27	27	obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
28	28	obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
29	29	obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
...	...	@@ -23,8 +23,6 @@
23	23	#include <i2c.h>
24	24	#include "s3c24x0_i2c.h"
25	25
26		-#ifdef CONFIG_HARD_I2C
27		-
28	26	#define I2C_WRITE 0
29	27	#define I2C_READ 1
30	28
...	...	@@ -127,7 +125,6 @@
127	125	* For SPL boot some boards need i2c before SDRAM is initialised so force
128	126	* variables to live in SRAM
129	127	*/
130		-static unsigned int g_current_bus __attribute__((section(".data")));
131	128	static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM]
132	129	__attribute__((section(".data")));
133	130
134	131
135	132
...	...	@@ -254,17 +251,17 @@
254	251	writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
255	252	}
256	253
257		-static struct s3c24x0_i2c *get_base_i2c(void)
	254	+static struct s3c24x0_i2c *get_base_i2c(int bus)
258	255	{
259	256	#ifdef CONFIG_EXYNOS4
260	257	struct s3c24x0_i2c i2c = (struct s3c24x0_i2c )(samsung_get_base_i2c()
261	258	+ (EXYNOS4_I2C_SPACING
262		- * g_current_bus));
	259	+ * bus));
263	260	return i2c;
264	261	#elif defined CONFIG_EXYNOS5
265	262	struct s3c24x0_i2c i2c = (struct s3c24x0_i2c )(samsung_get_base_i2c()
266	263	+ (EXYNOS5_I2C_SPACING
267		- * g_current_bus));
	264	+ * bus));
268	265	return i2c;
269	266	#else
270	267	return s3c24x0_get_base_i2c();
...	...	@@ -298,7 +295,6 @@
298	295	writel(I2C_MODE_MT \| I2C_TXRX_ENA, &i2c->iicstat);
299	296	}
300	297
301		-#ifdef CONFIG_I2C_MULTI_BUS
302	298	static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus)
303	299	{
304	300	struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
...	...	@@ -330,7 +326,6 @@
330	326	}
331	327	return -1;
332	328	}
333		-#endif
334	329
335	330	static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus)
336	331	{
337	332
338	333
339	334
...	...	@@ -401,49 +396,18 @@
401	396	hsi2c_ch_init(i2c_bus);
402	397	}
403	398
404		-/*
405		- * MULTI BUS I2C support
406		- */
407		-
408		-#ifdef CONFIG_I2C_MULTI_BUS
409		-int i2c_set_bus_num(unsigned int bus)
	399	+static void s3c24x0_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
410	400	{
411		- struct s3c24x0_i2c_bus *i2c_bus;
412		-
413		- i2c_bus = get_bus(bus);
414		- if (!i2c_bus)
415		- return -1;
416		- g_current_bus = bus;
417		-
418		- if (i2c_bus->is_highspeed) {
419		- if (hsi2c_get_clk_details(i2c_bus))
420		- return -1;
421		- hsi2c_ch_init(i2c_bus);
422		- } else {
423		- i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
424		- CONFIG_SYS_I2C_SLAVE);
425		- }
426		-
427		- return 0;
428		-}
429		-
430		-unsigned int i2c_get_bus_num(void)
431		-{
432		- return g_current_bus;
433		-}
434		-#endif
435		-
436		-void i2c_init(int speed, int slaveadd)
437		-{
438	401	struct s3c24x0_i2c *i2c;
	402	+ struct s3c24x0_i2c_bus *bus;
	403	+
439	404	#if !(defined CONFIG_EXYNOS4 \|\| defined CONFIG_EXYNOS5)
440	405	struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
441	406	#endif
442	407	ulong start_time = get_timer(0);
443	408
444	409	/* By default i2c channel 0 is the current bus */
445		- g_current_bus = 0;
446		- i2c = get_base_i2c();
	410	+ i2c = get_base_i2c(adap->hwadapnr);
447	411
448	412	/*
449	413	* In case the previous transfer is still going, wait to give it a
...	...	@@ -505,6 +469,10 @@
505	469	}
506	470	#endif /* #if !(defined CONFIG_EXYNOS4 \|\| defined CONFIG_EXYNOS5) */
507	471	i2c_ch_init(i2c, speed, slaveadd);
	472	+
	473	+ bus = &i2c_bus[adap->hwadapnr];
	474	+ bus->active = true;
	475	+ bus->regs = i2c;
508	476	}
509	477
510	478	/*
...	...	@@ -728,6 +696,29 @@
728	696	return rv;
729	697	}
730	698
	699	+static unsigned int s3c24x0_i2c_set_bus_speed(struct i2c_adapter *adap,
	700	+ unsigned int speed)
	701	+{
	702	+ struct s3c24x0_i2c_bus *i2c_bus;
	703	+
	704	+ i2c_bus = get_bus(adap->hwadapnr);
	705	+ if (!i2c_bus)
	706	+ return -1;
	707	+
	708	+ i2c_bus->clock_frequency = speed;
	709	+
	710	+ if (i2c_bus->is_highspeed) {
	711	+ if (hsi2c_get_clk_details(i2c_bus))
	712	+ return -1;
	713	+ hsi2c_ch_init(i2c_bus);
	714	+ } else {
	715	+ i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
	716	+ CONFIG_SYS_I2C_S3C24X0_SLAVE);
	717	+ }
	718	+
	719	+ return 0;
	720	+}
	721	+
731	722	/*
732	723	* cmd_type is 0 for write, 1 for read.
733	724	*
734	725
...	...	@@ -840,13 +831,13 @@
840	831	return result;
841	832	}
842	833
843		-int i2c_probe(uchar chip)
	834	+static int s3c24x0_i2c_probe(struct i2c_adapter *adap, uchar chip)
844	835	{
845	836	struct s3c24x0_i2c_bus *i2c_bus;
846	837	uchar buf[1];
847	838	int ret;
848	839
849		- i2c_bus = get_bus(g_current_bus);
	840	+ i2c_bus = get_bus(adap->hwadapnr);
850	841	if (!i2c_bus)
851	842	return -1;
852	843	buf[0] = 0;
853	844
...	...	@@ -864,11 +855,11 @@
864	855	I2C_READ, chip << 1, 0, 0, buf, 1);
865	856	}
866	857
867		-
868	858	return ret != I2C_OK;
869	859	}
870	860
871		-int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
	861	+static int s3c24x0_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
	862	+ int alen, uchar *buffer, int len)
872	863	{
873	864	struct s3c24x0_i2c_bus *i2c_bus;
874	865	uchar xaddr[4];
...	...	@@ -902,7 +893,7 @@
902	893	chip \|= ((addr >> (alen * 8)) &
903	894	CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
904	895	#endif
905		- i2c_bus = get_bus(g_current_bus);
	896	+ i2c_bus = get_bus(adap->hwadapnr);
906	897	if (!i2c_bus)
907	898	return -1;
908	899
...	...	@@ -922,7 +913,8 @@
922	913	return 0;
923	914	}
924	915
925		-int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
	916	+static int s3c24x0_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
	917	+ int alen, uchar *buffer, int len)
926	918	{
927	919	struct s3c24x0_i2c_bus *i2c_bus;
928	920	uchar xaddr[4];
...	...	@@ -955,7 +947,7 @@
955	947	chip \|= ((addr >> (alen * 8)) &
956	948	CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
957	949	#endif
958		- i2c_bus = get_bus(g_current_bus);
	950	+ i2c_bus = get_bus(adap->hwadapnr);
959	951	if (!i2c_bus)
960	952	return -1;
961	953
...	...	@@ -1001,8 +993,8 @@
1001	993
1002	994	bus->id = pinmux_decode_periph_id(blob, node);
1003	995	bus->clock_frequency = fdtdec_get_int(blob, node,
1004		- "clock-frequency",
1005		- CONFIG_SYS_I2C_SPEED);
	996	+ "clock-frequency",
	997	+ CONFIG_SYS_I2C_S3C24X0_SPEED);
1006	998	bus->node = node;
1007	999	bus->bus_num = i;
1008	1000	exynos_pinmux_config(bus->id, 0);
...	...	@@ -1044,7 +1036,6 @@
1044	1036	return -1;
1045	1037	}
1046	1038
1047		-#ifdef CONFIG_I2C_MULTI_BUS
1048	1039	int i2c_reset_port_fdt(const void *blob, int node)
1049	1040	{
1050	1041	struct s3c24x0_i2c_bus *i2c_bus;
1051	1042
1052	1043
...	...	@@ -1068,13 +1059,62 @@
1068	1059	hsi2c_ch_init(i2c_bus);
1069	1060	} else {
1070	1061	i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
1071		- CONFIG_SYS_I2C_SLAVE);
	1062	+ CONFIG_SYS_I2C_S3C24X0_SLAVE);
1072	1063	}
1073	1064
1074	1065	return 0;
1075	1066	}
1076	1067	#endif
1077		-#endif
1078	1068
1079		-#endif /* CONFIG_HARD_I2C */
	1069	+/*
	1070	+ * Register s3c24x0 i2c adapters
	1071	+ */
	1072	+U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_0, s3c24x0_i2c_init, s3c24x0_i2c_probe,
	1073	+ s3c24x0_i2c_read, s3c24x0_i2c_write,
	1074	+ s3c24x0_i2c_set_bus_speed,
	1075	+ CONFIG_SYS_I2C_S3C24X0_SPEED,
	1076	+ CONFIG_SYS_I2C_S3C24X0_SLAVE,
	1077	+ 0)
	1078	+U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_1, s3c24x0_i2c_init, s3c24x0_i2c_probe,
	1079	+ s3c24x0_i2c_read, s3c24x0_i2c_write,
	1080	+ s3c24x0_i2c_set_bus_speed,
	1081	+ CONFIG_SYS_I2C_S3C24X0_SPEED,
	1082	+ CONFIG_SYS_I2C_S3C24X0_SLAVE,
	1083	+ 1)
	1084	+U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_2, s3c24x0_i2c_init, s3c24x0_i2c_probe,
	1085	+ s3c24x0_i2c_read, s3c24x0_i2c_write,
	1086	+ s3c24x0_i2c_set_bus_speed,
	1087	+ CONFIG_SYS_I2C_S3C24X0_SPEED,
	1088	+ CONFIG_SYS_I2C_S3C24X0_SLAVE,
	1089	+ 2)
	1090	+U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_3, s3c24x0_i2c_init, s3c24x0_i2c_probe,
	1091	+ s3c24x0_i2c_read, s3c24x0_i2c_write,
	1092	+ s3c24x0_i2c_set_bus_speed,
	1093	+ CONFIG_SYS_I2C_S3C24X0_SPEED,
	1094	+ CONFIG_SYS_I2C_S3C24X0_SLAVE,
	1095	+ 3)
	1096	+U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_4, s3c24x0_i2c_init, s3c24x0_i2c_probe,
	1097	+ s3c24x0_i2c_read, s3c24x0_i2c_write,
	1098	+ s3c24x0_i2c_set_bus_speed,
	1099	+ CONFIG_SYS_I2C_S3C24X0_SPEED,
	1100	+ CONFIG_SYS_I2C_S3C24X0_SLAVE,
	1101	+ 4)
	1102	+U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_5, s3c24x0_i2c_init, s3c24x0_i2c_probe,
	1103	+ s3c24x0_i2c_read, s3c24x0_i2c_write,
	1104	+ s3c24x0_i2c_set_bus_speed,
	1105	+ CONFIG_SYS_I2C_S3C24X0_SPEED,
	1106	+ CONFIG_SYS_I2C_S3C24X0_SLAVE,
	1107	+ 5)
	1108	+U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_6, s3c24x0_i2c_init, s3c24x0_i2c_probe,
	1109	+ s3c24x0_i2c_read, s3c24x0_i2c_write,
	1110	+ s3c24x0_i2c_set_bus_speed,
	1111	+ CONFIG_SYS_I2C_S3C24X0_SPEED,
	1112	+ CONFIG_SYS_I2C_S3C24X0_SLAVE,
	1113	+ 6)
	1114	+U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_7, s3c24x0_i2c_init, s3c24x0_i2c_probe,
	1115	+ s3c24x0_i2c_read, s3c24x0_i2c_write,
	1116	+ s3c24x0_i2c_set_bus_speed,
	1117	+ CONFIG_SYS_I2C_S3C24X0_SPEED,
	1118	+ CONFIG_SYS_I2C_S3C24X0_SLAVE,
	1119	+ 7)
...	...	@@ -73,12 +73,12 @@
73	73	* the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at
74	74	* address 0x50 with 16bit addressing
75	75	*/
76		-#define CONFIG_HARD_I2C /* I2C with hardware support */
77		-#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
78		-#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave addr */
	76	+#define CONFIG_SYS_I2C
79	77
80	78	/* we use the built-in I2C controller */
81		-#define CONFIG_DRIVER_S3C24X0_I2C
	79	+#define CONFIG_SYS_I2C_S3C24X0
	80	+#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* I2C speed */
	81	+#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x7F /* I2C slave addr */
82	82
83	83	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
84	84	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
...	...	@@ -214,13 +214,12 @@
214	214
215	215	/* I2C */
216	216	#define CONFIG_SYS_I2C_INIT_BOARD
217		-#define CONFIG_HARD_I2C
	217	+#define CONFIG_SYS_I2C
218	218	#define CONFIG_CMD_I2C
219		-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 Kbps */
220		-#define CONFIG_DRIVER_S3C24X0_I2C
221		-#define CONFIG_I2C_MULTI_BUS
	219	+#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */
	220	+#define CONFIG_SYS_I2C_S3C24X0
222	221	#define CONFIG_MAX_I2C_NUM 8
223		-#define CONFIG_SYS_I2C_SLAVE 0x0
	222	+#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0
224	223	#define CONFIG_I2C_EDID
225	224
226	225	/* PMIC */
...	...	@@ -249,13 +249,13 @@
249	249
250	250	/* I2C */
251	251	#define CONFIG_SYS_I2C_INIT_BOARD
252		-#define CONFIG_HARD_I2C
	252	+#define CONFIG_SYS_I2C
253	253	#define CONFIG_CMD_I2C
254		-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 Kbps */
255		-#define CONFIG_DRIVER_S3C24X0_I2C
	254	+#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */
	255	+#define CONFIG_SYS_I2C_S3C24X0
256	256	#define CONFIG_I2C_MULTI_BUS
257	257	#define CONFIG_MAX_I2C_NUM 8
258		-#define CONFIG_SYS_I2C_SLAVE 0x0
	258	+#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0
259	259	#define CONFIG_I2C_EDID
260	260
261	261	/* PMIC */
...	...	@@ -16,6 +16,7 @@
16	16	*/
17	17	#define CONFIG_SAMSUNG /* in a SAMSUNG core */
18	18	#define CONFIG_S5P /* which is in a S5P Family */
	19	+#define CONFIG_EXYNOS4 /* which is in a EXYNOS4XXX */
19	20	#define CONFIG_EXYNOS4210 /* which is in a EXYNOS4210 */
20	21	#define CONFIG_TRATS /* working with TRATS */
21	22	#define CONFIG_TIZEN /* TIZEN lib */
22	23
23	24
24	25
25	26
...	...	@@ -268,31 +269,21 @@
268	269	#define CONFIG_SYS_CACHELINE_SIZE 32
269	270
270	271	#define CONFIG_SYS_I2C
	272	+#define CONFIG_SYS_I2C_S3C24X0
	273	+#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000
	274	+#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0xFE
	275	+#define CONFIG_MAX_I2C_NUM 8
271	276	#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
272	277	#define CONFIG_SYS_I2C_SOFT_SPEED 50000
273		-#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
274		-#define I2C_SOFT_DECLARATIONS2
275		-#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
276		-#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
	278	+#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
277	279	#define CONFIG_SOFT_I2C_READ_REPEATED_START
278	280	#define CONFIG_SYS_I2C_INIT_BOARD
279		-#define CONFIG_I2C_MULTI_BUS
280		-#define CONFIG_SOFT_I2C_MULTI_BUS
281		-#define CONFIG_SYS_MAX_I2C_BUS 15
282	281
283	282	#include <asm/arch/gpio.h>
284	283
285		-/* I2C PMIC */
286		-#define CONFIG_SOFT_I2C_I2C5_SCL exynos4_gpio_part1_get_nr(b, 7)
287		-#define CONFIG_SOFT_I2C_I2C5_SDA exynos4_gpio_part1_get_nr(b, 6)
288		-
289	284	/* I2C FG */
290		-#define CONFIG_SOFT_I2C_I2C9_SCL exynos4_gpio_part2_get_nr(y4, 1)
291		-#define CONFIG_SOFT_I2C_I2C9_SDA exynos4_gpio_part2_get_nr(y4, 0)
292		-
293		-#define CONFIG_SOFT_I2C_GPIO_SCL get_multi_scl_pin()
294		-#define CONFIG_SOFT_I2C_GPIO_SDA get_multi_sda_pin()
295		-#define I2C_INIT multi_i2c_init()
	285	+#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part2_get_nr(y4, 1)
	286	+#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part2_get_nr(y4, 0)
296	287
297	288	#define CONFIG_POWER
298	289	#define CONFIG_POWER_I2C
...	...	@@ -260,30 +260,25 @@
260	260	#include <asm/arch/gpio.h>
261	261
262	262	#define CONFIG_SYS_I2C
263		-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
	263	+#define CONFIG_SYS_I2C_S3C24X0
	264	+#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000
	265	+#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0
	266	+#define CONFIG_MAX_I2C_NUM 8
	267	+#define CONFIG_SYS_I2C_SOFT
264	268	#define CONFIG_SYS_I2C_SOFT_SPEED 50000
265	269	#define CONFIG_SYS_I2C_SOFT_SLAVE 0x00
266	270	#define I2C_SOFT_DECLARATIONS2
267	271	#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
268	272	#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x00
269		-#define I2C_SOFT_DECLARATIONS3
270		-#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
271		-#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x00
272	273	#define CONFIG_SOFT_I2C_READ_REPEATED_START
273	274	#define CONFIG_SYS_I2C_INIT_BOARD
274		-#define CONFIG_I2C_MULTI_BUS
275		-#define CONFIG_SOFT_I2C_MULTI_BUS
276		-#define CONFIG_SYS_MAX_I2C_BUS 15
277	275
278		-#define CONFIG_SOFT_I2C_I2C5_SCL exynos4x12_gpio_part1_get_nr(d0, 3)
279		-#define CONFIG_SOFT_I2C_I2C5_SDA exynos4x12_gpio_part1_get_nr(d0, 2)
280		-#define CONFIG_SOFT_I2C_I2C9_SCL exynos4x12_gpio_part1_get_nr(f1, 4)
281		-#define CONFIG_SOFT_I2C_I2C9_SDA exynos4x12_gpio_part1_get_nr(f1, 5)
282		-#define CONFIG_SOFT_I2C_I2C10_SCL exynos4x12_gpio_part2_get_nr(m2, 1)
283		-#define CONFIG_SOFT_I2C_I2C10_SDA exynos4x12_gpio_part2_get_nr(m2, 0)
284		-#define CONFIG_SOFT_I2C_GPIO_SCL get_multi_scl_pin()
285		-#define CONFIG_SOFT_I2C_GPIO_SDA get_multi_sda_pin()
286		-#define I2C_INIT multi_i2c_init()
	276	+#ifndef __ASSEMBLY__
	277	+int get_soft_i2c_scl_pin(void);
	278	+int get_soft_i2c_sda_pin(void);
	279	+#endif
	280	+#define CONFIG_SOFT_I2C_GPIO_SCL get_soft_i2c_scl_pin()
	281	+#define CONFIG_SOFT_I2C_GPIO_SDA get_soft_i2c_sda_pin()
287	282
288	283	/* POWER */
289	284	#define CONFIG_POWER