Eric Lee / smarc-uboot

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Commit 2d934e5703b712686c3ec67f6d5eeb137c68805d

Authored by Simon Glass
1 parent eea0f11278
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

x86: Rename MMCONF_BASE_ADDRESS and make it common across x86 

This setting will be used by more than just ivybridge so make it common.

Also rename it to PCIE_ECAM_BASE which is a more descriptive name.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Showing 4 changed files with 17 additions and 4 deletions Side-by-side Diff

... ... @@ -356,5 +356,19 @@
356 356  
357 357 source "board/intel/crownbay/Kconfig"
358 358  
  359 +config PCIE_ECAM_BASE
  360 + hex
  361 + default 0xe0000000
  362 + help
  363 + This is the memory-mapped address of PCI configuration space, which
  364 + is only available through the Enhanced Configuration Access
  365 + Mechanism (ECAM) with PCI Express. It can be set up almost
  366 + anywhere. Before it is set up, it is possible to access PCI
  367 + configuration space through I/O access, but memory access is more
  368 + convenient. Using this, PCI can be scanned and configured. This
  369 + should be set to a region that does not conflict with memory
  370 + assigned to PCI devices - i.e. the memory and prefetch regions, as
  371 + passed to pci_set_region().
  372 +
359 373 endmenu
arch/x86/cpu/ivybridge/sdram.c
Diff comments   View file @ 2d934e5
... ... @@ -757,7 +757,7 @@
757 757 .mchbar = DEFAULT_MCHBAR,
758 758 .dmibar = DEFAULT_DMIBAR,
759 759 .epbar = DEFAULT_EPBAR,
760   - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
  760 + .pciexbar = CONFIG_PCIE_ECAM_BASE,
761 761 .smbusbar = SMBUS_IO_BASE,
762 762 .wdbbar = 0x4000000,
763 763 .wdbsize = 0x1000,
arch/x86/include/asm/arch-ivybridge/sandybridge.h
Diff comments   View file @ 2d934e5
... ... @@ -43,7 +43,7 @@
43 43 #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
44 44 #define DEFAULT_RCBABASE 0xfed1c000
45 45 /* 4 KB per PCIe device */
46   -#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS
  46 +#define DEFAULT_PCIEXBAR CONFIG_PCIE_ECAM_BASE
47 47  
48 48 /* Device 0:0.0 PCI configuration space (Host Bridge) */
49 49 #define EPBAR 0x40
board/google/chromebook_link/Kconfig
Diff comments   View file @ 2d934e5
... ... @@ -22,8 +22,7 @@
22 22 select MARK_GRAPHICS_MEM_WRCOMB
23 23 select BOARD_ROMSIZE_KB_8192
24 24  
25   -config MMCONF_BASE_ADDRESS
26   - hex
  25 +config PCIE_ECAM_BASE
27 26 default 0xf0000000
28 27  
29 28 config EARLY_POST_CROS_EC