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Commit 2da0fc0d0fcdd991220cc120e5bc6d44991a5987

Authored by Dirk Eibach
Committed by Stefan Roese
1 parent 42d44f631c
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ppc4xx: Add DLVision-10G board support 

Board support for the Guntermann & Drunck DLVision-10G.
Adds support for multiple FPGAs per board for gdsys 405ep
architecture.
Adds support for dual link osd hardware for gdsys 405ep.

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>

Showing 16 changed files with 994 additions and 166 deletions Side-by-side Diff

... ... @@ -146,6 +146,7 @@
146 146  
147 147 devconcenter PPC460EX
148 148 dlvision PPC405EP
  149 + dlvision-10g PPC405EP
149 150 gdppc440etx PPC440EP/GR
150 151 intip PPC460EX
151 152 io PPC405EP
arch/powerpc/include/asm/global_data.h
Diff comments   View file @ 2da0fc0
... ... @@ -172,6 +172,9 @@
172 172 #if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5)
173 173 unsigned long kbd_status;
174 174 #endif
  175 +#ifdef CONFIG_SYS_FPGA_COUNT
  176 + unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
  177 +#endif
175 178 #if defined(CONFIG_WD_MAX_RATE)
176 179 unsigned long long wdt_last; /* trace watch-dog triggering rate */
177 180 #endif
board/gdsys/405ep/405ep.c
Diff comments   View file @ 2da0fc0
... ... @@ -26,8 +26,9 @@
26 26 #include <asm/processor.h>
27 27 #include <asm/io.h>
28 28 #include <asm/ppc4xx-gpio.h>
  29 +#include <asm/global_data.h>
29 30  
30   -#include "../common/fpga.h"
  31 +#include <gdsys_fpga.h>
31 32  
32 33 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
33 34 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
34 35  
... ... @@ -36,8 +37,29 @@
36 37 #define REFLECTION_TESTPATTERN 0xdede
37 38 #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
38 39  
  40 +DECLARE_GLOBAL_DATA_PTR;
  41 +
  42 +int get_fpga_state(unsigned dev)
  43 +{
  44 + return gd->fpga_state[dev];
  45 +}
  46 +
  47 +void print_fpga_state(unsigned dev)
  48 +{
  49 + if (gd->fpga_state[dev] & FPGA_STATE_DONE_FAILED)
  50 + puts(" Waiting for FPGA-DONE timed out.\n");
  51 + if (gd->fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
  52 + puts(" FPGA reflection test failed.\n");
  53 +}
  54 +
39 55 int board_early_init_f(void)
40 56 {
  57 + unsigned k;
  58 + unsigned ctr;
  59 +
  60 + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
  61 + gd->fpga_state[k] = 0;
  62 +
41 63 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
42 64 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
43 65 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
44 66  
... ... @@ -66,10 +88,18 @@
66 88  
67 89 /*
68 90 * wait for fpga-done
69   - * fail ungraceful if fpga is not configuring properly
70 91 */
71   - while (!(in_le16((void *)LATCH2_BASE) & 0x0010))
72   - ;
  92 + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
  93 + ctr = 0;
  94 + while (!(in_le16((void *)LATCH2_BASE)
  95 + & CONFIG_SYS_FPGA_DONE(k))) {
  96 + udelay(100000);
  97 + if (ctr++ > 5) {
  98 + gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED;
  99 + break;
  100 + }
  101 + }
  102 + }
73 103  
74 104 /*
75 105 * setup io-latches for boot (stop reset)
... ... @@ -78,15 +108,25 @@
78 108 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
79 109 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
80 110  
81   - /*
82   - * wait for fpga out of reset
83   - * fail ungraceful if fpga is not working properly
84   - */
85   - while (1) {
86   - fpga_set_reg(CONFIG_SYS_FPGA_RFL_LOW, REFLECTION_TESTPATTERN);
87   - if (fpga_get_reg(CONFIG_SYS_FPGA_RFL_HIGH) ==
88   - REFLECTION_TESTPATTERN_INV)
89   - break;
  111 + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
  112 + ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k);
  113 + /*
  114 + * wait for fpga out of reset
  115 + */
  116 + ctr = 0;
  117 + while (1) {
  118 + out_le16(&fpga->reflection_low,
  119 + REFLECTION_TESTPATTERN);
  120 + if (in_le16(&fpga->reflection_high) ==
  121 + REFLECTION_TESTPATTERN_INV)
  122 + break;
  123 + udelay(100000);
  124 + if (ctr++ > 5) {
  125 + gd->fpga_state[k] |=
  126 + FPGA_STATE_REFLECTION_FAILED;
  127 + break;
  128 + }
  129 + }
90 130 }
91 131  
92 132 return 0;
board/gdsys/405ep/Makefile
Diff comments   View file @ 2da0fc0
... ... @@ -27,6 +27,7 @@
27 27  
28 28 COBJS-$(CONFIG_IO) += io.o
29 29 COBJS-$(CONFIG_IOCON) += iocon.o
  30 +COBJS-$(CONFIG_DLVISION_10G) += dlvision-10g.o
30 31  
31 32 COBJS := $(BOARD).o $(COBJS-y)
32 33 SOBJS =
board/gdsys/405ep/dlvision-10g.c
Diff comments   View file @ 2da0fc0
  1 +/*
  2 + * (C) Copyright 2010
  3 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#include <common.h>
  25 +#include <command.h>
  26 +#include <asm/processor.h>
  27 +#include <asm/io.h>
  28 +#include <asm/ppc4xx-gpio.h>
  29 +
  30 +#include <gdsys_fpga.h>
  31 +
  32 +#include "../common/osd.h"
  33 +
  34 +enum {
  35 + UNITTYPE_VIDEO_USER = 0,
  36 + UNITTYPE_MAIN_USER = 1,
  37 + UNITTYPE_VIDEO_SERVER = 2,
  38 + UNITTYPE_MAIN_SERVER = 3,
  39 +};
  40 +
  41 +enum {
  42 + HWVER_101 = 0,
  43 + HWVER_110 = 1,
  44 +};
  45 +
  46 +enum {
  47 + AUDIO_NONE = 0,
  48 + AUDIO_TX = 1,
  49 + AUDIO_RX = 2,
  50 + AUDIO_RXTX = 3,
  51 +};
  52 +
  53 +enum {
  54 + SYSCLK_156250 = 2,
  55 +};
  56 +
  57 +enum {
  58 + RAM_NONE = 0,
  59 + RAM_DDR2_32 = 1,
  60 + RAM_DDR2_64 = 2,
  61 +};
  62 +
  63 +static void print_fpga_info(unsigned dev)
  64 +{
  65 + ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev);
  66 + u16 versions = in_le16(&fpga->versions);
  67 + u16 fpga_version = in_le16(&fpga->fpga_version);
  68 + u16 fpga_features = in_le16(&fpga->fpga_features);
  69 + unsigned unit_type;
  70 + unsigned hardware_version;
  71 + unsigned feature_compression;
  72 + unsigned feature_rs232;
  73 + unsigned feature_audio;
  74 + unsigned feature_sysclock;
  75 + unsigned feature_ramconfig;
  76 + unsigned feature_carrier_speed;
  77 + unsigned feature_carriers;
  78 + unsigned feature_video_channels;
  79 + int fpga_state = get_fpga_state(dev);
  80 +
  81 + printf("FPGA%d: ", dev);
  82 +
  83 + hardware_version = versions & 0x000f;
  84 +
  85 + if (fpga_state
  86 + && !((hardware_version == HWVER_101)
  87 + && (fpga_state == FPGA_STATE_DONE_FAILED))) {
  88 + puts("not available\n");
  89 + print_fpga_state(dev);
  90 + return;
  91 + }
  92 +
  93 + unit_type = (versions >> 4) & 0x000f;
  94 + hardware_version = versions & 0x000f;
  95 + feature_compression = (fpga_features >> 13) & 0x0003;
  96 + feature_rs232 = fpga_features & (1<<11);
  97 + feature_audio = (fpga_features >> 9) & 0x0003;
  98 + feature_sysclock = (fpga_features >> 7) & 0x0003;
  99 + feature_ramconfig = (fpga_features >> 5) & 0x0003;
  100 + feature_carrier_speed = fpga_features & (1<<4);
  101 + feature_carriers = (fpga_features >> 2) & 0x0003;
  102 + feature_video_channels = fpga_features & 0x0003;
  103 +
  104 + switch (unit_type) {
  105 + case UNITTYPE_VIDEO_USER:
  106 + printf("Videochannel Userside");
  107 + break;
  108 +
  109 + case UNITTYPE_MAIN_USER:
  110 + printf("Mainchannel Userside");
  111 + break;
  112 +
  113 + case UNITTYPE_VIDEO_SERVER:
  114 + printf("Videochannel Serverside");
  115 + break;
  116 +
  117 + case UNITTYPE_MAIN_SERVER:
  118 + printf("Mainchannel Serverside");
  119 + break;
  120 +
  121 + default:
  122 + printf("UnitType %d(not supported)", unit_type);
  123 + break;
  124 + }
  125 +
  126 + switch (hardware_version) {
  127 + case HWVER_101:
  128 + printf(" HW-Ver 1.01\n");
  129 + break;
  130 +
  131 + case HWVER_110:
  132 + printf(" HW-Ver 1.10\n");
  133 + break;
  134 +
  135 + default:
  136 + printf(" HW-Ver %d(not supported)\n",
  137 + hardware_version);
  138 + break;
  139 + }
  140 +
  141 + printf(" FPGA V %d.%02d, features:",
  142 + fpga_version / 100, fpga_version % 100);
  143 +
  144 + printf(" %sRS232", feature_rs232 ? "" : "no ");
  145 +
  146 + switch (feature_audio) {
  147 + case AUDIO_NONE:
  148 + printf(", no audio");
  149 + break;
  150 +
  151 + case AUDIO_TX:
  152 + printf(", audio tx");
  153 + break;
  154 +
  155 + case AUDIO_RX:
  156 + printf(", audio rx");
  157 + break;
  158 +
  159 + case AUDIO_RXTX:
  160 + printf(", audio rx+tx");
  161 + break;
  162 +
  163 + default:
  164 + printf(", audio %d(not supported)", feature_audio);
  165 + break;
  166 + }
  167 +
  168 + switch (feature_sysclock) {
  169 + case SYSCLK_156250:
  170 + printf(", clock 156.25 MHz");
  171 + break;
  172 +
  173 + default:
  174 + printf(", clock %d(not supported)", feature_sysclock);
  175 + break;
  176 + }
  177 +
  178 + puts(",\n ");
  179 +
  180 + switch (feature_ramconfig) {
  181 + case RAM_NONE:
  182 + printf("no RAM");
  183 + break;
  184 +
  185 + case RAM_DDR2_32:
  186 + printf("RAM 32 bit DDR2");
  187 + break;
  188 +
  189 + case RAM_DDR2_64:
  190 + printf("RAM 64 bit DDR2");
  191 + break;
  192 +
  193 + default:
  194 + printf("RAM %d(not supported)", feature_ramconfig);
  195 + break;
  196 + }
  197 +
  198 + printf(", %d carrier(s) %s", feature_carriers,
  199 + feature_carrier_speed ? "10 Gbit/s" : "of unknown speed");
  200 +
  201 + printf(", %d video channel(s)\n", feature_video_channels);
  202 +}
  203 +
  204 +/*
  205 + * Check Board Identity:
  206 + */
  207 +int checkboard(void)
  208 +{
  209 + unsigned k;
  210 + char *s = getenv("serial#");
  211 +
  212 + printf("Board: ");
  213 +
  214 + printf("DLVision 10G");
  215 +
  216 + if (s != NULL) {
  217 + puts(", serial# ");
  218 + puts(s);
  219 + }
  220 +
  221 + puts("\n");
  222 +
  223 + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
  224 + print_fpga_info(k);
  225 +
  226 + return 0;
  227 +}
  228 +
  229 +int last_stage_init(void)
  230 +{
  231 + unsigned k;
  232 +
  233 + for (k = 0; k < CONFIG_SYS_OSD_SCREENS; ++k)
  234 + if (!get_fpga_state(k)
  235 + || (get_fpga_state(k) == FPGA_STATE_DONE_FAILED))
  236 + osd_probe(k);
  237 +
  238 + return 0;
  239 +}
board/gdsys/405ep/io.c
Diff comments   View file @ 2da0fc0
... ... @@ -29,7 +29,7 @@
29 29  
30 30 #include <miiphy.h>
31 31  
32   -#include "../common/fpga.h"
  32 +#include <gdsys_fpga.h>
33 33  
34 34 #define PHYREG_CONTROL 0
35 35 #define PHYREG_PAGE_ADDRESS 22
... ... @@ -37,13 +37,6 @@
37 37 #define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
38 38  
39 39 enum {
40   - REG_VERSIONS = 0x0002,
41   - REG_FPGA_FEATURES = 0x0004,
42   - REG_FPGA_VERSION = 0x0006,
43   - REG_QUAD_SERDES_RESET = 0x0012,
44   -};
45   -
46   -enum {
47 40 UNITTYPE_CCD_SWITCH = 1,
48 41 };
49 42  
50 43  
... ... @@ -94,10 +87,11 @@
94 87 */
95 88 int checkboard(void)
96 89 {
  90 + ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
97 91 char *s = getenv("serial#");
98   - u16 versions = fpga_get_reg(REG_VERSIONS);
99   - u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
100   - u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
  92 + u16 versions = in_le16(&fpga->versions);
  93 + u16 fpga_version = in_le16(&fpga->fpga_version);
  94 + u16 fpga_features = in_le16(&fpga->fpga_features);
101 95 unsigned unit_type;
102 96 unsigned hardware_version;
103 97 unsigned feature_channels;
... ... @@ -166,6 +160,7 @@
166 160 */
167 161 int last_stage_init(void)
168 162 {
  163 + ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
169 164 unsigned int k;
170 165  
171 166 miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
... ... @@ -175,7 +170,7 @@
175 170 configure_gbit_phy(k);
176 171  
177 172 /* take fpga serdes blocks out of reset */
178   - fpga_set_reg(REG_QUAD_SERDES_RESET, 0);
  173 + out_le16(&fpga->quad_serdes_reset, 0);
179 174  
180 175 return 0;
181 176 }
board/gdsys/405ep/iocon.c
Diff comments   View file @ 2da0fc0
... ... @@ -27,16 +27,11 @@
27 27 #include <asm/io.h>
28 28 #include <asm/ppc4xx-gpio.h>
29 29  
30   -#include "../common/fpga.h"
  30 +#include <gdsys_fpga.h>
  31 +
31 32 #include "../common/osd.h"
32 33  
33 34 enum {
34   - REG_VERSIONS = 0x0002,
35   - REG_FPGA_VERSION = 0x0004,
36   - REG_FPGA_FEATURES = 0x0006,
37   -};
38   -
39   -enum {
40 35 UNITTYPE_MAIN_SERVER = 0,
41 36 UNITTYPE_MAIN_USER = 1,
42 37 UNITTYPE_VIDEO_SERVER = 2,
43 38  
... ... @@ -74,10 +69,11 @@
74 69 */
75 70 int checkboard(void)
76 71 {
  72 + ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
77 73 char *s = getenv("serial#");
78   - u16 versions = fpga_get_reg(REG_VERSIONS);
79   - u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
80   - u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
  74 + u16 versions = in_le16(&fpga->versions);
  75 + u16 fpga_version = in_le16(&fpga->fpga_version);
  76 + u16 fpga_features = in_le16(&fpga->fpga_features);
81 77 unsigned unit_type;
82 78 unsigned hardware_version;
83 79 unsigned feature_compression;
... ... @@ -214,7 +210,7 @@
214 210  
215 211 int last_stage_init(void)
216 212 {
217   - return osd_probe();
  213 + return osd_probe(0);
218 214 }
219 215  
220 216 /*
221 217  
222 218  
... ... @@ -222,16 +218,16 @@
222 218 */
223 219 void fpga_gpio_set(int pin)
224 220 {
225   - out_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x18), pin);
  221 + out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x18), pin);
226 222 }
227 223  
228 224 void fpga_gpio_clear(int pin)
229 225 {
230   - out_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x16), pin);
  226 + out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x16), pin);
231 227 }
232 228  
233 229 int fpga_gpio_get(int pin)
234 230 {
235   - return in_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x14)) & pin;
  231 + return in_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x14)) & pin;
236 232 }
board/gdsys/common/Makefile
Diff comments   View file @ 2da0fc0
... ... @@ -31,6 +31,7 @@
31 31  
32 32 COBJS-$(CONFIG_IO) += miiphybb.o
33 33 COBJS-$(CONFIG_IOCON) += osd.o
  34 +COBJS-$(CONFIG_DLVISION_10G) += osd.o
34 35  
35 36 COBJS := $(COBJS-y)
36 37 SOBJS =
board/gdsys/common/fpga.h
View file @ 2da0fc0
1   -/*
2   - * (C) Copyright 2010
3   - * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4   - *
5   - * See file CREDITS for list of people who contributed to this
6   - * project.
7   - *
8   - * This program is free software; you can redistribute it and/or
9   - * modify it under the terms of the GNU General Public License as
10   - * published by the Free Software Foundation; either version 2 of
11   - * the License, or (at your option) any later version.
12   - *
13   - * This program is distributed in the hope that it will be useful,
14   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
15   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   - * GNU General Public License for more details.
17   - *
18   - * You should have received a copy of the GNU General Public License
19   - * along with this program; if not, write to the Free Software
20   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   - * MA 02111-1307 USA
22   - */
23   -
24   -#ifndef _FPGA_H_
25   -#define _FPGA_H_
26   -
27   -static inline u16 fpga_get_reg(unsigned reg)
28   -{
29   - return in_le16((void *)(CONFIG_SYS_FPGA_BASE + reg));
30   -}
31   -
32   -static inline void fpga_set_reg(unsigned reg, u16 val)
33   -{
34   - return out_le16((void *)(CONFIG_SYS_FPGA_BASE + reg), val);
35   -}
36   -
37   -#endif
board/gdsys/common/osd.c
Diff comments   View file @ 2da0fc0
... ... @@ -25,10 +25,16 @@
25 25 #include <i2c.h>
26 26 #include <asm/io.h>
27 27  
28   -#include "fpga.h"
  28 +#include <gdsys_fpga.h>
29 29  
30 30 #define CH7301_I2C_ADDR 0x75
31 31  
  32 +#define ICS8N3QV01_I2C_ADDR 0x6E
  33 +#define ICS8N3QV01_FREF 114285
  34 +
  35 +#define SIL1178_MASTER_I2C_ADDRESS 0x38
  36 +#define SIL1178_SLAVE_I2C_ADDRESS 0x39
  37 +
32 38 #define PIXCLK_640_480_60 25180000
33 39  
34 40 #define BASE_WIDTH 32
... ... @@ -36,17 +42,6 @@
36 42 #define BUFSIZE (BASE_WIDTH * BASE_HEIGHT)
37 43  
38 44 enum {
39   - REG_CONTROL = 0x0010,
40   - REG_MPC3W_CONTROL = 0x001a,
41   - REG_VIDEOCONTROL = 0x0042,
42   - REG_OSDVERSION = 0x0100,
43   - REG_OSDFEATURES = 0x0102,
44   - REG_OSDCONTROL = 0x0104,
45   - REG_XY_SIZE = 0x0106,
46   - REG_VIDEOMEM = 0x0800,
47   -};
48   -
49   -enum {
50 45 CH7301_CM = 0x1c, /* Clock Mode Register */
51 46 CH7301_IC = 0x1d, /* Input Clock Register */
52 47 CH7301_GPIO = 0x1e, /* GPIO Control Register */
... ... @@ -67,6 +62,41 @@
67 62 CH7301_DSP = 0x56, /* DVI Sync polarity Register */
68 63 };
69 64  
  65 +#if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178)
  66 +static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data)
  67 +{
  68 + ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
  69 + ihs_i2c_t *i2c = &fpga->i2c;
  70 +
  71 + while (in_le16(&fpga->extended_interrupt) & (1 << 12))
  72 + ;
  73 + out_le16(&i2c->write_mailbox_ext, reg | (data << 8));
  74 + out_le16(&i2c->write_mailbox, 0xc400 | (slave << 1));
  75 +}
  76 +
  77 +static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg)
  78 +{
  79 + ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
  80 + ihs_i2c_t *i2c = &fpga->i2c;
  81 + unsigned int ctr = 0;
  82 +
  83 + while (in_le16(&fpga->extended_interrupt) & (1 << 12))
  84 + ;
  85 + out_le16(&fpga->extended_interrupt, 1 << 14);
  86 + out_le16(&i2c->write_mailbox_ext, reg);
  87 + out_le16(&i2c->write_mailbox, 0xc000 | (slave << 1));
  88 + while (!(in_le16(&fpga->extended_interrupt) & (1 << 14))) {
  89 + udelay(100000);
  90 + if (ctr++ > 5) {
  91 + printf("iic receive timeout\n");
  92 + break;
  93 + }
  94 + }
  95 + return in_le16(&i2c->read_mailbox_ext) >> 8;
  96 +}
  97 +#endif
  98 +
  99 +#ifdef CONFIG_SYS_MPC92469AC
70 100 static void mpc92469ac_calc_parameters(unsigned int fout,
71 101 unsigned int *post_div, unsigned int *feedback_div)
72 102 {
73 103  
... ... @@ -92,8 +122,9 @@
92 122 *feedback_div = m;
93 123 }
94 124  
95   -static void mpc92469ac_set(unsigned int fout)
  125 +static void mpc92469ac_set(unsigned screen, unsigned int fout)
96 126 {
  127 + ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
97 128 unsigned int n;
98 129 unsigned int m;
99 130 unsigned int bitval = 0;
100 131  
101 132  
102 133  
103 134  
... ... @@ -114,17 +145,85 @@
114 145 break;
115 146 }
116 147  
117   - fpga_set_reg(REG_MPC3W_CONTROL, (bitval << 9) | m);
  148 + out_le16(&fpga->mpc3w_control, (bitval << 9) | m);
118 149 }
  150 +#endif
119 151  
120   -static int osd_write_videomem(unsigned offset, u16 *data, size_t charcount)
  152 +#ifdef CONFIG_SYS_ICS8N3QV01
  153 +static void ics8n3qv01_calc_parameters(unsigned int fout,
  154 + unsigned int *_mint, unsigned int *_mfrac,
  155 + unsigned int *_n)
121 156 {
  157 + unsigned int n;
  158 + unsigned int foutiic;
  159 + unsigned int fvcoiic;
  160 + unsigned int mint;
  161 + unsigned long long mfrac;
  162 +
  163 + n = 2550000000U / fout;
  164 + if ((n & 1) && (n > 5))
  165 + n -= 1;
  166 +
  167 + foutiic = fout - (fout / 10000);
  168 + fvcoiic = foutiic * n;
  169 +
  170 + mint = fvcoiic / 114285000;
  171 + if ((mint < 17) || (mint > 63))
  172 + printf("ics8n3qv01_calc_parameters: cannot determine mint\n");
  173 +
  174 + mfrac = ((unsigned long long)fvcoiic % 114285000LL) * 262144LL
  175 + / 114285000LL;
  176 +
  177 + *_mint = mint;
  178 + *_mfrac = mfrac;
  179 + *_n = n;
  180 +}
  181 +
  182 +static void ics8n3qv01_set(unsigned screen, unsigned int fout)
  183 +{
  184 + unsigned int n;
  185 + unsigned int mint;
  186 + unsigned int mfrac;
  187 + u8 reg0, reg4, reg8, reg12, reg18, reg20;
  188 +
  189 + ics8n3qv01_calc_parameters(fout, &mint, &mfrac, &n);
  190 +
  191 + reg0 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0) & 0xc0;
  192 + reg0 |= (mint & 0x1f) << 1;
  193 + reg0 |= (mfrac >> 17) & 0x01;
  194 + fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 0, reg0);
  195 +
  196 + reg4 = mfrac >> 9;
  197 + fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 4, reg4);
  198 +
  199 + reg8 = mfrac >> 1;
  200 + fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 8, reg8);
  201 +
  202 + reg12 = mfrac << 7;
  203 + reg12 |= n & 0x7f;
  204 + fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 12, reg12);
  205 +
  206 + reg18 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 18) & 0x03;
  207 + reg18 |= 0x20;
  208 + fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 18, reg18);
  209 +
  210 + reg20 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20) & 0x1f;
  211 + reg20 |= mint & (1 << 5);
  212 + fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 20, reg20);
  213 +}
  214 +#endif
  215 +
  216 +static int osd_write_videomem(unsigned screen, unsigned offset,
  217 + u16 *data, size_t charcount)
  218 +{
  219 + ihs_fpga_t *fpga =
  220 + (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
122 221 unsigned int k;
123 222  
124 223 for (k = 0; k < charcount; ++k) {
125 224 if (offset + k >= BUFSIZE)
126 225 return -1;
127   - fpga_set_reg(REG_VIDEOMEM + 2 * (offset + k), data[k]);
  226 + out_le16(&fpga->videomem + offset + k, data[k]);
128 227 }
129 228  
130 229 return charcount;
131 230  
132 231  
133 232  
134 233  
135 234  
136 235  
137 236  
138 237  
139 238  
... ... @@ -132,46 +231,59 @@
132 231  
133 232 static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
134 233 {
135   - unsigned x;
136   - unsigned y;
137   - unsigned charcount;
138   - unsigned len;
139   - u8 color;
140   - unsigned int k;
141   - u16 buf[BUFSIZE];
142   - char *text;
  234 + unsigned screen;
143 235  
144   - if (argc < 5) {
145   - return cmd_usage(cmdtp);
146   - }
  236 + for (screen = 0; screen < CONFIG_SYS_OSD_SCREENS; ++screen) {
  237 + unsigned x;
  238 + unsigned y;
  239 + unsigned charcount;
  240 + unsigned len;
  241 + u8 color;
  242 + unsigned int k;
  243 + u16 buf[BUFSIZE];
  244 + char *text;
  245 + int res;
147 246  
148   - x = simple_strtoul(argv[1], NULL, 16);
149   - y = simple_strtoul(argv[2], NULL, 16);
150   - color = simple_strtoul(argv[3], NULL, 16);
151   - text = argv[4];
152   - charcount = strlen(text);
153   - len = (charcount > BUFSIZE) ? BUFSIZE : charcount;
  247 + if (argc < 5) {
  248 + cmd_usage(cmdtp);
  249 + return 1;
  250 + }
154 251  
155   - for (k = 0; k < len; ++k)
156   - buf[k] = (text[k] << 8) | color;
  252 + x = simple_strtoul(argv[1], NULL, 16);
  253 + y = simple_strtoul(argv[2], NULL, 16);
  254 + color = simple_strtoul(argv[3], NULL, 16);
  255 + text = argv[4];
  256 + charcount = strlen(text);
  257 + len = (charcount > BUFSIZE) ? BUFSIZE : charcount;
157 258  
158   - return osd_write_videomem(y * BASE_WIDTH + x, buf, len);
  259 + for (k = 0; k < len; ++k)
  260 + buf[k] = (text[k] << 8) | color;
  261 +
  262 + res = osd_write_videomem(screen, y * BASE_WIDTH + x, buf, len);
  263 + if (res < 0)
  264 + return res;
  265 + }
  266 +
  267 + return 0;
159 268 }
160 269  
161   -int osd_probe(void)
  270 +int osd_probe(unsigned screen)
162 271 {
163   - u8 value;
164   - u16 version = fpga_get_reg(REG_OSDVERSION);
165   - u16 features = fpga_get_reg(REG_OSDFEATURES);
  272 + ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
  273 + ihs_osd_t *osd = &fpga->osd;
  274 + u16 version = in_le16(&osd->version);
  275 + u16 features = in_le16(&osd->features);
166 276 unsigned width;
167 277 unsigned height;
  278 + u8 value;
168 279  
169 280 width = ((features & 0x3f00) >> 8) + 1;
170 281 height = (features & 0x001f) + 1;
171 282  
172   - printf("OSD: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
173   - version/100, version%100, width, height);
  283 + printf("OSD%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
  284 + screen, version/100, version%100, width, height);
174 285  
  286 +#ifdef CONFIG_SYS_CH7301
175 287 value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
176 288 if (value != 0x17) {
177 289 printf(" Probing CH7301 failed, DID %02x\n", value);
178 290  
179 291  
180 292  
181 293  
182 294  
183 295  
184 296  
185 297  
186 298  
187 299  
188 300  
... ... @@ -182,51 +294,86 @@
182 294 i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
183 295 i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
184 296 i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
  297 +#endif
185 298  
186   - mpc92469ac_set(PIXCLK_640_480_60);
187   - fpga_set_reg(REG_VIDEOCONTROL, 0x0002);
188   - fpga_set_reg(REG_OSDCONTROL, 0x0049);
  299 +#ifdef CONFIG_SYS_MPC92469AC
  300 + mpc92469ac_set(screen, PIXCLK_640_480_60);
  301 +#endif
189 302  
190   - fpga_set_reg(REG_XY_SIZE, ((32 - 1) << 8) | (16 - 1));
  303 +#ifdef CONFIG_SYS_ICS8N3QV01
  304 + ics8n3qv01_set(screen, PIXCLK_640_480_60);
  305 +#endif
191 306  
  307 +#ifdef CONFIG_SYS_SIL1178
  308 + value = fpga_iic_read(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x02);
  309 + if (value != 0x06) {
  310 + printf(" Probing CH7301 SIL1178, DEV_IDL %02x\n", value);
  311 + return -1;
  312 + }
  313 + /* magic initialization sequence adapted from datasheet */
  314 + fpga_iic_write(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
  315 + fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
  316 + fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
  317 + fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
  318 + fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
  319 + fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
  320 + fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
  321 + fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
  322 + fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
  323 + fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
  324 +#endif
  325 +
  326 + out_le16(&fpga->videocontrol, 0x0002);
  327 + out_le16(&osd->control, 0x0049);
  328 +
  329 + out_le16(&osd->xy_size, ((32 - 1) << 8) | (16 - 1));
  330 +
192 331 return 0;
193 332 }
194 333  
195 334 int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
196 335 {
197   - unsigned x;
198   - unsigned y;
199   - unsigned k;
200   - u16 buffer[BASE_WIDTH];
201   - char *rp;
202   - u16 *wp = buffer;
203   - unsigned count = (argc > 4) ? simple_strtoul(argv[4], NULL, 16) : 1;
  336 + unsigned screen;
204 337  
205   - if ((argc < 4) || (strlen(argv[3]) % 4)) {
206   - return cmd_usage(cmdtp);
207   - }
  338 + for (screen = 0; screen < CONFIG_SYS_OSD_SCREENS; ++screen) {
  339 + unsigned x;
  340 + unsigned y;
  341 + unsigned k;
  342 + u16 buffer[BASE_WIDTH];
  343 + char *rp;
  344 + u16 *wp = buffer;
  345 + unsigned count = (argc > 4) ?
  346 + simple_strtoul(argv[4], NULL, 16) : 1;
208 347  
209   - x = simple_strtoul(argv[1], NULL, 16);
210   - y = simple_strtoul(argv[2], NULL, 16);
211   - rp = argv[3];
  348 + if ((argc < 4) || (strlen(argv[3]) % 4)) {
  349 + cmd_usage(cmdtp);
  350 + return 1;
  351 + }
212 352  
  353 + x = simple_strtoul(argv[1], NULL, 16);
  354 + y = simple_strtoul(argv[2], NULL, 16);
  355 + rp = argv[3];
213 356  
214   - while (*rp) {
215   - char substr[5];
216 357  
217   - memcpy(substr, rp, 4);
218   - substr[4] = 0;
219   - *wp = simple_strtoul(substr, NULL, 16);
  358 + while (*rp) {
  359 + char substr[5];
220 360  
221   - rp += 4;
222   - wp++;
223   - if (wp - buffer > BASE_WIDTH)
224   - break;
225   - }
  361 + memcpy(substr, rp, 4);
  362 + substr[4] = 0;
  363 + *wp = simple_strtoul(substr, NULL, 16);
226 364  
227   - for (k = 0; k < count; ++k) {
228   - unsigned offset = y * BASE_WIDTH + x + k * (wp - buffer);
229   - osd_write_videomem(offset, buffer, wp - buffer);
  365 + rp += 4;
  366 + wp++;
  367 + if (wp - buffer > BASE_WIDTH)
  368 + break;
  369 + }
  370 +
  371 + for (k = 0; k < count; ++k) {
  372 + unsigned offset =
  373 + y * BASE_WIDTH + x + k * (wp - buffer);
  374 + osd_write_videomem(screen, offset, buffer,
  375 + wp - buffer);
  376 + }
230 377 }
231 378  
232 379 return 0;
board/gdsys/common/osd.h
Diff comments   View file @ 2da0fc0
... ... @@ -24,7 +24,7 @@
24 24 #ifndef _OSD_H_
25 25 #define _OSD_H_
26 26  
27   -int osd_probe(void);
  27 +int osd_probe(unsigned screen);
28 28  
29 29 #endif
... ... @@ -717,6 +717,7 @@
717 717 WUH405 powerpc ppc4xx wuh405 esd
718 718 devconcenter powerpc ppc4xx intip gdsys - intip:DEVCONCENTER
719 719 dlvision powerpc ppc4xx - gdsys
  720 +dlvision-10g powerpc ppc4xx 405ep gdsys
720 721 gdppc440etx powerpc ppc4xx - gdsys
721 722 intip powerpc ppc4xx intip gdsys - intip:INTIB
722 723 io powerpc ppc4xx 405ep gdsys
include/configs/dlvision-10g.h
Diff comments   View file @ 2da0fc0
  1 +/*
  2 + * (C) Copyright 2010
  3 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#ifndef __CONFIG_H
  25 +#define __CONFIG_H
  26 +
  27 +#define CONFIG_405EP 1 /* this is a PPC405 CPU */
  28 +#define CONFIG_4xx 1 /* member of PPC4xx family */
  29 +#define CONFIG_DLVISION_10G 1 /* on a DLVision-10G board */
  30 +
  31 +#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
  32 +
  33 +/*
  34 + * Include common defines/options for all AMCC eval boards
  35 + */
  36 +#define CONFIG_HOSTNAME dlvsion-10g
  37 +#define CONFIG_IDENT_STRING " dlvision-10g 0.01"
  38 +#include "amcc-common.h"
  39 +
  40 +#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
  41 +#define CONFIG_LAST_STAGE_INIT
  42 +
  43 +#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
  44 +
  45 +/*
  46 + * Configure PLL
  47 + */
  48 +#define PLLMR0_DEFAULT PLLMR0_266_133_66
  49 +#define PLLMR1_DEFAULT PLLMR1_266_133_66
  50 +
  51 +/* new uImage format support */
  52 +#define CONFIG_FIT
  53 +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
  54 +
  55 +#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
  56 +
  57 +/*
  58 + * Default environment variables
  59 + */
  60 +#define CONFIG_EXTRA_ENV_SETTINGS \
  61 + CONFIG_AMCC_DEF_ENV \
  62 + CONFIG_AMCC_DEF_ENV_POWERPC \
  63 + CONFIG_AMCC_DEF_ENV_NOR_UPD \
  64 + "kernel_addr=fc000000\0" \
  65 + "fdt_addr=fc1e0000\0" \
  66 + "ramdisk_addr=fc200000\0" \
  67 + ""
  68 +
  69 +#define CONFIG_PHY_ADDR 4 /* PHY address */
  70 +#define CONFIG_HAS_ETH0
  71 +#define CONFIG_HAS_ETH1
  72 +#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */
  73 +#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
  74 +
  75 +/*
  76 + * Commands additional to the ones defined in amcc-common.h
  77 + */
  78 +#define CONFIG_CMD_CACHE
  79 +#undef CONFIG_CMD_EEPROM
  80 +
  81 +/*
  82 + * SDRAM configuration (please see cpu/ppc/sdram.[ch])
  83 + */
  84 +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
  85 +
  86 +/* SDRAM timings used in datasheet */
  87 +#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
  88 +#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
  89 +#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
  90 +#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
  91 +#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
  92 +
  93 +/*
  94 + * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
  95 + * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
  96 + * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
  97 + * The Linux BASE_BAUD define should match this configuration.
  98 + * baseBaud = cpuClock/(uartDivisor*16)
  99 + * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
  100 + * set Linux BASE_BAUD to 403200.
  101 + */
  102 +#define CONFIG_CONS_INDEX 1 /* Use UART0 */
  103 +#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
  104 +#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
  105 +#define CONFIG_SYS_BASE_BAUD 691200
  106 +
  107 +/*
  108 + * I2C stuff
  109 + */
  110 +#define CONFIG_SYS_I2C_SPEED 100000
  111 +
  112 +/* Temp sensor/hwmon/dtt */
  113 +#define CONFIG_DTT_LM63 1 /* National LM63 */
  114 +#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */
  115 +#define CONFIG_DTT_PWM_LOOKUPTABLE \
  116 + { { 40, 10 }, { 50, 20 }, { 60, 40 } }
  117 +#define CONFIG_DTT_TACH_LIMIT 0xa10
  118 +
  119 +/* EBC peripherals */
  120 +
  121 +#define CONFIG_SYS_FLASH_BASE 0xFC000000
  122 +#define CONFIG_SYS_FPGA0_BASE 0x7f100000
  123 +#define CONFIG_SYS_FPGA1_BASE 0x7f200000
  124 +#define CONFIG_SYS_LATCH_BASE 0x7f300000
  125 +
  126 +#define CONFIG_SYS_FPGA_BASE(k) \
  127 + (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
  128 +
  129 +#define CONFIG_SYS_FPGA_DONE(k) \
  130 + (k ? 0x2000 : 0x1000)
  131 +
  132 +#define CONFIG_SYS_FPGA_COUNT 2
  133 +
  134 +#define CONFIG_SYS_LATCH0_RESET 0xffff
  135 +#define CONFIG_SYS_LATCH0_BOOT 0xffff
  136 +#define CONFIG_SYS_LATCH1_RESET 0xffcf
  137 +#define CONFIG_SYS_LATCH1_BOOT 0xffff
  138 +
  139 +/*
  140 + * FLASH organization
  141 + */
  142 +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
  143 +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
  144 +
  145 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
  146 +
  147 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
  148 +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
  149 +
  150 +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
  151 +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
  152 +
  153 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
  154 +#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protect */
  155 +
  156 +#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
  157 +#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
  158 +
  159 +#ifdef CONFIG_ENV_IS_IN_FLASH
  160 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
  161 +#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
  162 +#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
  163 +
  164 +/* Address and size of Redundant Environment Sector */
  165 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
  166 +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  167 +#endif
  168 +
  169 +/*
  170 + * PPC405 GPIO Configuration
  171 + */
  172 +#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
  173 +{ \
  174 +/* GPIO Core 0 */ \
  175 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
  176 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
  177 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
  178 +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
  179 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
  180 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
  181 +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
  182 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
  183 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
  184 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
  185 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
  186 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
  187 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
  188 +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
  189 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
  190 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
  191 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
  192 +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
  193 +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
  194 +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
  195 +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
  196 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
  197 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
  198 +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
  199 +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
  200 +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
  201 +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
  202 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
  203 +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
  204 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
  205 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
  206 +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
  207 +} \
  208 +}
  209 +
  210 +/*
  211 + * Definitions for initial stack pointer and data area (in data cache)
  212 + */
  213 +/* use on chip memory (OCM) for temperary stack until sdram is tested */
  214 +#define CONFIG_SYS_TEMP_STACK_OCM 1
  215 +
  216 +/* On Chip Memory location */
  217 +#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
  218 +#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
  219 +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
  220 +#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
  221 +
  222 +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/
  223 +#define CONFIG_SYS_GBL_DATA_OFFSET \
  224 + (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  225 +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  226 +
  227 +/*
  228 + * External Bus Controller (EBC) Setup
  229 + */
  230 +
  231 +/* Memory Bank 0 (NOR-flash) */
  232 +#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_ENABLED | \
  233 + EBC_BXAP_FWT_ENCODE(8) | \
  234 + EBC_BXAP_BWT_ENCODE(7) | \
  235 + EBC_BXAP_BCE_DISABLE | \
  236 + EBC_BXAP_BCT_2TRANS | \
  237 + EBC_BXAP_CSN_ENCODE(0) | \
  238 + EBC_BXAP_OEN_ENCODE(2) | \
  239 + EBC_BXAP_WBN_ENCODE(2) | \
  240 + EBC_BXAP_WBF_ENCODE(2) | \
  241 + EBC_BXAP_TH_ENCODE(4) | \
  242 + EBC_BXAP_RE_DISABLED | \
  243 + EBC_BXAP_SOR_NONDELAYED | \
  244 + EBC_BXAP_BEM_WRITEONLY | \
  245 + EBC_BXAP_PEN_DISABLED)
  246 +#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
  247 + EBC_BXCR_BS_64MB | \
  248 + EBC_BXCR_BU_RW | \
  249 + EBC_BXCR_BW_16BIT)
  250 +
  251 +/* Memory Bank 1 (FPGA0) */
  252 +#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
  253 + EBC_BXAP_TWT_ENCODE(5) | \
  254 + EBC_BXAP_BCE_DISABLE | \
  255 + EBC_BXAP_BCT_2TRANS | \
  256 + EBC_BXAP_CSN_ENCODE(0) | \
  257 + EBC_BXAP_OEN_ENCODE(2) | \
  258 + EBC_BXAP_WBN_ENCODE(1) | \
  259 + EBC_BXAP_WBF_ENCODE(1) | \
  260 + EBC_BXAP_TH_ENCODE(0) | \
  261 + EBC_BXAP_RE_DISABLED | \
  262 + EBC_BXAP_SOR_NONDELAYED | \
  263 + EBC_BXAP_BEM_WRITEONLY | \
  264 + EBC_BXAP_PEN_DISABLED)
  265 +#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
  266 + EBC_BXCR_BS_1MB | \
  267 + EBC_BXCR_BU_RW | \
  268 + EBC_BXCR_BW_16BIT)
  269 +
  270 +/* Memory Bank 2 (FPGA1) */
  271 +#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \
  272 + EBC_BXAP_TWT_ENCODE(6) | \
  273 + EBC_BXAP_BCE_DISABLE | \
  274 + EBC_BXAP_BCT_2TRANS | \
  275 + EBC_BXAP_CSN_ENCODE(0) | \
  276 + EBC_BXAP_OEN_ENCODE(2) | \
  277 + EBC_BXAP_WBN_ENCODE(1) | \
  278 + EBC_BXAP_WBF_ENCODE(1) | \
  279 + EBC_BXAP_TH_ENCODE(0) | \
  280 + EBC_BXAP_RE_DISABLED | \
  281 + EBC_BXAP_SOR_NONDELAYED | \
  282 + EBC_BXAP_BEM_WRITEONLY | \
  283 + EBC_BXAP_PEN_DISABLED)
  284 +#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
  285 + EBC_BXCR_BS_1MB | \
  286 + EBC_BXCR_BU_RW | \
  287 + EBC_BXCR_BW_16BIT)
  288 +
  289 +/* Memory Bank 3 (Latches) */
  290 +#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_ENABLED | \
  291 + EBC_BXAP_FWT_ENCODE(8) | \
  292 + EBC_BXAP_BWT_ENCODE(4) | \
  293 + EBC_BXAP_BCE_DISABLE | \
  294 + EBC_BXAP_BCT_2TRANS | \
  295 + EBC_BXAP_CSN_ENCODE(0) | \
  296 + EBC_BXAP_OEN_ENCODE(1) | \
  297 + EBC_BXAP_WBN_ENCODE(1) | \
  298 + EBC_BXAP_WBF_ENCODE(1) | \
  299 + EBC_BXAP_TH_ENCODE(2) | \
  300 + EBC_BXAP_RE_DISABLED | \
  301 + EBC_BXAP_SOR_NONDELAYED | \
  302 + EBC_BXAP_BEM_WRITEONLY | \
  303 + EBC_BXAP_PEN_DISABLED)
  304 +#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
  305 + EBC_BXCR_BS_1MB | \
  306 + EBC_BXCR_BU_RW | \
  307 + EBC_BXCR_BW_16BIT)
  308 +
  309 +/*
  310 + * OSD Setup
  311 + */
  312 +#define CONFIG_SYS_ICS8N3QV01
  313 +#define CONFIG_SYS_SIL1178
  314 +#define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT
  315 +
  316 +#endif /* __CONFIG_H */
include/configs/io.h
Diff comments   View file @ 2da0fc0
... ... @@ -229,13 +229,15 @@
229 229 #define CONFIG_SYS_EBC_PB1CR 0x7f318000
230 230  
231 231 /* Memory Bank 2 (FPGA) initialization */
232   -#define CONFIG_SYS_FPGA_BASE 0x7f100000
  232 +#define CONFIG_SYS_FPGA0_BASE 0x7f100000
233 233 #define CONFIG_SYS_EBC_PB2AP 0x02025080
234 234 /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
235 235 #define CONFIG_SYS_EBC_PB2CR 0x7f11a000
236 236  
237   -#define CONFIG_SYS_FPGA_RFL_LOW 0x0000
238   -#define CONFIG_SYS_FPGA_RFL_HIGH 0x3ffe
  237 +#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
  238 +#define CONFIG_SYS_FPGA_DONE(k) 0x0010
  239 +
  240 +#define CONFIG_SYS_FPGA_COUNT 1
239 241  
240 242 /* Memory Bank 3 (Latches) initialization */
241 243 #define CONFIG_SYS_LATCH_BASE 0x7f200000
include/configs/iocon.h
Diff comments   View file @ 2da0fc0
... ... @@ -131,6 +131,12 @@
131 131 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
132 132  
133 133 /*
  134 + * OSD hardware
  135 + */
  136 +#define CONFIG_SYS_MPC92469AC
  137 +#define CONFIG_SYS_CH7301
  138 +
  139 +/*
134 140 * FLASH organization
135 141 */
136 142 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
137 143  
138 144  
139 145  
... ... @@ -231,14 +237,16 @@
231 237 #define CONFIG_SYS_EBC_PB1AP 0x92015480
232 238 #define CONFIG_SYS_EBC_PB1CR 0xFB858000
233 239  
234   -/* Memory Bank 2 (FPGA) initialization */
235   -#define CONFIG_SYS_FPGA_BASE 0x7f100000
  240 +/* Memory Bank 2 (FPGA0) initialization */
  241 +#define CONFIG_SYS_FPGA0_BASE 0x7f100000
236 242 #define CONFIG_SYS_EBC_PB2AP 0x02825080
237   -#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE | 0x1a000)
  243 +#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA0_BASE | 0x1a000)
238 244  
239   -#define CONFIG_SYS_FPGA_RFL_LOW 0x0000
240   -#define CONFIG_SYS_FPGA_RFL_HIGH 0x00fe
  245 +#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
  246 +#define CONFIG_SYS_FPGA_DONE(k) 0x0010
241 247  
  248 +#define CONFIG_SYS_FPGA_COUNT 1
  249 +
242 250 /* Memory Bank 3 (Latches) initialization */
243 251 #define CONFIG_SYS_LATCH_BASE 0x7f200000
244 252 #define CONFIG_SYS_EBC_PB3AP 0x02025080
... ... @@ -248,6 +256,13 @@
248 256 #define CONFIG_SYS_LATCH0_BOOT 0xffff
249 257 #define CONFIG_SYS_LATCH1_RESET 0xffff
250 258 #define CONFIG_SYS_LATCH1_BOOT 0xffff
  259 +
  260 +/*
  261 + * OSD Setup
  262 + */
  263 +#define CONFIG_SYS_MPC92469AC
  264 +#define CONFIG_SYS_CH7301
  265 +#define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT
251 266  
252 267 #endif /* __CONFIG_H */
include/gdsys_fpga.h
Diff comments   View file @ 2da0fc0
  1 +/*
  2 + * (C) Copyright 2010
  3 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#ifndef __GDSYS_FPGA_H
  25 +#define __GDSYS_FPGA_H
  26 +
  27 +enum {
  28 + FPGA_STATE_DONE_FAILED = 1 << 0,
  29 + FPGA_STATE_REFLECTION_FAILED = 1 << 1,
  30 +};
  31 +
  32 +int get_fpga_state(unsigned dev);
  33 +void print_fpga_state(unsigned dev);
  34 +
  35 +typedef struct ihs_gpio {
  36 + u16 read;
  37 + u16 clear;
  38 + u16 set;
  39 +} ihs_gpio_t;
  40 +
  41 +typedef struct ihs_i2c {
  42 + u16 write_mailbox;
  43 + u16 write_mailbox_ext;
  44 + u16 read_mailbox;
  45 + u16 read_mailbox_ext;
  46 +} ihs_i2c_t;
  47 +
  48 +typedef struct ihs_osd {
  49 + u16 version;
  50 + u16 features;
  51 + u16 control;
  52 + u16 xy_size;
  53 +} ihs_osd_t;
  54 +
  55 +#ifdef CONFIG_IO
  56 +typedef struct ihs_fpga {
  57 + u16 reflection_low; /* 0x0000 */
  58 + u16 versions; /* 0x0002 */
  59 + u16 fpga_features; /* 0x0004 */
  60 + u16 fpga_version; /* 0x0006 */
  61 + u16 reserved_0[5]; /* 0x0008 */
  62 + u16 quad_serdes_reset; /* 0x0012 */
  63 + u16 reserved_1[8181]; /* 0x0014 */
  64 + u16 reflection_high; /* 0x3ffe */
  65 +} ihs_fpga_t;
  66 +#endif
  67 +
  68 +#ifdef CONFIG_IOCON
  69 +typedef struct ihs_fpga {
  70 + u16 reflection_low; /* 0x0000 */
  71 + u16 versions; /* 0x0002 */
  72 + u16 fpga_version; /* 0x0004 */
  73 + u16 fpga_features; /* 0x0006 */
  74 + u16 reserved_0[6]; /* 0x0008 */
  75 + ihs_gpio_t gpio; /* 0x0014 */
  76 + u16 mpc3w_control; /* 0x001a */
  77 + u16 reserved_1[19]; /* 0x001c */
  78 + u16 videocontrol; /* 0x0042 */
  79 + u16 reserved_2[93]; /* 0x0044 */
  80 + u16 reflection_high; /* 0x00fe */
  81 + ihs_osd_t osd; /* 0x0100 */
  82 + u16 reserved_3[892]; /* 0x0108 */
  83 + u16 videomem; /* 0x0800 */
  84 +} ihs_fpga_t;
  85 +#endif
  86 +
  87 +#ifdef CONFIG_DLVISION_10G
  88 +typedef struct ihs_fpga {
  89 + u16 reflection_low; /* 0x0000 */
  90 + u16 versions; /* 0x0002 */
  91 + u16 fpga_version; /* 0x0004 */
  92 + u16 fpga_features; /* 0x0006 */
  93 + u16 reserved_0[10]; /* 0x0008 */
  94 + u16 extended_interrupt; /* 0x001c */
  95 + u16 reserved_1[9]; /* 0x001e */
  96 + ihs_i2c_t i2c; /* 0x0030 */
  97 + u16 reserved_2[35]; /* 0x0038 */
  98 + u16 reflection_high; /* 0x007e */
  99 + u16 reserved_3[15]; /* 0x0080 */
  100 + u16 videocontrol; /* 0x009e */
  101 + u16 reserved_4[176]; /* 0x00a0 */
  102 + ihs_osd_t osd; /* 0x0200 */
  103 + u16 reserved_5[764]; /* 0x0208 */
  104 + u16 videomem; /* 0x0800 */
  105 +} ihs_fpga_t;
  106 +#endif
  107 +
  108 +#endif