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Commit 2da8137b450304070364ec7bb3cf93034f0230c1

Authored by Masahiro Yamada
Committed by Tom Rini
1 parent f8296d6975
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

powerpc: ppc4xx: remove JSE board support 

This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Stephen Williams <steve@icarus.com>

Showing 14 changed files with 1 additions and 1329 deletions Side-by-side Diff

arch/powerpc/cpu/ppc4xx/Kconfig
Diff comments   View file @ 2da8137
... ... @@ -13,9 +13,6 @@
13 13 config TARGET_CSB472
14 14 bool "Support csb472"
15 15  
16   -config TARGET_JSE
17   - bool "Support JSE"
18   -
19 16 config TARGET_KORAT
20 17 bool "Support korat"
21 18  
... ... @@ -204,7 +201,6 @@
204 201 source "board/gdsys/dlvision/Kconfig"
205 202 source "board/gdsys/gdppc440etx/Kconfig"
206 203 source "board/gdsys/intip/Kconfig"
207   -source "board/jse/Kconfig"
208 204 source "board/korat/Kconfig"
209 205 source "board/lwmon5/Kconfig"
210 206 source "board/mosaixtech/icon/Kconfig"
board/jse/Kconfig
View file @ 2da8137
1   -if TARGET_JSE
2   -
3   -config SYS_BOARD
4   - default "jse"
5   -
6   -config SYS_CONFIG_NAME
7   - default "JSE"
8   -
9   -endif
board/jse/MAINTAINERS
View file @ 2da8137
1   -JSE BOARD
2   -M: Stephen Williams <steve@icarus.com>
3   -S: Maintained
4   -F: board/jse/
5   -F: include/configs/JSE.h
6   -F: configs/JSE_defconfig
board/jse/Makefile
View file @ 2da8137
1   -#
2   -# (C) Copyright 2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# Copyright 2004 Picture Elements, Inc.
6   -# Stephen Williams <steve@icarus.com>
7   -#
8   -# SPDX-License-Identifier: GPL-2.0+
9   -#
10   -
11   -obj-y = jse.o sdram.o flash.o host_bridge.o
12   -obj-y += init.o
board/jse/README.txt
View file @ 2da8137
1   -JSE Configuration Details
2   -
3   -Memory Bank 0 -- Flash chip
4   ----------------------------
5   -
6   -0xfff00000 - 0xffffffff
7   -
8   -The flash chip is really only 512Kbytes, but the high address bit of
9   -the 1Meg region is ignored, so the flash is replicated through the
10   -region. Thus, this is consistent with a flash base address 0xfff80000.
11   -
12   -The placement at the end is to be consistent with reset behavior,
13   -where the processor itself initially uses this bus to load the branch
14   -vector and start running.
15   -
16   -On-Chip Memory
17   ---------------
18   -
19   -0xf4000000 - 0xf4000fff
20   -
21   -The 405GPr includes a 4K on-chip memory that can be placed however
22   -software chooses. I choose to place the memory at this address, to
23   -keep it out of the cachable areas.
24   -
25   -
26   -Memory Bank 1 -- SystemACE Controller
27   --------------------------------------
28   -
29   -0xf0000000 - 0xf00fffff
30   -
31   -The SystemACE chip is along on peripheral bank CS#1. We don't need
32   -much space, but 1Meg is the smallest we can configure the chip to
33   -allocate. We need it far away from the flash region, because this
34   -region is set to be non-cached.
35   -
36   -
37   -Internal Peripherals
38   ---------------------
39   -
40   -0xef600300 - 0xef6008ff
41   -
42   -These are scattered various peripherals internal to the PPC405GPr
43   -chip.
44   -
45   -SDRAM
46   ------
47   -
48   -0x00000000 - 0x07ffffff (128 MBytes)
board/jse/flash.c
View file @ 2da8137
1   -/*
2   - * (C) Copyright 2000-2004
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -/*
9   - * Modified 4/5/2001
10   - * Wait for completion of each sector erase command issued
11   - * 4/5/2001
12   - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
13   - */
14   -
15   -#include <common.h>
16   -#include <asm/ppc4xx.h>
17   -#include <asm/processor.h>
18   -
19   -#if CONFIG_SYS_MAX_FLASH_BANKS != 1
20   -#error "CONFIG_SYS_MAX_FLASH_BANKS must be 1"
21   -#endif
22   -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
23   -
24   -/*-----------------------------------------------------------------------
25   - * Functions
26   - */
27   -static ulong flash_get_size (vu_long * addr, flash_info_t * info);
28   -static int write_word (flash_info_t * info, ulong dest, ulong data);
29   -static void flash_get_offsets (ulong base, flash_info_t * info);
30   -
31   -#define ADDR0 0x5555
32   -#define ADDR1 0x2aaa
33   -#define FLASH_WORD_SIZE unsigned char
34   -
35   -/*-----------------------------------------------------------------------
36   - */
37   -
38   -unsigned long flash_init (void)
39   -{
40   - unsigned long size_b0;
41   -
42   - /* Init: no FLASHes known */
43   - flash_info[0].flash_id = FLASH_UNKNOWN;
44   -
45   - /* Static FLASH Bank configuration here - FIXME XXX */
46   -
47   - size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
48   -
49   - if (flash_info[0].flash_id == FLASH_UNKNOWN) {
50   - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
51   - size_b0, size_b0 << 20);
52   - }
53   -
54   - /* Only one bank */
55   - /* Setup offsets */
56   - flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
57   -
58   - /* Monitor protection ON by default */
59   - (void) flash_protect (FLAG_PROTECT_SET,
60   - FLASH_BASE0_PRELIM,
61   - FLASH_BASE0_PRELIM + monitor_flash_len - 1,
62   - &flash_info[0]);
63   - flash_info[0].size = size_b0;
64   -
65   - return size_b0;
66   -}
67   -
68   -
69   -/*-----------------------------------------------------------------------
70   - */
71   -/*
72   - * This implementation assumes that the flash chips are uniform sector
73   - * devices. This is true for all likely JSE devices.
74   - */
75   -static void flash_get_offsets (ulong base, flash_info_t * info)
76   -{
77   - unsigned idx;
78   - unsigned long sector_size = info->size / info->sector_count;
79   -
80   - for (idx = 0; idx < info->sector_count; idx += 1) {
81   - info->start[idx] = base + (idx * sector_size);
82   - }
83   -}
84   -
85   -/*-----------------------------------------------------------------------
86   - */
87   -void flash_print_info (flash_info_t * info)
88   -{
89   - int i;
90   - int k;
91   - int size;
92   - int erased;
93   - volatile unsigned long *flash;
94   -
95   - if (info->flash_id == FLASH_UNKNOWN) {
96   - printf ("missing or unknown FLASH type\n");
97   - return;
98   - }
99   -
100   - switch (info->flash_id & FLASH_VENDMASK) {
101   - case FLASH_MAN_AMD:
102   - printf ("AMD ");
103   - break;
104   - case FLASH_MAN_FUJ:
105   - printf ("FUJITSU ");
106   - break;
107   - case FLASH_MAN_SST:
108   - printf ("SST ");
109   - break;
110   - case FLASH_MAN_STM:
111   - printf ("ST Micro ");
112   - break;
113   - default:
114   - printf ("Unknown Vendor ");
115   - break;
116   - }
117   -
118   - /* (Reduced table of only parts expected in JSE boards.) */
119   - switch (info->flash_id) {
120   - case FLASH_MAN_AMD | FLASH_AM040:
121   - printf ("AM29F040 (512 Kbit, uniform sector size)\n");
122   - break;
123   - case FLASH_MAN_STM | FLASH_AM040:
124   - printf ("MM29W040W (512 Kbit, uniform sector size)\n");
125   - break;
126   - default:
127   - printf ("Unknown Chip Type\n");
128   - break;
129   - }
130   -
131   - printf (" Size: %ld KB in %d Sectors\n",
132   - info->size >> 10, info->sector_count);
133   -
134   - printf (" Sector Start Addresses:");
135   - for (i = 0; i < info->sector_count; ++i) {
136   - /*
137   - * Check if whole sector is erased
138   - */
139   - if (i != (info->sector_count - 1))
140   - size = info->start[i + 1] - info->start[i];
141   - else
142   - size = info->start[0] + info->size - info->start[i];
143   - erased = 1;
144   - flash = (volatile unsigned long *) info->start[i];
145   - size = size >> 2; /* divide by 4 for longword access */
146   - for (k = 0; k < size; k++) {
147   - if (*flash++ != 0xffffffff) {
148   - erased = 0;
149   - break;
150   - }
151   - }
152   -
153   - if ((i % 5) == 0)
154   - printf ("\n ");
155   - printf (" %08lX%s%s",
156   - info->start[i],
157   - erased ? " E" : " ", info->protect[i] ? "RO " : " "
158   - );
159   - }
160   - printf ("\n");
161   - return;
162   -}
163   -
164   -/*-----------------------------------------------------------------------
165   - */
166   -
167   -
168   -/*-----------------------------------------------------------------------
169   - */
170   -
171   -/*
172   - * The following code cannot be run from FLASH!
173   - */
174   -static ulong flash_get_size (vu_long * addr, flash_info_t * info)
175   -{
176   - short i;
177   - FLASH_WORD_SIZE value;
178   - ulong base = (ulong) addr;
179   - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
180   -
181   - /* Write auto select command: read Manufacturer ID */
182   - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
183   - addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
184   - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090;
185   -
186   - value = addr2[0];
187   -
188   - switch (value) {
189   - case (FLASH_WORD_SIZE) AMD_MANUFACT:
190   - info->flash_id = FLASH_MAN_AMD;
191   - break;
192   - case (FLASH_WORD_SIZE) FUJ_MANUFACT:
193   - info->flash_id = FLASH_MAN_FUJ;
194   - break;
195   - case (FLASH_WORD_SIZE) SST_MANUFACT:
196   - info->flash_id = FLASH_MAN_SST;
197   - break;
198   - case (FLASH_WORD_SIZE)STM_MANUFACT:
199   - info->flash_id = FLASH_MAN_STM;
200   - break;
201   - default:
202   - info->flash_id = FLASH_UNKNOWN;
203   - info->sector_count = 0;
204   - info->size = 0;
205   - printf("Unknown flash manufacturer code: 0x%x\n", value);
206   - return (0); /* no or unknown flash */
207   - }
208   -
209   - value = addr2[1]; /* device ID */
210   -
211   - switch (value) {
212   - case (FLASH_WORD_SIZE) AMD_ID_F040B:
213   - info->flash_id += FLASH_AM040;
214   - info->sector_count = 8;
215   - info->size = 0x0080000; /* => 512 ko */
216   - break;
217   - case (FLASH_WORD_SIZE) AMD_ID_LV040B:
218   - info->flash_id += FLASH_AM040;
219   - info->sector_count = 8;
220   - info->size = 0x0080000; /* => 512 ko */
221   - break;
222   - case (FLASH_WORD_SIZE)STM_ID_M29W040B: /* most likele JSE chip */
223   - info->flash_id += FLASH_AM040;
224   - info->sector_count = 8;
225   - info->size = 0x0080000; /* => 512 ko */
226   - break;
227   - default:
228   - info->flash_id = FLASH_UNKNOWN;
229   - return (0); /* => no or unknown flash */
230   -
231   - }
232   -
233   - /* Calculate the sector offsets (Use JSE Optimized code). */
234   - flash_get_offsets(base, info);
235   -
236   - /* check for protected sectors */
237   - for (i = 0; i < info->sector_count; i++) {
238   - /* read sector protection at sector address, (A7 .. A0) = 0x02 */
239   - /* D0 = 1 if protected */
240   - addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
241   - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
242   - info->protect[i] = 0;
243   - else
244   - info->protect[i] = addr2[2] & 1;
245   - }
246   -
247   - /*
248   - * Prevent writes to uninitialized FLASH.
249   - */
250   - if (info->flash_id != FLASH_UNKNOWN) {
251   - addr2 = (FLASH_WORD_SIZE *) info->start[0];
252   - *addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
253   - }
254   -
255   - return (info->size);
256   -}
257   -
258   -int wait_for_DQ7 (flash_info_t * info, int sect)
259   -{
260   - ulong start, now, last;
261   - volatile FLASH_WORD_SIZE *addr =
262   - (FLASH_WORD_SIZE *) (info->start[sect]);
263   -
264   - start = get_timer (0);
265   - last = start;
266   - while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
267   - (FLASH_WORD_SIZE) 0x00800080) {
268   - if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
269   - printf ("Timeout\n");
270   - return -1;
271   - }
272   - /* show that we're waiting */
273   - if ((now - last) > 1000) { /* every second */
274   - putc ('.');
275   - last = now;
276   - }
277   - }
278   - return 0;
279   -}
280   -
281   -/*-----------------------------------------------------------------------
282   - */
283   -
284   -int flash_erase (flash_info_t * info, int s_first, int s_last)
285   -{
286   - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
287   - volatile FLASH_WORD_SIZE *addr2;
288   - int flag, prot, sect;
289   - int i;
290   -
291   - if ((s_first < 0) || (s_first > s_last)) {
292   - if (info->flash_id == FLASH_UNKNOWN) {
293   - printf ("- missing\n");
294   - } else {
295   - printf ("- no sectors to erase\n");
296   - }
297   - return 1;
298   - }
299   -
300   - if (info->flash_id == FLASH_UNKNOWN) {
301   - printf ("Can't erase unknown flash type - aborted\n");
302   - return 1;
303   - }
304   -
305   - prot = 0;
306   - for (sect = s_first; sect <= s_last; ++sect) {
307   - if (info->protect[sect]) {
308   - prot++;
309   - }
310   - }
311   -
312   - if (prot) {
313   - printf ("- Warning: %d protected sectors will not be erased!\n", prot);
314   - } else {
315   - printf ("\n");
316   - }
317   -
318   - /* Disable interrupts which might cause a timeout here */
319   - flag = disable_interrupts ();
320   -
321   - /* Start erase on unprotected sectors */
322   - for (sect = s_first; sect <= s_last; sect++) {
323   - if (info->protect[sect] == 0) { /* not protected */
324   - addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
325   - printf ("Erasing sector %p\n", addr2); /* CLH */
326   -
327   - if ((info->flash_id & FLASH_VENDMASK) ==
328   - FLASH_MAN_SST) {
329   - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
330   - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
331   - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
332   - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
333   - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
334   - addr2[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */
335   - for (i = 0; i < 50; i++)
336   - udelay (1000); /* wait 1 ms */
337   - } else {
338   - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
339   - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
340   - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
341   - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
342   - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
343   - addr2[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */
344   - }
345   - /*
346   - * Wait for each sector to complete, it's more
347   - * reliable. According to AMD Spec, you must
348   - * issue all erase commands within a specified
349   - * timeout. This has been seen to fail, especially
350   - * if printf()s are included (for debug)!!
351   - */
352   - wait_for_DQ7 (info, sect);
353   - }
354   - }
355   -
356   - /* re-enable interrupts if necessary */
357   - if (flag)
358   - enable_interrupts ();
359   -
360   - /* wait at least 80us - let's wait 1 ms */
361   - udelay (1000);
362   -
363   - /* reset to read mode */
364   - addr = (FLASH_WORD_SIZE *) info->start[0];
365   - addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
366   -
367   - printf (" done\n");
368   - return 0;
369   -}
370   -
371   -/*-----------------------------------------------------------------------
372   - * Copy memory to flash, returns:
373   - * 0 - OK
374   - * 1 - write timeout
375   - * 2 - Flash not erased
376   - */
377   -
378   -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
379   -{
380   - ulong cp, wp, data;
381   - int i, l, rc;
382   -
383   - wp = (addr & ~3); /* get lower word aligned address */
384   -
385   - /*
386   - * handle unaligned start bytes
387   - */
388   - if ((l = addr - wp) != 0) {
389   - data = 0;
390   - for (i = 0, cp = wp; i < l; ++i, ++cp) {
391   - data = (data << 8) | (*(uchar *) cp);
392   - }
393   - for (; i < 4 && cnt > 0; ++i) {
394   - data = (data << 8) | *src++;
395   - --cnt;
396   - ++cp;
397   - }
398   - for (; cnt == 0 && i < 4; ++i, ++cp) {
399   - data = (data << 8) | (*(uchar *) cp);
400   - }
401   -
402   - if ((rc = write_word (info, wp, data)) != 0) {
403   - return (rc);
404   - }
405   - wp += 4;
406   - }
407   -
408   - /*
409   - * handle word aligned part
410   - */
411   - while (cnt >= 4) {
412   - data = 0;
413   - for (i = 0; i < 4; ++i) {
414   - data = (data << 8) | *src++;
415   - }
416   - if ((rc = write_word (info, wp, data)) != 0) {
417   - return (rc);
418   - }
419   - wp += 4;
420   - cnt -= 4;
421   - }
422   -
423   - if (cnt == 0) {
424   - return (0);
425   - }
426   -
427   - /*
428   - * handle unaligned tail bytes
429   - */
430   - data = 0;
431   - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
432   - data = (data << 8) | *src++;
433   - --cnt;
434   - }
435   - for (; i < 4; ++i, ++cp) {
436   - data = (data << 8) | (*(uchar *) cp);
437   - }
438   -
439   - return (write_word (info, wp, data));
440   -}
441   -
442   -/*-----------------------------------------------------------------------
443   - * Write a word to Flash, returns:
444   - * 0 - OK
445   - * 1 - write timeout
446   - * 2 - Flash not erased
447   - */
448   -static int write_word (flash_info_t * info, ulong dest, ulong data)
449   -{
450   - volatile FLASH_WORD_SIZE *addr2 =
451   - (FLASH_WORD_SIZE *) (info->start[0]);
452   - volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
453   - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
454   - ulong start;
455   - int i;
456   -
457   - /* Check if Flash is (sufficiently) erased */
458   - if ((*((volatile FLASH_WORD_SIZE *) dest) &
459   - (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
460   - return (2);
461   - }
462   -
463   - for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
464   - int flag;
465   -
466   - /* Disable interrupts which might cause a timeout here */
467   - flag = disable_interrupts ();
468   -
469   - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
470   - addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
471   - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
472   -
473   - dest2[i] = data2[i];
474   -
475   - /* re-enable interrupts if necessary */
476   - if (flag)
477   - enable_interrupts ();
478   -
479   - /* data polling for D7 */
480   - start = get_timer (0);
481   - while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
482   - (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
483   -
484   - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
485   - return (1);
486   - }
487   - }
488   - }
489   -
490   - return (0);
491   -}
board/jse/host_bridge.c
View file @ 2da8137
1   -/*
2   - * Copyright (c) 2004 Picture Elements, Inc.
3   - * Stephen Williams (steve@icarus.com)
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -#ident "$Id:$"
8   -
9   -# include <common.h>
10   -# include <pci.h>
11   -# include "jse_priv.h"
12   -
13   -/*
14   - * The JSE board has an Intel 21555 non-transparent bridge for
15   - * communication with the host. We need to render it harmless on the
16   - * JSE side, but leave it alone on the host (primary) side. Normally,
17   - * this will all be done before the host BIOS can gain access to the
18   - * board, due to the Primary Access Lockout bit.
19   - *
20   - * The host_bridge_init function is called as a late initialization
21   - * function, after most of the board is set up, including a PCI scan.
22   - */
23   -
24   -void host_bridge_init (void)
25   -{
26   - /* The bridge chip is at a fixed location. */
27   - pci_dev_t dev = PCI_BDF (0, 10, 0);
28   -
29   - /* Set PCI Class code --
30   - The primary side sees this class code at 0x08 in the
31   - primary config space. This must be something other then a
32   - bridge, or MS Windows starts doing weird stuff to me. */
33   - pci_write_config_dword (dev, 0x48, 0x04800000);
34   -
35   - /* Set subsystem ID --
36   - The primary side sees this value at 0x2c. We set it here so
37   - that the host can tell what sort of device this is:
38   - We are a Picture Elements [0x12c5] JSE [0x008a]. */
39   - pci_write_config_dword (dev, 0x6c, 0x008a12c5);
40   -
41   - /* Downstream (Primary-to-Secondary) BARs are set up mostly
42   - off. We need only the Memory-0 Bar so that the host can get
43   - at the CSR region to set up tables and the lot. */
44   -
45   - /* Downstream Memory 0 setup (4K for CSR) */
46   - pci_write_config_dword (dev, 0xac, 0xfffff000);
47   - /* Downstream Memory 1 setup (off) */
48   - pci_write_config_dword (dev, 0xb0, 0x00000000);
49   - /* Downstream Memory 2 setup (off) */
50   - pci_write_config_dword (dev, 0xb4, 0x00000000);
51   - /* Downstream Memory 3 setup (off) */
52   - pci_write_config_dword (dev, 0xb8, 0x00000000);
53   -
54   - /* Upstream (Secondary-to-Primary) BARs are used to get at
55   - host memory from the JSE card. Create two regions: a small
56   - one to manage individual word reads/writes, and a larger
57   - one for doing bulk frame moves. */
58   -
59   - /* Upstream Memory 0 Setup -- (BAR2) 4K non-prefetchable */
60   - pci_write_config_dword (dev, 0xc4, 0xfffff000);
61   - /* Upstream Memory 1 setup -- (BAR3) 4K non-prefetchable */
62   - pci_write_config_dword (dev, 0xc8, 0xfffff000);
63   -
64   - /* Upstream Memory 2 (BAR4) uses page translation, and is set
65   - up in CCR1. Configure for 4K pages. */
66   -
67   - /* Set CCR1,0 reigsters. This clears the Primary PCI Lockout
68   - bit as well, so we are done configuring after this
69   - point. Therefore, this must be the last step.
70   -
71   - CC1[15:12]= 0 (disable I2O message unit)
72   - CC1[11:8] = 0x5 (4K page size)
73   - CC0[11] = 1 (Secondary Clock Disable: disable clock)
74   - CC0[10] = 0 (Primary Access Lockout: allow primary access)
75   - */
76   - pci_write_config_dword (dev, 0xcc, 0x05000800);
77   -}
board/jse/init.S
View file @ 2da8137
1   -/*
2   - * SPDX-License-Identifier: GPL-2.0 IBM-pibs
3   - */
4   -/*------------------------------------------------------------------------- */
5   -/* Function: ext_bus_cntlr_init */
6   -/* Description: Initializes the External Bus Controller for the external */
7   -/* peripherals. IMPORTANT: For pass1 this code must run from */
8   -/* cache since you can not reliably change a peripheral banks */
9   -/* timing register (pbxap) while running code from that bank. */
10   -/* For ex., since we are running from ROM on bank 0, we can NOT */
11   -/* execute the code that modifies bank 0 timings from ROM, so */
12   -/* we run it from cache. */
13   -/* */
14   -/* */
15   -/* The layout for the PEI JSE board: */
16   -/* Bank 0 - Flash and SRAM */
17   -/* Bank 1 - SystemACE */
18   -/* Bank 2 - not used */
19   -/* Bank 3 - not used */
20   -/* Bank 4 - not used */
21   -/* Bank 5 - not used */
22   -/* Bank 6 - not used */
23   -/* Bank 7 - not used */
24   -/*------------------------------------------------------------------------- */
25   -#include <asm/ppc4xx.h>
26   -
27   -#include <ppc_asm.tmpl>
28   -#include <ppc_defs.h>
29   -
30   -#include <asm/cache.h>
31   -#include <asm/mmu.h>
32   -
33   - .globl ext_bus_cntlr_init
34   -ext_bus_cntlr_init:
35   - mflr r4 /* save link register */
36   - bl ..getAddr
37   -..getAddr:
38   - mflr r3 /* get address of ..getAddr */
39   - mtlr r4 /* restore link register */
40   - addi r4,0,14 /* set ctr to 10; used to prefetch */
41   - mtctr r4 /* 10 cache lines to fit this function */
42   - /* in cache (gives us 8x10=80 instrctns) */
43   -..ebcloop:
44   - icbt r0,r3 /* prefetch cache line for addr in r3 */
45   - addi r3,r3,32 /* move to next cache line */
46   - bdnz ..ebcloop /* continue for 10 cache lines */
47   -
48   - /*----------------------------------------------------------------- */
49   - /* Delay to ensure all accesses to ROM are complete before changing */
50   - /* bank 0 timings. 200usec should be enough. */
51   - /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
52   - /*----------------------------------------------------------------- */
53   - addis r3,0,0x0
54   - ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
55   - mtctr r3
56   -..spinlp:
57   - bdnz ..spinlp /* spin loop */
58   -
59   - /*----------------------------------------------------------------- */
60   - /* Memory Bank 0 (Flash) initialization */
61   - /*----------------------------------------------------------------- */
62   -
63   - addi r4,0,PB1AP
64   - mtdcr EBC0_CFGADDR,r4
65   - addis r4,0,0x9B01
66   - ori r4,r4,0x5480
67   - mtdcr EBC0_CFGDATA,r4
68   -
69   - addi r4,0,PB0CR
70   - mtdcr EBC0_CFGADDR,r4
71   - addis r4,0,0xFFF1 /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */
72   - ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
73   - mtdcr EBC0_CFGDATA,r4
74   -
75   - blr
board/jse/jse.c
View file @ 2da8137
1   -/*
2   - * Copyright (c) 2004 Picture Elements, Inc.
3   - * Stephen Williams (steve@icarus.com)
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -# include <common.h>
9   -# include <asm/ppc4xx.h>
10   -# include <asm/processor.h>
11   -# include <asm/io.h>
12   -# include "jse_priv.h"
13   -
14   -/*
15   - * This function is run very early, out of flash, and before devices are
16   - * initialized. It is called by arch/powerpc/lib/board.c:board_init_f by virtue
17   - * of being in the init_sequence array.
18   - *
19   - * The SDRAM has been initialized already -- start.S:start called
20   - * init.S:init_sdram early on -- but it is not yet being used for
21   - * anything, not even stack. So be careful.
22   - */
23   -int board_early_init_f (void)
24   -{
25   - /*-------------------------------------------------------------------------+
26   - | Interrupt controller setup for the JSE board.
27   - | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
28   - | IRQ 16 405GP internally generated; active low; level sensitive
29   - | IRQ 17-24 RESERVED/UNUSED
30   - | IRQ 25 (EXT IRQ 0) PCI SLOT 0; active low; level sensitive
31   - | IRQ 26 (EXT IRQ 1) PCI SLOT 1; active low; level sensitive
32   - | IRQ 27 (EXT IRQ 2) JP2C CHIP ; active low; level sensitive
33   - | IRQ 28 (EXT IRQ 3) PCI bridge; active low; level sensitive
34   - | IRQ 29 (EXT IRQ 4) SystemACE IRQ; active high
35   - | IRQ 30 (EXT IRQ 5) SystemACE BRdy (unused)
36   - | IRQ 31 (EXT IRQ 6) (unused)
37   - +-------------------------------------------------------------------------*/
38   - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
39   - mtdcr (UIC0ER, 0x00000000); /* disable all ints */
40   - mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
41   - mtdcr (UIC0PR, 0xFFFFFF87); /* set int polarities */
42   - mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
43   - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
44   -
45   - /* Configure the interface to the SystemACE MCU port.
46   - The SystemACE is fast, but there is no reason to have
47   - excessivly tight timings. So the settings are slightly
48   - generous. */
49   -
50   - /* EBC0_B1AP: BME=1, TWT=2, CSN=0, OEN=1,
51   - WBN=0, WBF=1, TH=0, RE=0, SOR=0, BEM=0, PEN=0 */
52   - mtdcr (EBC0_CFGADDR, PB1AP);
53   - mtdcr (EBC0_CFGDATA, 0x01011000);
54   -
55   - /* EBC0_B1CR: BAS=x, BS=0(1MB), BU=3(R/W), BW=0(8bits) */
56   - mtdcr (EBC0_CFGADDR, PB1CR);
57   - mtdcr (EBC0_CFGDATA, CONFIG_SYS_SYSTEMACE_BASE | 0x00018000);
58   -
59   - /* Enable the /PerWE output as /PerWE, instead of /PCIINT. */
60   - /* CPC0_CR1 |= PCIPW */
61   - mtdcr (0xb2, mfdcr (0xb2) | 0x00004000);
62   -
63   - return 0;
64   -}
65   -
66   -#ifdef CONFIG_BOARD_PRE_INIT
67   -int board_pre_init (void)
68   -{
69   - return board_early_init_f ();
70   -}
71   -
72   -#endif
73   -
74   -/*
75   - * This function is also called by arch/powerpc/lib/board.c:board_init_f (it is
76   - * also in the init_sequence array) but later. Many more things are
77   - * configured, but we are still running from flash.
78   - */
79   -int checkboard (void)
80   -{
81   - unsigned vers, status;
82   -
83   - /* check that the SystemACE chip is alive. */
84   - printf ("ACE: ");
85   - vers = readw (CONFIG_SYS_SYSTEMACE_BASE + 0x16);
86   - printf ("SystemACE %u.%u (build %u)",
87   - (vers >> 12) & 0x0f, (vers >> 8) & 0x0f, vers & 0xff);
88   -
89   - status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04);
90   -#ifdef DEBUG
91   - printf (" STATUS=0x%08x", status);
92   -#endif
93   - /* If the flash card is present and there is an initial error,
94   - then force a restart of the program. */
95   - if (status & 0x00000010) {
96   - printf (" CFDETECT");
97   -
98   - if (status & 0x04) {
99   - /* CONTROLREG = CFGPROG */
100   - writew (0x1000, CONFIG_SYS_SYSTEMACE_BASE + 0x18);
101   - udelay (500);
102   - /* CONTROLREG = CFGRESET */
103   - writew (0x0080, CONFIG_SYS_SYSTEMACE_BASE + 0x18);
104   - udelay (500);
105   - writew (0x0000, CONFIG_SYS_SYSTEMACE_BASE + 0x18);
106   - /* CONTROLREG = CFGSTART */
107   - writew (0x0020, CONFIG_SYS_SYSTEMACE_BASE + 0x18);
108   -
109   - status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04);
110   - }
111   - }
112   -
113   - /* Wait for the SystemACE to program its chain of devices. */
114   - while ((status & 0x84) == 0x00) {
115   - udelay (500);
116   - status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04);
117   - }
118   -
119   - if (status & 0x04)
120   - printf (" CFG-ERROR");
121   - if (status & 0x80)
122   - printf (" CFGDONE");
123   -
124   - printf ("\n");
125   -
126   - /* Force /RTS to active. The board it not wired quite
127   - correctly to use cts/rtc flow control, so just force the
128   - /RST active and forget about it. */
129   - writeb (readb (0xef600404) | 0x03, 0xef600404);
130   -
131   - printf ("JSE: ready\n");
132   -
133   - return 0;
134   -}
135   -
136   -/* **** No more functions called by board_init_f. **** */
137   -
138   -/*
139   - * This function is called by arch/powerpc/lib/board.c:board_init_r. At this
140   - * point, basic setup is done, U-Boot has been moved into SDRAM and
141   - * PCI has been set up. From here we done late setup.
142   - */
143   -int misc_init_r (void)
144   -{
145   - host_bridge_init ();
146   - return 0;
147   -}
board/jse/jse_priv.h
View file @ 2da8137
1   -#ifndef __jse_priv_H
2   -#define __jse_prov_H
3   -/*
4   - * Copyright (c) 2004 Picture Elements, Inc.
5   - * Stephen Williams (steve@icarus.com)
6   - *
7   - * SPDX-License-Identifier: GPL-2.0+
8   - */
9   -
10   -extern void host_bridge_init(void);
11   -
12   -#endif
board/jse/sdram.c
View file @ 2da8137
1   -/*
2   - * Copyright (c) 2004 Picture Elements, Inc.
3   - * Stephen Williams (steve@icarus.com)
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -#include <asm/ppc4xx.h>
10   -#include <asm/processor.h>
11   -
12   -# define SDRAM_LEN 0x08000000
13   -
14   -/*
15   - * this is even after checkboard. It returns the size of the SDRAM
16   - * that we have installed. This function is called by board_init_f
17   - * in arch/powerpc/lib/board.c to initialize the memory and return what I
18   - * found.
19   - */
20   -phys_size_t initdram (int board_type)
21   -{
22   - /* Configure the SDRAMS */
23   -
24   - /* disable memory controller */
25   - mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
26   - mtdcr (SDRAM0_CFGDATA, 0x00000000);
27   -
28   - udelay (500);
29   -
30   - /* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
31   - mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR0);
32   - mtdcr (SDRAM0_CFGDATA, 0xffffffff);
33   -
34   - /* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
35   - mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR1);
36   - mtdcr (SDRAM0_CFGDATA, 0xffffffff);
37   -
38   - /* Clear SDRAM0_ECCCFG (disable ECC) */
39   - mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
40   - mtdcr (SDRAM0_CFGDATA, 0x00000000);
41   -
42   - /* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
43   - mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCESR);
44   - mtdcr (SDRAM0_CFGDATA, 0xffffffff);
45   -
46   - /* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 */
47   - mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
48   - mtdcr (SDRAM0_CFGDATA, 0x010a4016);
49   -
50   - /* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 */
51   - mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
52   - mtdcr (SDRAM0_CFGDATA, 0x00084001);
53   -
54   - /* Memory Bank 1 Config == BA=0x04000000, SZ=64M, AM=3, BE=1 */
55   - mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
56   - mtdcr (SDRAM0_CFGDATA, 0x04084001);
57   -
58   - /* Memory Bank 2 Config == BE=0 */
59   - mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
60   - mtdcr (SDRAM0_CFGDATA, 0x00000000);
61   -
62   - /* Memory Bank 3 Config == BE=0 */
63   - mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
64   - mtdcr (SDRAM0_CFGDATA, 0x00000000);
65   -
66   - /* refresh timer = 0x400 */
67   - mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
68   - mtdcr (SDRAM0_CFGDATA, 0x04000000);
69   -
70   - /* Power management idle timer set to the default. */
71   - mtdcr (SDRAM0_CFGADDR, SDRAM0_PMIT);
72   - mtdcr (SDRAM0_CFGDATA, 0x07c00000);
73   -
74   - udelay (500);
75   -
76   - /* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) */
77   - mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
78   - mtdcr (SDRAM0_CFGDATA, 0x80e00000);
79   -
80   - return SDRAM_LEN;
81   -}
82   -
83   -/*
84   - * The U-Boot core, as part of the initialization to prepare for
85   - * loading the monitor into SDRAM, requests of this function that the
86   - * memory be tested. Return 0 if the memory tests OK.
87   - */
88   -int testdram (void)
89   -{
90   - unsigned long idx;
91   - unsigned val;
92   - unsigned errors;
93   - volatile unsigned long *sdram;
94   -
95   -#ifdef DEBUG
96   - printf ("SDRAM Controller Registers --\n");
97   -
98   - mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
99   - val = mfdcr (SDRAM0_CFGDATA);
100   - printf (" SDRAM0_CFG : 0x%08x\n", val);
101   -
102   - mtdcr (SDRAM0_CFGADDR, 0x24);
103   - val = mfdcr (SDRAM0_CFGDATA);
104   - printf (" SDRAM0_STATUS: 0x%08x\n", val);
105   -
106   - mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
107   - val = mfdcr (SDRAM0_CFGDATA);
108   - printf (" SDRAM0_B0CR : 0x%08x\n", val);
109   -
110   - mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
111   - val = mfdcr (SDRAM0_CFGDATA);
112   - printf (" SDRAM0_B1CR : 0x%08x\n", val);
113   -
114   - mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
115   - val = mfdcr (SDRAM0_CFGDATA);
116   - printf (" SDRAM0_TR : 0x%08x\n", val);
117   -
118   - mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
119   - val = mfdcr (SDRAM0_CFGDATA);
120   - printf (" SDRAM0_RTR : 0x%08x\n", val);
121   -#endif
122   -
123   - /* Wait for memory to be ready by testing MRSCMPbit
124   - bit. Really, there should already have been plenty of time,
125   - given it was started long ago. But, best to check. */
126   - for (idx = 0; idx < 1000000; idx += 1) {
127   - mtdcr (SDRAM0_CFGADDR, 0x24);
128   - val = mfdcr (SDRAM0_CFGDATA);
129   - if (val & 0x80000000)
130   - break;
131   - }
132   -
133   - if (!(val & 0x80000000)) {
134   - printf ("SDRAM ERROR: SDRAM0_STATUS never set!\n");
135   - return 1;
136   - }
137   -
138   - /* Start memory test. */
139   - printf ("test: %u MB - ", SDRAM_LEN / 1048576);
140   -
141   - sdram = (unsigned long *) CONFIG_SYS_SDRAM_BASE;
142   -
143   - printf ("write - ");
144   - for (idx = 2; idx < SDRAM_LEN / 4; idx += 2) {
145   - sdram[idx + 0] = idx;
146   - sdram[idx + 1] = ~idx;
147   - }
148   -
149   - printf ("read - ");
150   - errors = 0;
151   - for (idx = 2; idx < SDRAM_LEN / 4; idx += 2) {
152   - if (sdram[idx + 0] != idx)
153   - errors += 1;
154   - if (sdram[idx + 1] != ~idx)
155   - errors += 1;
156   - if (errors > 0)
157   - break;
158   - }
159   -
160   - if (errors > 0) {
161   - printf ("NOT OK\n");
162   - printf ("FIRST ERROR at %p: 0x%08lx:0x%08lx != 0x%08lx:0x%08lx\n",
163   - sdram + idx, sdram[idx + 0], sdram[idx + 1], idx, ~idx);
164   - return 1;
165   - }
166   -
167   - printf ("ok\n");
168   - return 0;
169   -}
configs/JSE_defconfig
View file @ 2da8137
1   -CONFIG_PPC=y
2   -CONFIG_4xx=y
3   -CONFIG_TARGET_JSE=y
doc/README.scrapyard
Diff comments   View file @ 2da8137
... ... @@ -12,6 +12,7 @@
12 12  
13 13 Board Arch CPU Commit Removed Last known maintainer/contact
14 14 =================================================================================================
  15 +JSE powerpc ppc4xx - - Stephen Williams <steve@icarus.com>
15 16 BC3450 powerpc mpc5xxx - -
16 17 hawkboard arm arm926ejs cb957cda 2015-02-24 Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com>
17 18 tnetv107x arm arm1176 50b82c4b 2015-02-24 Chan-Taek Park <c-park@ti.com>
include/configs/JSE.h
View file @ 2da8137
1   -/*
2   - * (C) Copyright 2003 Picture Elements, Inc.
3   - * Stephen Williams <steve@icarus.com>
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -/*
9   - * board/config.h - configuration options, board specific
10   - */
11   -
12   -#ifndef __CONFIG_H
13   -#define __CONFIG_H
14   -
15   -/*
16   - * High Level Configuration Options for the JSE board
17   - * (Theoretically easy to change, but the board is fixed.)
18   - */
19   -
20   -#define CONFIG_JSE 1
21   - /* JSE has a PPC405GPr */
22   -#define CONFIG_405GP 1
23   - /* ... with a 33MHz OSC. connected to the SysCLK input */
24   -#define CONFIG_SYS_CLK_FREQ 33333333
25   - /* ... with on-chip memory here (4KBytes) */
26   -#define CONFIG_SYS_OCM_DATA_ADDR 0xF4000000
27   -#define CONFIG_SYS_OCM_DATA_SIZE 0x00001000
28   - /* Do not set up locked dcache as init ram. */
29   -#undef CONFIG_SYS_INIT_DCACHE_CS
30   -
31   -#define CONFIG_SYS_TEXT_BASE 0xFFF80000
32   -
33   - /* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */
34   -#define CONFIG_SYSTEMACE 1
35   -#define CONFIG_SYS_SYSTEMACE_BASE 0xf0000000
36   -#define CONFIG_SYS_SYSTEMACE_WIDTH 8
37   -#define CONFIG_DOS_PARTITION 1
38   -
39   - /* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
40   -#define CONFIG_SYS_TEMP_STACK_OCM 1
41   - /* ... place INIT RAM in the OCM address */
42   -# define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
43   - /* ... give it the whole init ram */
44   -# define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
45   - /* ... Shave a bit off the end for global data */
46   -# define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
47   - /* ... and place the stack pointer at the top of what's left. */
48   -# define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
49   -
50   - /* Enable board_pre_init function */
51   -#define CONFIG_BOARD_PRE_INIT 1
52   -#define CONFIG_BOARD_EARLY_INIT_F 1
53   - /* Disable post-clk setup init function */
54   -#undef CONFIG_BOARD_POSTCLK_INIT
55   - /* Disable call to post_init_f: late init function. */
56   -#undef CONFIG_POST
57   - /* Enable DRAM test. */
58   -#define CONFIG_SYS_DRAM_TEST 1
59   - /* Enable misc_init_r function. */
60   -#define CONFIG_MISC_INIT_R 1
61   -
62   - /* JSE has EEPROM chips that are good for environment. */
63   -#undef CONFIG_ENV_IS_IN_NVRAM
64   -#undef CONFIG_ENV_IS_IN_FLASH
65   -#define CONFIG_ENV_IS_IN_EEPROM 1
66   -#undef CONFIG_ENV_IS_NOWHERE
67   -
68   - /* This is the 7bit address of the device, not including P. */
69   -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
70   - /* After the device address, need one more address byte. */
71   -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
72   - /* The EEPROM is 512 bytes. */
73   -#define CONFIG_SYS_EEPROM_SIZE 512
74   - /* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
75   -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
76   -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
77   - /* Put the environment in the second half. */
78   -#define CONFIG_ENV_OFFSET 0x00
79   -#define CONFIG_ENV_SIZE 512
80   -
81   - /* The JSE connects UART1 to the console tap connector. */
82   -#define CONFIG_CONS_INDEX 2
83   -#define CONFIG_SYS_NS16550
84   -#define CONFIG_SYS_NS16550_SERIAL
85   -#define CONFIG_SYS_NS16550_REG_SIZE 1
86   -#define CONFIG_SYS_NS16550_CLK get_serial_clock()
87   -
88   - /* Set console baudrate to 9600 */
89   -#define CONFIG_BAUDRATE 9600
90   -
91   -/*
92   - * Configuration related to auto-boot.
93   - *
94   - * CONFIG_BOOTDELAY sets the delay (in seconds) that U-Boot will wait
95   - * before resorting to autoboot. This value can be overridden by the
96   - * bootdelay environment variable.
97   - *
98   - * CONFIG_AUTOBOOT_PROMPT is the string that U-Boot emits to warn the
99   - * user that an autoboot will happen.
100   - *
101   - * CONFIG_BOOTCOMMAND is the sequence of commands that U-Boot will
102   - * execute to boot the JSE. This loads the uimage and initrd.img files
103   - * from CompactFlash into memory, then boots them from memory.
104   - *
105   - * CONFIG_BOOTARGS is the arguments passed to the Linux kernel to get
106   - * it going on the JSE.
107   - */
108   -#define CONFIG_BOOTDELAY 5
109   -#define CONFIG_BOOTARGS "root=/dev/ram0 init=/linuxrc rw"
110   -#define CONFIG_BOOTCOMMAND "fatload ace 0 2000000 uimage; fatload ace 0 2100000 initrd.img; bootm 2000000 2100000"
111   -
112   -
113   -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
114   -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
115   -
116   -#define CONFIG_PPC4xx_EMAC
117   -#define CONFIG_MII 1 /* MII PHY management */
118   -#define CONFIG_PHY_ADDR 1 /* PHY address */
119   -
120   -
121   -/*
122   - * BOOTP options
123   - */
124   -#define CONFIG_BOOTP_BOOTFILESIZE
125   -#define CONFIG_BOOTP_BOOTPATH
126   -#define CONFIG_BOOTP_GATEWAY
127   -#define CONFIG_BOOTP_HOSTNAME
128   -
129   -
130   -/*
131   - * Command line configuration.
132   - */
133   -#include <config_cmd_default.h>
134   -
135   -#define CONFIG_CMD_DHCP
136   -#define CONFIG_CMD_EEPROM
137   -#define CONFIG_CMD_ELF
138   -#define CONFIG_CMD_FAT
139   -#define CONFIG_CMD_FLASH
140   -#define CONFIG_CMD_IRQ
141   -#define CONFIG_CMD_MII
142   -#define CONFIG_CMD_NET
143   -#define CONFIG_CMD_PCI
144   -#define CONFIG_CMD_PING
145   -
146   -
147   - /* watchdog disabled */
148   -#undef CONFIG_WATCHDOG
149   - /* SPD EEPROM (sdram speed config) disabled */
150   -#undef CONFIG_SPD_EEPROM
151   -#undef SPD_EEPROM_ADDRESS
152   -
153   -/*
154   - * Miscellaneous configurable options
155   - */
156   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
157   -
158   -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
159   -
160   -#if defined(CONFIG_CMD_KGDB)
161   -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
162   -#else
163   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
164   -#endif
165   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
166   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
167   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
168   -
169   -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
170   -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
171   -
172   -/*
173   - * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
174   - * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
175   - * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
176   - * The Linux BASE_BAUD define should match this configuration.
177   - * baseBaud = cpuClock/(uartDivisor*16)
178   - * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
179   - * set Linux BASE_BAUD to 403200.
180   - */
181   -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
182   -#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
183   -#define CONFIG_SYS_BASE_BAUD 691200
184   -
185   -/* The following table includes the supported baudrates */
186   -#define CONFIG_SYS_BAUDRATE_TABLE \
187   - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
188   -
189   -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
190   -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
191   -
192   -#define CONFIG_SYS_I2C
193   -#define CONFIG_SYS_I2C_PPC4XX
194   -#define CONFIG_SYS_I2C_PPC4XX_CH0
195   -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
196   -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
197   -
198   -
199   -/*-----------------------------------------------------------------------
200   - * PCI stuff
201   - *-----------------------------------------------------------------------
202   - */
203   -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
204   -#define PCI_HOST_FORCE 1 /* configure as pci host */
205   -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
206   -
207   -#define CONFIG_PCI /* include pci support */
208   -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
209   -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
210   -#undef CONFIG_PCI_PNP /* do pci plug-and-play */
211   - /* resource configuration */
212   -
213   -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
214   -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
215   -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
216   -#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
217   -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
218   -#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
219   -#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
220   -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
221   -
222   -/*-----------------------------------------------------------------------
223   - * External peripheral base address
224   - *-----------------------------------------------------------------------
225   - */
226   -#undef CONFIG_IDE_LED /* no led for ide supported */
227   -#undef CONFIG_IDE_RESET /* no reset for ide supported */
228   -
229   -#define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000
230   -#define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000
231   -#define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000
232   -
233   -/*-----------------------------------------------------------------------
234   - * Start addresses for the final memory configuration
235   - * (Set up by the startup code)
236   - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
237   - */
238   -#define CONFIG_SYS_SDRAM_BASE 0x00000000
239   -#define CONFIG_SYS_FLASH_BASE 0xFFF80000
240   -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
241   -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
242   -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
243   -
244   -/*
245   - * For booting Linux, the board info and command line data
246   - * have to be in the first 8 MB of memory, since this is
247   - * the maximum mapped by the Linux kernel during initialization.
248   - */
249   -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
250   -
251   -/*-----------------------------------------------------------------------
252   - * FLASH organization
253   - */
254   -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
255   -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
256   -
257   -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
258   -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
259   -
260   -/*
261   - * Init Memory Controller:
262   - *
263   - * BR0/1 and OR0/1 (FLASH)
264   - */
265   -
266   -#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
267   -#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
268   -
269   -
270   -/* Configuration Port location */
271   -#define CONFIG_PORT_ADDR 0xF0000500
272   -
273   -#if defined(CONFIG_CMD_KGDB)
274   -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
275   -#endif
276   -#endif /* __CONFIG_H */