Enabled the Freescale SGMII riser card on 8536DS

Signed-off-by: Jason Jin <Jason.jin@freescale.com>

Enabled the Freescale SGMII riser card on 8536DS
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Jason Jin · Wolfgang Denk
1 parent 7e183cad0c
Showing 2 changed files with 45 additions and 0 deletions Side-by-side Diff
board/freescale/mpc8536ds/mpc8536ds.c
include/configs/MPC8536DS.h
@@ -35,8 +35,11 @@
 #include <libfdt.h>
 #include <spd_sdram.h>
 #include <fdt_support.h>
+#include <tsec.h>
+#include <netdev.h>
  
 #include "../common/pixis.h"
+#include "../common/sgmii_riser.h"
  
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
@@ -616,6 +619,45 @@
 		return 0;
  
 	return 1;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_TSEC_ENET
+	struct tsec_info_struct tsec_info[2];
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	int num = 0;
+	uint sdrs2_io_sel =
+		(gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
+
+#ifdef CONFIG_TSEC1
+	SET_STD_TSEC_INFO(tsec_info[num], 1);
+	if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) {
+		tsec_info[num].phyaddr = 0;
+		tsec_info[num].flags |= TSEC_SGMII;
+	}
+	num++;
+#endif
+#ifdef CONFIG_TSEC3
+	SET_STD_TSEC_INFO(tsec_info[num], 3);
+	if (sdrs2_io_sel == 4) {
+		tsec_info[num].phyaddr = 1;
+		tsec_info[num].flags |= TSEC_SGMII;
+	}
+	num++;
+#endif
+
+	if (!num) {
+		printf("No TSECs initialized\n");
+		return 0;
+	}
+
+	if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6))
+		fsl_sgmii_riser_init(tsec_info, num);
+
+	tsec_eth_init(bis, tsec_info, num);
+#endif
+	return pci_eth_init(bis);
 }
  
 #if defined(CONFIG_OF_BOARD_SETUP)
@@ -427,6 +427,9 @@
 #define CONFIG_TSEC3	1
 #define CONFIG_TSEC3_NAME	"eTSEC3"
  
+#define CONFIG_FSL_SGMII_RISER	1
+#define SGMII_RISER_PHY_OFFSET	0x1c
+
 #define TSEC1_PHY_ADDR		1	/* TSEC1 -> PHY1 */
 #define TSEC3_PHY_ADDR		0	/* TSEC3 -> PHY0 */
...	...	@@ -35,8 +35,11 @@
35	35	#include <libfdt.h>
36	36	#include <spd_sdram.h>
37	37	#include <fdt_support.h>
	38	+#include <tsec.h>
	39	+#include <netdev.h>
38	40
39	41	#include "../common/pixis.h"
	42	+#include "../common/sgmii_riser.h"
40	43
41	44	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
42	45	extern void ddr_enable_ecc(unsigned int dram_size);
...	...	@@ -616,6 +619,45 @@
616	619	return 0;
617	620
618	621	return 1;
	622	+}
	623	+
	624	+int board_eth_init(bd_t *bis)
	625	+{
	626	+#ifdef CONFIG_TSEC_ENET
	627	+ struct tsec_info_struct tsec_info[2];
	628	+ volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	629	+ int num = 0;
	630	+ uint sdrs2_io_sel =
	631	+ (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
	632	+
	633	+#ifdef CONFIG_TSEC1
	634	+ SET_STD_TSEC_INFO(tsec_info[num], 1);
	635	+ if ((sdrs2_io_sel == 4) \|\| (sdrs2_io_sel == 6)) {
	636	+ tsec_info[num].phyaddr = 0;
	637	+ tsec_info[num].flags \|= TSEC_SGMII;
	638	+ }
	639	+ num++;
	640	+#endif
	641	+#ifdef CONFIG_TSEC3
	642	+ SET_STD_TSEC_INFO(tsec_info[num], 3);
	643	+ if (sdrs2_io_sel == 4) {
	644	+ tsec_info[num].phyaddr = 1;
	645	+ tsec_info[num].flags \|= TSEC_SGMII;
	646	+ }
	647	+ num++;
	648	+#endif
	649	+
	650	+ if (!num) {
	651	+ printf("No TSECs initialized\n");
	652	+ return 0;
	653	+ }
	654	+
	655	+ if ((sdrs2_io_sel == 4) \|\| (sdrs2_io_sel == 6))
	656	+ fsl_sgmii_riser_init(tsec_info, num);
	657	+
	658	+ tsec_eth_init(bis, tsec_info, num);
	659	+#endif
	660	+ return pci_eth_init(bis);
619	661	}
620	662
621	663	#if defined(CONFIG_OF_BOARD_SETUP)
...	...	@@ -427,6 +427,9 @@
427	427	#define CONFIG_TSEC3 1
428	428	#define CONFIG_TSEC3_NAME "eTSEC3"
429	429
	430	+#define CONFIG_FSL_SGMII_RISER 1
	431	+#define SGMII_RISER_PHY_OFFSET 0x1c
	432	+
430	433	#define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */
431	434	#define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */
432	435