mpc83xx: Add NAND boot support for MPC8315E-RDB boards

The core support for NAND booting is there already, so this patch is pretty straightforward. There is one trick though: top level Makefile expects nand_spl to be in nand_spl/board/$(BOARDDIR), but we can fully reuse the code from mpc8313erdb boards, and so to not duplicate the code we just symlink nand_spl/board/freescale/mpc8315erdb to mpc8313erdb. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> o silence make during ln echo o update documentation o and avoid: $ ./MAKEALL MPC8315ERDB_NAND Configuring for MPC8315ERDB board... sdram.o: In function `fixed_sdram': /home/r1aaha/git/u-boot/nand_spl/board/freescale/mpc8313erdb/sdram.c:72: undefined reference to `udelay' by renaming udelay -> __udelay in the spirit of commit 3eb90bad651fab39cffba750ec4421a9c01d60e7 "Generic udelay() with watchdog support". Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

mpc83xx: Add NAND boot support for MPC8315E-RDB boards
The core support for NAND booting is there already, so this patch is pretty straightforward. There is one trick though: top level Makefile expects nand_spl to be in nand_spl/board/$(BOARDDIR), but we can fully reuse the code from mpc8313erdb boards, and so to not duplicate the code we just symlink nand_spl/board/freescale/mpc8315erdb to mpc8313erdb. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> o silence make during ln echo o update documentation o and avoid: $ ./MAKEALL MPC8315ERDB_NAND Configuring for MPC8315ERDB board... sdram.o: In function `fixed_sdram': /home/r1aaha/git/u-boot/nand_spl/board/freescale/mpc8313erdb/sdram.c:72: undefined reference to `udelay' by renaming udelay -> __udelay in the spirit of commit 3eb90bad651fab39cffba750ec4421a9c01d60e7 "Generic udelay() with watchdog support". Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Anton Vorontsov · Kim Phillips
1 parent 6ca9da4d42
Showing 7 changed files with 167 additions and 23 deletions Side-by-side Diff
MAKEALL
Makefile
board/freescale/mpc8315erdb/config.mk
board/freescale/mpc8315erdb/mpc8315erdb.c
board/freescale/mpc8315erdb/sdram.c
doc/README.mpc8315erdb
include/configs/MPC8315ERDB.h
@@ -362,6 +362,7 @@
 	MPC8313ERDB_33	\
 	MPC8313ERDB_NAND_66	\
 	MPC8315ERDB	\
+	MPC8315ERDB_NAND	\
 	MPC8323ERDB	\
 	MPC832XEMDS	\
 	MPC832XEMDS_ATM	\
@@ -2261,8 +2261,12 @@
 		echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk ; \
 	fi ;
  
+MPC8315ERDB_NAND_config \
 MPC8315ERDB_config: unconfig
-	@$(MKCONFIG) -a MPC8315ERDB ppc mpc83xx mpc8315erdb freescale
+	@if [ "$(findstring _NAND_,$@)" ] ; then \
+		ln -sf mpc8313erdb nand_spl/board/freescale/mpc8315erdb ; \
+	fi ;
+	@$(MKCONFIG) -t $(@:_config=) MPC8315ERDB ppc mpc83xx mpc8315erdb freescale
  
 MPC8323ERDB_config:	unconfig
 	@$(MKCONFIG) -a MPC8323ERDB ppc mpc83xx mpc8323erdb freescale
+ifndef NAND_SPL
+ifeq ($(CONFIG_MK_NAND), y)
+TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
+endif
+endif
+
+ifndef TEXT_BASE
 TEXT_BASE = 0xFE000000
+endif
@@ -32,6 +32,8 @@
 #include <mpc83xx.h>
 #include <netdev.h>
 #include <asm/io.h>
+#include <ns16550.h>
+#include <nand.h>
  
 DECLARE_GLOBAL_DATA_PTR;
  
@@ -45,6 +47,8 @@
 	return 0;
 }
  
+#ifndef CONFIG_NAND_SPL
+
 static u8 read_board_info(void)
 {
 	u8 val8;
@@ -220,4 +224,42 @@
 	cpu_eth_init(bis);	/* Initialize TSECs first */
 	return pci_eth_init(bis);
 }
+
+#else /* CONFIG_NAND_SPL */
+
+int checkboard(void)
+{
+	puts("Board: Freescale MPC8315ERDB\n");
+	return 0;
+}
+
+void board_init_f(ulong bootflag)
+{
+	board_early_init_f();
+	NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
+		     CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+	puts("NAND boot... ");
+	init_timebase();
+	initdram(0);
+	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
+		      CONFIG_SYS_NAND_U_BOOT_RELOC);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	nand_boot();
+}
+
+void putc(char c)
+{
+	if (gd->flags & GD_FLG_SILENT)
+		return;
+
+	if (c == '\n')
+		NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
+
+	NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
+}
+
+#endif /* CONFIG_NAND_SPL */
@@ -54,6 +54,7 @@
  * This is useful for faster booting in configs where the RAM is unlikely
  * to be changed, or for things like NAND booting where space is tight.
  */
+#ifndef CONFIG_SYS_RAMBOOT
 static long fixed_sdram(void)
 {
 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
@@ -68,7 +69,7 @@
 	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
 	 * or the DDR2 controller may fail to initialize correctly.
 	 */
-	udelay(50000);
+	__udelay(50000);
  
 	im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
 	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
@@ -100,6 +101,12 @@
  
 	return msize;
 }
+#else
+static long fixed_sdram(void)
+{
+	return CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+}
+#endif /* CONFIG_SYS_RAMBOOT */
  
 phys_size_t initdram(int board_type)
 {
@@ -15,6 +15,18 @@
 	  4321		  4321
 	(where the '*' indicates the position of the tab of the switch.)
  
+	To boot the image at the beginning of NAND flash, use these
+	DIP switch settings for S3 S4:
+
+	+------+	+------+
+	| *    |	|  *** |
+	|  *** |	| *    |
+	+------+ ON	+------+ ON
+	  4321		  4321
+	(where the '*' indicates the position of the tab of the switch.)
+
+	When booting from NAND, use u-boot-nand.bin, not u-boot.bin.
+
 2.	Memory Map
 	The memory map looks like this:
  
@@ -26,6 +38,9 @@
 	0xe060_0000	0xe060_7fff	NAND FLASH (CS1) 32K
 	0xfe00_0000	0xfe7f_ffff	NOR FLASH (CS0)	 8M
  
+	When booting from NAND, NAND flash is CS0 and NOR flash
+	is CS1.
+
 3.	Definitions
  
 3.1	Explanation of NEW definitions in:
  
@@ -43,13 +58,15 @@
  
 	export CROSS_COMPILE=your-cross-compiler-prefix-
 	make distclean
-	make MPC8315ERDB_config
+	make MPC8315ERDB_config (or MPC8315ERDB_NAND_config for u-boot-nand.bin)
 	make all
  
 5.	Downloading and Flashing Images
  
 5.1	Reflash U-boot Image using U-boot
  
+	NOR flash:
+
 	tftp 40000 u-boot.bin
 	protect off all
 	erase fe000000 fe1fffff
@@ -60,6 +77,15 @@
 	You have to supply the correct byte count with 'xxxx'
 	from the TFTP result log.
  
+	NAND flash:
+
+	=>tftpboot $loadaddr <filename>
+	=>nand erase 0 0x80000
+	=>nand write $loadaddr 0 0x80000
+
+	...where 0x80000 is the filesize rounded up to
+	the next 0x20000 increment.
+
 5.2	Downloading and Booting Linux Kernel
  
 	Ensure that all networking-related environment variables are set
@@ -76,6 +102,5 @@
  
 6	Notes
  
-	Booting from NAND flash is not yet supported.
 	The console baudrate for MPC8315ERDB is 115200bps.
@@ -25,6 +25,11 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
  
+#ifdef CONFIG_MK_NAND
+#define CONFIG_NAND_U_BOOT		1
+#define CONFIG_RAMBOOT_TEXT_BASE	0x00100000
+#endif
+
 /*
  * High Level Configuration Options
  */
  
  
  
@@ -51,20 +56,29 @@
 	HRCWL_SVCOD_DIV_2 |\
 	HRCWL_CSB_TO_CLKIN_2X1 |\
 	HRCWL_CORE_TO_CSB_3X1)
-#define CONFIG_SYS_HRCW_HIGH (\
+#define CONFIG_SYS_HRCW_HIGH_BASE (\
 	HRCWH_PCI_HOST |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
 	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0X00000100 |\
 	HRCWH_BOOTSEQ_DISABLE |\
 	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_RL_EXT_LEGACY |\
 	HRCWH_TSEC1M_IN_RGMII |\
 	HRCWH_TSEC2M_IN_RGMII |\
 	HRCWH_BIG_ENDIAN |\
 	HRCWH_LALE_NORMAL)
  
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
+		       HRCWH_FROM_0XFFF00100 |\
+		       HRCWH_ROM_LOC_NAND_SP_8BIT |\
+		       HRCWH_RL_EXT_NAND)
+#else
+#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
+		       HRCWH_FROM_0X00000100 |\
+		       HRCWH_ROM_LOC_LOCAL_16BIT |\
+		       HRCWH_RL_EXT_LEGACY)
+#endif
+
 /*
  * System IO Config
  */
@@ -79,6 +93,10 @@
  */
 #define CONFIG_SYS_IMMR		0xE0000000
  
+#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#define CONFIG_DEFAULT_IMMR	CONFIG_SYS_IMMR
+#endif
+
 /*
  * Arbiter Setup
  */
@@ -161,12 +179,6 @@
  */
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE /* start of monitor */
  
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
 #define CONFIG_SYS_MONITOR_LEN		(384 * 1024) /* Reserve 384 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN		(512 * 1024) /* Reserved for malloc */
  
  
@@ -200,10 +212,10 @@
 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE /* Window base at flash base */
 #define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000016 /* 8MB window size */
  
-#define CONFIG_SYS_BR0_PRELIM		( CONFIG_SYS_FLASH_BASE	/* Flash Base address */ \
+#define CONFIG_SYS_NOR_BR_PRELIM	(CONFIG_SYS_FLASH_BASE \
 				| (2 << BR_PS_SHIFT)	/* 16 bit port size */ \
 				| BR_V )		/* valid */
-#define CONFIG_SYS_OR0_PRELIM		( (~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
+#define CONFIG_SYS_NOR_OR_PRELIM	((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
 				| OR_UPM_XAM \
 				| OR_GPCM_CSNT \
 				| OR_GPCM_ACS_DIV2 \
  
  
  
@@ -223,18 +235,31 @@
 /*
  * NAND Flash on the Local Bus
  */
-#define CONFIG_SYS_NAND_BASE		0xE0600000	/* 0xE0600000 */
+
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_NAND_BASE		0xFFF00000
+#else
+#define CONFIG_SYS_NAND_BASE		0xE0600000
+#endif
+
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_MTD_NAND_VERIFY_WRITE	1
 #define CONFIG_CMD_NAND			1
 #define CONFIG_NAND_FSL_ELBC		1
+#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
  
-#define CONFIG_SYS_BR1_PRELIM	( CONFIG_SYS_NAND_BASE \
+#define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
+#define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
+#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
+
+#define CONFIG_SYS_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE \
 				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
 				| BR_PS_8		/* Port Size = 8 bit */ \
 				| BR_MS_FCM		/* MSEL = FCM */ \
 				| BR_V )		/* valid */
-#define CONFIG_SYS_OR1_PRELIM	( 0xFFFF8000		/* length 32K */ \
+#define CONFIG_SYS_NAND_OR_PRELIM	(0xFFFF8000	/* length 32K */ \
 				| OR_FCM_CSCT \
 				| OR_FCM_CST \
 				| OR_FCM_CHT \
  
@@ -243,9 +268,31 @@
 				| OR_FCM_EHTR )
 				/* 0xFFFF8396 */
  
+#ifdef CONFIG_NAND_U_BOOT
+#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
+#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
+#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
+#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
+#else
+#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
+#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
+#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
+#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
+#endif
+
 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
 #define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000000E	/* 32KB  */
  
+#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
+#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
+
+#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
+	!defined(CONFIG_NAND_SPL)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
 /*
  * Serial Port
  */
@@ -254,7 +301,7 @@
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550_CLK		(CONFIG_83XX_CLKIN * 2)
  
 #define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
@@ -408,7 +455,16 @@
 /*
  * Environment
  */
-#ifndef CONFIG_SYS_RAMBOOT
+#if defined(CONFIG_NAND_U_BOOT)
+	#define CONFIG_ENV_IS_IN_NAND	1
+	#define CONFIG_ENV_OFFSET		(512 * 1024)
+	#define CONFIG_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+	#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+	#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+	#define CONFIG_ENV_RANGE	(CONFIG_ENV_SECT_SIZE * 4)
+	#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
+						 CONFIG_ENV_RANGE)
+#elif !defined(CONFIG_SYS_RAMBOOT)
 	#define CONFIG_ENV_IS_IN_FLASH	1
 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 	#define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K(one sector) for env */
@@ -442,7 +498,7 @@
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_PCI
  
-#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
     #undef CONFIG_CMD_SAVEENV
     #undef CONFIG_CMD_LOADS
 #endif
@@ -504,7 +560,8 @@
  
 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_FLASH_BASE | BATU_BL_32M | \
+				 BATU_VS | BATU_VP)
 #define CONFIG_SYS_DBAT2L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
...	...	@@ -362,6 +362,7 @@
362	362	MPC8313ERDB_33 \
363	363	MPC8313ERDB_NAND_66 \
364	364	MPC8315ERDB \
	365	+ MPC8315ERDB_NAND \
365	366	MPC8323ERDB \
366	367	MPC832XEMDS \
367	368	MPC832XEMDS_ATM \
...	...	@@ -2261,8 +2261,12 @@
2261	2261	echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk ; \
2262	2262	fi ;
2263	2263
	2264	+MPC8315ERDB_NAND_config \
2264	2265	MPC8315ERDB_config: unconfig
2265		- @$(MKCONFIG) -a MPC8315ERDB ppc mpc83xx mpc8315erdb freescale
	2266	+ @if [ "$(findstring _NAND_,$@)" ] ; then \
	2267	+ ln -sf mpc8313erdb nand_spl/board/freescale/mpc8315erdb ; \
	2268	+ fi ;
	2269	+ @$(MKCONFIG) -t $(@:_config=) MPC8315ERDB ppc mpc83xx mpc8315erdb freescale
2266	2270
2267	2271	MPC8323ERDB_config: unconfig
2268	2272	@$(MKCONFIG) -a MPC8323ERDB ppc mpc83xx mpc8323erdb freescale
	1	+ifndef NAND_SPL
	2	+ifeq ($(CONFIG_MK_NAND), y)
	3	+TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
	4	+endif
	5	+endif
	6	+
	7	+ifndef TEXT_BASE
1	8	TEXT_BASE = 0xFE000000
	9	+endif
...	...	@@ -32,6 +32,8 @@
32	32	#include <mpc83xx.h>
33	33	#include <netdev.h>
34	34	#include <asm/io.h>
	35	+#include <ns16550.h>
	36	+#include <nand.h>
35	37
36	38	DECLARE_GLOBAL_DATA_PTR;
37	39
...	...	@@ -45,6 +47,8 @@
45	47	return 0;
46	48	}
47	49
	50	+#ifndef CONFIG_NAND_SPL
	51	+
48	52	static u8 read_board_info(void)
49	53	{
50	54	u8 val8;
...	...	@@ -220,4 +224,42 @@
220	224	cpu_eth_init(bis); /* Initialize TSECs first */
221	225	return pci_eth_init(bis);
222	226	}
	227	+
	228	+#else /* CONFIG_NAND_SPL */
	229	+
	230	+int checkboard(void)
	231	+{
	232	+ puts("Board: Freescale MPC8315ERDB\n");
	233	+ return 0;
	234	+}
	235	+
	236	+void board_init_f(ulong bootflag)
	237	+{
	238	+ board_early_init_f();
	239	+ NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
	240	+ CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
	241	+ puts("NAND boot... ");
	242	+ init_timebase();
	243	+ initdram(0);
	244	+ relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
	245	+ CONFIG_SYS_NAND_U_BOOT_RELOC);
	246	+}
	247	+
	248	+void board_init_r(gd_t *gd, ulong dest_addr)
	249	+{
	250	+ nand_boot();
	251	+}
	252	+
	253	+void putc(char c)
	254	+{
	255	+ if (gd->flags & GD_FLG_SILENT)
	256	+ return;
	257	+
	258	+ if (c == '\n')
	259	+ NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
	260	+
	261	+ NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
	262	+}
	263	+
	264	+#endif /* CONFIG_NAND_SPL */
...	...	@@ -54,6 +54,7 @@
54	54	* This is useful for faster booting in configs where the RAM is unlikely
55	55	* to be changed, or for things like NAND booting where space is tight.
56	56	*/
	57	+#ifndef CONFIG_SYS_RAMBOOT
57	58	static long fixed_sdram(void)
58	59	{
59	60	volatile immap_t im = (volatile immap_t )CONFIG_SYS_IMMR;
...	...	@@ -68,7 +69,7 @@
68	69	* Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
69	70	* or the DDR2 controller may fail to initialize correctly.
70	71	*/
71		- udelay(50000);
	72	+ __udelay(50000);
72	73
73	74	im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
74	75	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
...	...	@@ -100,6 +101,12 @@
100	101
101	102	return msize;
102	103	}
	104	+#else
	105	+static long fixed_sdram(void)
	106	+{
	107	+ return CONFIG_SYS_DDR_SIZE * 1024 * 1024;
	108	+}
	109	+#endif /* CONFIG_SYS_RAMBOOT */
103	110
104	111	phys_size_t initdram(int board_type)
105	112	{
...	...	@@ -15,6 +15,18 @@
15	15	4321 4321
16	16	(where the '*' indicates the position of the tab of the switch.)
17	17
	18	+ To boot the image at the beginning of NAND flash, use these
	19	+ DIP switch settings for S3 S4:
	20	+
	21	+ +------+ +------+
	22	+ \| * \| \| *** \|
	23	+ \| *** \| \| * \|
	24	+ +------+ ON +------+ ON
	25	+ 4321 4321
	26	+ (where the '*' indicates the position of the tab of the switch.)
	27	+
	28	+ When booting from NAND, use u-boot-nand.bin, not u-boot.bin.
	29	+
18	30	2. Memory Map
19	31	The memory map looks like this:
20	32
...	...	@@ -26,6 +38,9 @@
26	38	0xe060_0000 0xe060_7fff NAND FLASH (CS1) 32K
27	39	0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0) 8M
28	40
	41	+ When booting from NAND, NAND flash is CS0 and NOR flash
	42	+ is CS1.
	43	+
29	44	3. Definitions
30	45
31	46	3.1 Explanation of NEW definitions in:
32	47
...	...	@@ -43,13 +58,15 @@
43	58
44	59	export CROSS_COMPILE=your-cross-compiler-prefix-
45	60	make distclean
46		- make MPC8315ERDB_config
	61	+ make MPC8315ERDB_config (or MPC8315ERDB_NAND_config for u-boot-nand.bin)
47	62	make all
48	63
49	64	5. Downloading and Flashing Images
50	65
51	66	5.1 Reflash U-boot Image using U-boot
52	67
	68	+ NOR flash:
	69	+
53	70	tftp 40000 u-boot.bin
54	71	protect off all
55	72	erase fe000000 fe1fffff
...	...	@@ -60,6 +77,15 @@
60	77	You have to supply the correct byte count with 'xxxx'
61	78	from the TFTP result log.
62	79
	80	+ NAND flash:
	81	+
	82	+ =>tftpboot $loadaddr <filename>
	83	+ =>nand erase 0 0x80000
	84	+ =>nand write $loadaddr 0 0x80000
	85	+
	86	+ ...where 0x80000 is the filesize rounded up to
	87	+ the next 0x20000 increment.
	88	+
63	89	5.2 Downloading and Booting Linux Kernel
64	90
65	91	Ensure that all networking-related environment variables are set
...	...	@@ -76,6 +102,5 @@
76	102
77	103	6 Notes
78	104
79		- Booting from NAND flash is not yet supported.
80	105	The console baudrate for MPC8315ERDB is 115200bps.
...	...	@@ -25,6 +25,11 @@
25	25	#ifndef __CONFIG_H
26	26	#define __CONFIG_H
27	27
	28	+#ifdef CONFIG_MK_NAND
	29	+#define CONFIG_NAND_U_BOOT 1
	30	+#define CONFIG_RAMBOOT_TEXT_BASE 0x00100000
	31	+#endif
	32	+
28	33	/*
29	34	* High Level Configuration Options
30	35	*/
31	36
32	37
33	38
...	...	@@ -51,20 +56,29 @@
51	56	HRCWL_SVCOD_DIV_2 \|\
52	57	HRCWL_CSB_TO_CLKIN_2X1 \|\
53	58	HRCWL_CORE_TO_CSB_3X1)
54		-#define CONFIG_SYS_HRCW_HIGH (\
	59	+#define CONFIG_SYS_HRCW_HIGH_BASE (\
55	60	HRCWH_PCI_HOST \|\
56	61	HRCWH_PCI1_ARBITER_ENABLE \|\
57	62	HRCWH_CORE_ENABLE \|\
58		- HRCWH_FROM_0X00000100 \|\
59	63	HRCWH_BOOTSEQ_DISABLE \|\
60	64	HRCWH_SW_WATCHDOG_DISABLE \|\
61		- HRCWH_ROM_LOC_LOCAL_16BIT \|\
62		- HRCWH_RL_EXT_LEGACY \|\
63	65	HRCWH_TSEC1M_IN_RGMII \|\
64	66	HRCWH_TSEC2M_IN_RGMII \|\
65	67	HRCWH_BIG_ENDIAN \|\
66	68	HRCWH_LALE_NORMAL)
67	69
	70	+#ifdef CONFIG_NAND_SPL
	71	+#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE \|\
	72	+ HRCWH_FROM_0XFFF00100 \|\
	73	+ HRCWH_ROM_LOC_NAND_SP_8BIT \|\
	74	+ HRCWH_RL_EXT_NAND)
	75	+#else
	76	+#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE \|\
	77	+ HRCWH_FROM_0X00000100 \|\
	78	+ HRCWH_ROM_LOC_LOCAL_16BIT \|\
	79	+ HRCWH_RL_EXT_LEGACY)
	80	+#endif
	81	+
68	82	/*
69	83	* System IO Config
70	84	*/
...	...	@@ -79,6 +93,10 @@
79	93	*/
80	94	#define CONFIG_SYS_IMMR 0xE0000000
81	95
	96	+#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
	97	+#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
	98	+#endif
	99	+
82	100	/*
83	101	* Arbiter Setup
84	102	*/
...	...	@@ -161,12 +179,6 @@
161	179	*/
162	180	#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
163	181
164		-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
165		-#define CONFIG_SYS_RAMBOOT
166		-#else
167		-#undef CONFIG_SYS_RAMBOOT
168		-#endif
169		-
170	182	#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
171	183	#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
172	184
173	185
...	...	@@ -200,10 +212,10 @@
200	212	#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
201	213	#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */
202	214
203		-#define CONFIG_SYS_BR0_PRELIM ( CONFIG_SYS_FLASH_BASE /* Flash Base address */ \
	215	+#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
204	216	\| (2 << BR_PS_SHIFT) /* 16 bit port size */ \
205	217	\| BR_V ) /* valid */
206		-#define CONFIG_SYS_OR0_PRELIM ( (~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
	218	+#define CONFIG_SYS_NOR_OR_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
207	219	\| OR_UPM_XAM \
208	220	\| OR_GPCM_CSNT \
209	221	\| OR_GPCM_ACS_DIV2 \
210	222
211	223
212	224
...	...	@@ -223,18 +235,31 @@
223	235	/*
224	236	* NAND Flash on the Local Bus
225	237	*/
226		-#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
	238	+
	239	+#ifdef CONFIG_NAND_SPL
	240	+#define CONFIG_SYS_NAND_BASE 0xFFF00000
	241	+#else
	242	+#define CONFIG_SYS_NAND_BASE 0xE0600000
	243	+#endif
	244	+
227	245	#define CONFIG_SYS_MAX_NAND_DEVICE 1
228	246	#define CONFIG_MTD_NAND_VERIFY_WRITE 1
229	247	#define CONFIG_CMD_NAND 1
230	248	#define CONFIG_NAND_FSL_ELBC 1
	249	+#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
231	250
232		-#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \
	251	+#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
	252	+#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
	253	+#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
	254	+#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
	255	+#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
	256	+
	257	+#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
233	258	\| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
234	259	\| BR_PS_8 /* Port Size = 8 bit */ \
235	260	\| BR_MS_FCM /* MSEL = FCM */ \
236	261	\| BR_V ) /* valid */
237		-#define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \
	262	+#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFF8000 /* length 32K */ \
238	263	\| OR_FCM_CSCT \
239	264	\| OR_FCM_CST \
240	265	\| OR_FCM_CHT \
241	266
...	...	@@ -243,9 +268,31 @@
243	268	\| OR_FCM_EHTR )
244	269	/* 0xFFFF8396 */
245	270
	271	+#ifdef CONFIG_NAND_U_BOOT
	272	+#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
	273	+#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
	274	+#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
	275	+#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
	276	+#else
	277	+#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
	278	+#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
	279	+#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
	280	+#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
	281	+#endif
	282	+
246	283	#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
247	284	#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
248	285
	286	+#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
	287	+#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
	288	+
	289	+#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
	290	+ !defined(CONFIG_NAND_SPL)
	291	+#define CONFIG_SYS_RAMBOOT
	292	+#else
	293	+#undef CONFIG_SYS_RAMBOOT
	294	+#endif
	295	+
249	296	/*
250	297	* Serial Port
251	298	*/
...	...	@@ -254,7 +301,7 @@
254	301	#define CONFIG_SYS_NS16550
255	302	#define CONFIG_SYS_NS16550_SERIAL
256	303	#define CONFIG_SYS_NS16550_REG_SIZE 1
257		-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	304	+#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
258	305
259	306	#define CONFIG_SYS_BAUDRATE_TABLE \
260	307	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
...	...	@@ -408,7 +455,16 @@
408	455	/*
409	456	* Environment
410	457	*/
411		-#ifndef CONFIG_SYS_RAMBOOT
	458	+#if defined(CONFIG_NAND_U_BOOT)
	459	+ #define CONFIG_ENV_IS_IN_NAND 1
	460	+ #define CONFIG_ENV_OFFSET (512 * 1024)
	461	+ #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
	462	+ #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
	463	+ #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
	464	+ #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
	465	+ #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
	466	+ CONFIG_ENV_RANGE)
	467	+#elif !defined(CONFIG_SYS_RAMBOOT)
412	468	#define CONFIG_ENV_IS_IN_FLASH 1
413	469	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
414	470	#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
...	...	@@ -442,7 +498,7 @@
442	498	#define CONFIG_CMD_DATE
443	499	#define CONFIG_CMD_PCI
444	500
445		-#if defined(CONFIG_SYS_RAMBOOT)
	501	+#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
446	502	#undef CONFIG_CMD_SAVEENV
447	503	#undef CONFIG_CMD_LOADS
448	504	#endif
...	...	@@ -504,7 +560,8 @@
504	560
505	561	/* FLASH: icache cacheable, but dcache-inhibit and guarded */
506	562	#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
507		-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \| BATU_BL_8M \| BATU_VS \| BATU_VP)
	563	+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \| BATU_BL_32M \| \
	564	+ BATU_VS \| BATU_VP)
508	565	#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \| BATL_PP_10 \| \
509	566	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
510	567	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U