MLK-12483-5 mx6ul: Enable module fuse check EVK board and DDR3 ARM2 board

Enable the configurations CONFIG_MODULE_FUSE and CONFIG_OF_SYSTEM_SETUP for module fuse check. And modify board level codes for SD, FEC and EIM. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit f9d57bc73807d14062721a793a2a55be69aa4973)

MLK-12483-5 mx6ul: Enable module fuse check EVK board and DDR3 ARM2 board
Enable the configurations CONFIG_MODULE_FUSE and CONFIG_OF_SYSTEM_SETUP for module fuse check. And modify board level codes for SD, FEC and EIM. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit f9d57bc73807d14062721a793a2a55be69aa4973)
Ye Li · guoyin.chen
1 parent 952524c736
Showing 4 changed files with 49 additions and 2 deletions Side-by-side Diff
board/freescale/mx6ul_14x14_ddr3_arm2/mx6ul_14x14_ddr3_arm2.c
board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
include/configs/mx6ul_14x14_ddr3_arm2.h
include/configs/mx6ul_14x14_evk.h
@@ -339,10 +339,25 @@
  
 static void setup_eimnor(void)
 {
+	if (check_module_fused(MX6_MODULE_EIM)) {
+		printf("WEIM@0x%x is fused, disable it\n", WEIM_BASE_ADDR);
+		return;
+	}
+
 	imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads));
  
 	eimnor_cs_setup();
 }
+
+int board_flash_wp_on(void)
+{
+	if (check_module_fused(MX6_MODULE_EIM)) {
+		return 1; /* Skip flash init */
+	}
+
+	return 0;
+}
+
 #endif
  
 #ifdef CONFIG_FEC_MXC
  
@@ -489,11 +504,17 @@
 	/* BOOT_CFG2[3] and BOOT_CFG2[4] */
 	dev_no = (soc_sbmr & 0x00001800) >> 11;
  
+	if (dev_no == 1 && mx6_esdhc_fused(USDHC1_BASE_ADDR))
+		dev_no = 0;
+
 	return dev_no;
 }
  
 int mmc_map_to_kernel_blk(int dev_no)
 {
+	if (dev_no == 0 && mx6_esdhc_fused(USDHC1_BASE_ADDR))
+		dev_no = 1;
+	
 	return dev_no;
 }
  
@@ -532,7 +553,7 @@
 	 */
 	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 		switch (i) {
-		case 0:
+		case 0:			
 #ifdef CONFIG_MX6UL_DDR3_ARM2_EMMC_REWORK
 			imx_iomux_v3_setup_multiple_pads(
 				usdhc1_emmc_pads, ARRAY_SIZE(usdhc1_emmc_pads));
@@ -735,6 +756,10 @@
 	int ret;
  
 	if (0 == fec_id) {
+		if (check_module_fused(MX6_MODULE_ENET1)) {
+			return -1;
+		}
+		
 		/*
 		 * Use 50M anatop loopback REF_CLK1 for ENET1,
 		 * clear gpr1[13], set gpr1[17]
@@ -746,6 +771,10 @@
 			return ret;
  
 	} else {
+		if (check_module_fused(MX6_MODULE_ENET2)) {
+			return -1;
+		}
+	
 		/* clk from phy, set gpr1[14], clear gpr1[18]*/
 		clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
 				IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK);
@@ -488,11 +488,17 @@
 	/* BOOT_CFG2[3] and BOOT_CFG2[4] */
 	dev_no = (soc_sbmr & 0x00001800) >> 11;
  
+	if (dev_no == 1 && mx6_esdhc_fused(USDHC1_BASE_ADDR))
+		dev_no = 0;
+
 	return dev_no;
 }
  
 int mmc_map_to_kernel_blk(int dev_no)
 {
+	if (dev_no == 0 && mx6_esdhc_fused(USDHC1_BASE_ADDR))
+		dev_no = 1;
+	
 	return dev_no;
 }
  
@@ -570,7 +576,6 @@
 			ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 			if (ret) {
 				printf("Warning: failed to initialize mmc dev %d\n", i);
-				return ret;
 			}
 	}
  
  
@@ -750,10 +755,18 @@
 	int ret;
  
 	if (0 == fec_id) {
+		if (check_module_fused(MX6_MODULE_ENET1)) {
+			return -1;
+		}
+		
 		/* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]*/
 		clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
 				IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
 	} else {
+		if (check_module_fused(MX6_MODULE_ENET2)) {
+			return -1;
+		}
+		
 		/* Use 50M anatop loopback REF_CLK2 for ENET2, clear gpr1[14], set gpr1[18]*/
 		clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
 				IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
@@ -71,5 +71,7 @@
 #define CONFIG_FEC_DMA_MINALIGN		64
 #endif
  
+#define CONFIG_MODULE_FUSE
+#define CONFIG_OF_SYSTEM_SETUP
 #endif
@@ -423,6 +423,9 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
 #endif
  
+#define CONFIG_MODULE_FUSE
+#define CONFIG_OF_SYSTEM_SETUP
+
 #if defined(CONFIG_ANDROID_SUPPORT)
 #include "mx6ul_14x14_evk_android.h"
 #endif
...	...	@@ -339,10 +339,25 @@
339	339
340	340	static void setup_eimnor(void)
341	341	{
	342	+ if (check_module_fused(MX6_MODULE_EIM)) {
	343	+ printf("WEIM@0x%x is fused, disable it\n", WEIM_BASE_ADDR);
	344	+ return;
	345	+ }
	346	+
342	347	imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads));
343	348
344	349	eimnor_cs_setup();
345	350	}
	351	+
	352	+int board_flash_wp_on(void)
	353	+{
	354	+ if (check_module_fused(MX6_MODULE_EIM)) {
	355	+ return 1; /* Skip flash init */
	356	+ }
	357	+
	358	+ return 0;
	359	+}
	360	+
346	361	#endif
347	362
348	363	#ifdef CONFIG_FEC_MXC
349	364
...	...	@@ -489,11 +504,17 @@
489	504	/* BOOT_CFG2[3] and BOOT_CFG2[4] */
490	505	dev_no = (soc_sbmr & 0x00001800) >> 11;
491	506
	507	+ if (dev_no == 1 && mx6_esdhc_fused(USDHC1_BASE_ADDR))
	508	+ dev_no = 0;
	509	+
492	510	return dev_no;
493	511	}
494	512
495	513	int mmc_map_to_kernel_blk(int dev_no)
496	514	{
	515	+ if (dev_no == 0 && mx6_esdhc_fused(USDHC1_BASE_ADDR))
	516	+ dev_no = 1;
	517	+
497	518	return dev_no;
498	519	}
499	520
...	...	@@ -532,7 +553,7 @@
532	553	*/
533	554	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
534	555	switch (i) {
535		- case 0:
	556	+ case 0:
536	557	#ifdef CONFIG_MX6UL_DDR3_ARM2_EMMC_REWORK
537	558	imx_iomux_v3_setup_multiple_pads(
538	559	usdhc1_emmc_pads, ARRAY_SIZE(usdhc1_emmc_pads));
...	...	@@ -735,6 +756,10 @@
735	756	int ret;
736	757
737	758	if (0 == fec_id) {
	759	+ if (check_module_fused(MX6_MODULE_ENET1)) {
	760	+ return -1;
	761	+ }
	762	+
738	763	/*
739	764	* Use 50M anatop loopback REF_CLK1 for ENET1,
740	765	* clear gpr1[13], set gpr1[17]
...	...	@@ -746,6 +771,10 @@
746	771	return ret;
747	772
748	773	} else {
	774	+ if (check_module_fused(MX6_MODULE_ENET2)) {
	775	+ return -1;
	776	+ }
	777	+
749	778	/* clk from phy, set gpr1[14], clear gpr1[18]*/
750	779	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
751	780	IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK);
...	...	@@ -488,11 +488,17 @@
488	488	/* BOOT_CFG2[3] and BOOT_CFG2[4] */
489	489	dev_no = (soc_sbmr & 0x00001800) >> 11;
490	490
	491	+ if (dev_no == 1 && mx6_esdhc_fused(USDHC1_BASE_ADDR))
	492	+ dev_no = 0;
	493	+
491	494	return dev_no;
492	495	}
493	496
494	497	int mmc_map_to_kernel_blk(int dev_no)
495	498	{
	499	+ if (dev_no == 0 && mx6_esdhc_fused(USDHC1_BASE_ADDR))
	500	+ dev_no = 1;
	501	+
496	502	return dev_no;
497	503	}
498	504
...	...	@@ -570,7 +576,6 @@
570	576	ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
571	577	if (ret) {
572	578	printf("Warning: failed to initialize mmc dev %d\n", i);
573		- return ret;
574	579	}
575	580	}
576	581
577	582
...	...	@@ -750,10 +755,18 @@
750	755	int ret;
751	756
752	757	if (0 == fec_id) {
	758	+ if (check_module_fused(MX6_MODULE_ENET1)) {
	759	+ return -1;
	760	+ }
	761	+
753	762	/* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]*/
754	763	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
755	764	IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
756	765	} else {
	766	+ if (check_module_fused(MX6_MODULE_ENET2)) {
	767	+ return -1;
	768	+ }
	769	+
757	770	/* Use 50M anatop loopback REF_CLK2 for ENET2, clear gpr1[14], set gpr1[18]*/
758	771	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
759	772	IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
...	...	@@ -71,5 +71,7 @@
71	71	#define CONFIG_FEC_DMA_MINALIGN 64
72	72	#endif
73	73
	74	+#define CONFIG_MODULE_FUSE
	75	+#define CONFIG_OF_SYSTEM_SETUP
74	76	#endif
...	...	@@ -423,6 +423,9 @@
423	423	#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
424	424	#endif
425	425
	426	+#define CONFIG_MODULE_FUSE
	427	+#define CONFIG_OF_SYSTEM_SETUP
	428	+
426	429	#if defined(CONFIG_ANDROID_SUPPORT)
427	430	#include "mx6ul_14x14_evk_android.h"
428	431	#endif