Eric Lee / smarc-uboot

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Commit 3064f322783241f83b8e25b5acdd97a0d898a970

Authored by Tom Warren
Committed by Tom Rini
1 parent 66b796a560
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Tegra20: Move some code files to common directories for upcoming Tegra30 patches. 

Move files that are going to be common between T20 and T30 into 'tegra-common'
subdirs in AVP (arm720t), CPU (armv7), and shared (arch/arm/cpu/.) areas. Any
files that are left behind in '/tegra20' will be copied to '/tegra30' subdirs
and modified for that SoC. The 'common' files should need only minor changes.

Include files (arch/arm/include/asm/arch-tegra/tegra20) will be done in a
follow-on patch.

Builds fine w/MAKEALL -s tegra20. Checkpatch.pl is clean.

Signed-off-by: Tom Warren <twarren@nvidia.com>

Showing 27 changed files with 937 additions and 793 deletions Side-by-side Diff

... ... @@ -343,6 +343,8 @@
343 343 endif
344 344 ifeq ($(SOC),tegra20)
345 345 LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o
  346 +LIBS-y += arch/$(ARCH)/cpu/tegra-common/libcputegra-common.o
  347 +LIBS-y += $(CPUDIR)/tegra-common/libtegra-common.o
346 348 endif
347 349  
348 350 LIBS := $(addprefix $(obj),$(sort $(LIBS-y)))
arch/arm/cpu/arm720t/tegra-common/Makefile
Diff comments   View file @ 3064f32
  1 +#
  2 +# (C) Copyright 2010,2011 Nvidia Corporation.
  3 +#
  4 +# (C) Copyright 2000-2008
  5 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  6 +#
  7 +# See file CREDITS for list of people who contributed to this
  8 +# project.
  9 +#
  10 +# This program is free software; you can redistribute it and/or
  11 +# modify it under the terms of the GNU General Public License as
  12 +# published by the Free Software Foundation; either version 2 of
  13 +# the License, or (at your option) any later version.
  14 +#
  15 +# This program is distributed in the hope that it will be useful,
  16 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18 +# GNU General Public License for more details.
  19 +#
  20 +# You should have received a copy of the GNU General Public License
  21 +# along with this program; if not, write to the Free Software
  22 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23 +# MA 02111-1307 USA
  24 +#
  25 +
  26 +include $(TOPDIR)/config.mk
  27 +
  28 +LIB = $(obj)libtegra-common.o
  29 +
  30 +COBJS-$(CONFIG_SPL_BUILD) += spl.o
  31 +
  32 +SRCS := $(COBJS-y:.o=.c)
  33 +OBJS := $(addprefix $(obj),$(COBJS-y))
  34 +
  35 +all: $(obj).depend $(LIB)
  36 +
  37 +$(LIB): $(OBJS)
  38 + $(call cmd_link_o_target, $(OBJS))
  39 +
  40 +#########################################################################
  41 +
  42 +# defines $(obj).depend target
  43 +include $(SRCTREE)/rules.mk
  44 +
  45 +sinclude $(obj).depend
  46 +
  47 +#########################################################################
arch/arm/cpu/arm720t/tegra-common/board.h
Diff comments   View file @ 3064f32
  1 +/*
  2 + * (C) Copyright 2010-2011
  3 + * NVIDIA Corporation <www.nvidia.com>
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +void board_init_uart_f(void);
  25 +void gpio_config_uart(void);
arch/arm/cpu/arm720t/tegra-common/cpu.h
Diff comments   View file @ 3064f32
  1 +/*
  2 + * (C) Copyright 2010-2011
  3 + * NVIDIA Corporation <www.nvidia.com>
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +#include <asm/types.h>
  24 +
  25 +/* Stabilization delays, in usec */
  26 +#define PLL_STABILIZATION_DELAY (300)
  27 +#define IO_STABILIZATION_DELAY (1000)
  28 +
  29 +#define NVBL_PLLP_KHZ (216000)
  30 +
  31 +#define PLLX_ENABLED (1 << 30)
  32 +#define CCLK_BURST_POLICY 0x20008888
  33 +#define SUPER_CCLK_DIVIDER 0x80000000
  34 +
  35 +/* Calculate clock fractional divider value from ref and target frequencies */
  36 +#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
  37 +
  38 +/* Calculate clock frequency value from reference and clock divider value */
  39 +#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
  40 +
  41 +/* AVP/CPU ID */
  42 +#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
  43 +#define PG_UP_TAG_0 0x0
  44 +
  45 +#define CORESIGHT_UNLOCK 0xC5ACCE55;
  46 +
  47 +/* AP20-Specific Base Addresses */
  48 +
  49 +/* AP20 Base physical address of SDRAM. */
  50 +#define AP20_BASE_PA_SDRAM 0x00000000
  51 +/* AP20 Base physical address of internal SRAM. */
  52 +#define AP20_BASE_PA_SRAM 0x40000000
  53 +/* AP20 Size of internal SRAM (256KB). */
  54 +#define AP20_BASE_PA_SRAM_SIZE 0x00040000
  55 +/* AP20 Base physical address of flash. */
  56 +#define AP20_BASE_PA_NOR_FLASH 0xD0000000
  57 +/* AP20 Base physical address of boot information table. */
  58 +#define AP20_BASE_PA_BOOT_INFO AP20_BASE_PA_SRAM
  59 +
  60 +/*
  61 + * Super-temporary stacks for EXTREMELY early startup. The values chosen for
  62 + * these addresses must be valid on ALL SOCs because this value is used before
  63 + * we are able to differentiate between the SOC types.
  64 + *
  65 + * NOTE: The since CPU's stack will eventually be moved from IRAM to SDRAM, its
  66 + * stack is placed below the AVP stack. Once the CPU stack has been moved,
  67 + * the AVP is free to use the IRAM the CPU stack previously occupied if
  68 + * it should need to do so.
  69 + *
  70 + * NOTE: In multi-processor CPU complex configurations, each processor will have
  71 + * its own stack of size CPU_EARLY_BOOT_STACK_SIZE. CPU 0 will have a
  72 + * limit of CPU_EARLY_BOOT_STACK_LIMIT. Each successive CPU will have a
  73 + * stack limit that is CPU_EARLY_BOOT_STACK_SIZE less then the previous
  74 + * CPU.
  75 + */
  76 +
  77 +/* Common AVP early boot stack limit */
  78 +#define AVP_EARLY_BOOT_STACK_LIMIT \
  79 + (AP20_BASE_PA_SRAM + (AP20_BASE_PA_SRAM_SIZE/2))
  80 +/* Common AVP early boot stack size */
  81 +#define AVP_EARLY_BOOT_STACK_SIZE 0x1000
  82 +/* Common CPU early boot stack limit */
  83 +#define CPU_EARLY_BOOT_STACK_LIMIT \
  84 + (AVP_EARLY_BOOT_STACK_LIMIT - AVP_EARLY_BOOT_STACK_SIZE)
  85 +/* Common CPU early boot stack size */
  86 +#define CPU_EARLY_BOOT_STACK_SIZE 0x1000
  87 +
  88 +#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
  89 +#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
  90 +#define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0)
  91 +
  92 +#define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4)
  93 +#define FLOW_MODE_STOP 2
  94 +#define HALT_COP_EVENT_JTAG (1 << 28)
  95 +#define HALT_COP_EVENT_IRQ_1 (1 << 11)
  96 +#define HALT_COP_EVENT_FIQ_1 (1 << 9)
  97 +
  98 +void start_cpu(u32 reset_vector);
  99 +int ap20_cpu_is_cortexa9(void);
  100 +void halt_avp(void) __attribute__ ((noreturn));
arch/arm/cpu/arm720t/tegra-common/spl.c
Diff comments   View file @ 3064f32
  1 +/*
  2 + * (C) Copyright 2012
  3 + * NVIDIA Inc, <www.nvidia.com>
  4 + *
  5 + * Allen Martin <amartin@nvidia.com>
  6 + *
  7 + * See file CREDITS for list of people who contributed to this
  8 + * project.
  9 + *
  10 + * This program is free software; you can redistribute it and/or
  11 + * modify it under the terms of the GNU General Public License as
  12 + * published by the Free Software Foundation; either version 2 of
  13 + * the License, or (at your option) any later version.
  14 + *
  15 + * This program is distributed in the hope that it will be useful,
  16 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18 + * GNU General Public License for more details.
  19 + *
  20 + * You should have received a copy of the GNU General Public License
  21 + * along with this program; if not, write to the Free Software
  22 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23 + * MA 02111-1307 USA
  24 + */
  25 +#include <common.h>
  26 +#include <asm/u-boot.h>
  27 +#include <asm/utils.h>
  28 +#include <asm/arch/sys_proto.h>
  29 +#include <asm/arch/clock.h>
  30 +#include <nand.h>
  31 +#include <mmc.h>
  32 +#include <fat.h>
  33 +#include <version.h>
  34 +#include <i2c.h>
  35 +#include <image.h>
  36 +#include <malloc.h>
  37 +#include <linux/compiler.h>
  38 +#include "board.h"
  39 +#include "cpu.h"
  40 +
  41 +#include <asm/io.h>
  42 +#include <asm/arch/tegra20.h>
  43 +#include <asm/arch/clk_rst.h>
  44 +#include <asm/arch/clock.h>
  45 +#include <asm/arch/pmc.h>
  46 +#include <asm/arch/pinmux.h>
  47 +#include <asm/arch/scu.h>
  48 +#include <common.h>
  49 +
  50 +DECLARE_GLOBAL_DATA_PTR;
  51 +
  52 +/* Define global data structure pointer to it*/
  53 +static gd_t gdata __attribute__ ((section(".data")));
  54 +static bd_t bdata __attribute__ ((section(".data")));
  55 +
  56 +inline void hang(void)
  57 +{
  58 + puts("### ERROR ### Please RESET the board ###\n");
  59 + for (;;)
  60 + ;
  61 +}
  62 +
  63 +void board_init_f(ulong dummy)
  64 +{
  65 + board_init_uart_f();
  66 +
  67 + /* Initialize periph GPIOs */
  68 +#ifdef CONFIG_SPI_UART_SWITCH
  69 + gpio_early_init_uart();
  70 +#else
  71 + gpio_config_uart();
  72 +#endif
  73 +
  74 + /*
  75 + * We call relocate_code() with relocation target same as the
  76 + * CONFIG_SYS_SPL_TEXT_BASE. This will result in relocation getting
  77 + * skipped. Instead, only .bss initialization will happen. That's
  78 + * all we need
  79 + */
  80 + debug(">>board_init_f()\n");
  81 + relocate_code(CONFIG_SPL_STACK, &gdata, CONFIG_SPL_TEXT_BASE);
  82 +}
  83 +
  84 +/* This requires UART clocks to be enabled */
  85 +static void preloader_console_init(void)
  86 +{
  87 + const char *u_boot_rev = U_BOOT_VERSION;
  88 +
  89 + gd = &gdata;
  90 + gd->bd = &bdata;
  91 + gd->flags |= GD_FLG_RELOC;
  92 + gd->baudrate = CONFIG_BAUDRATE;
  93 +
  94 + serial_init(); /* serial communications setup */
  95 +
  96 + gd->have_console = 1;
  97 +
  98 + /* Avoid a second "U-Boot" coming from this string */
  99 + u_boot_rev = &u_boot_rev[7];
  100 +
  101 + printf("\nU-Boot SPL %s (%s - %s)\n", u_boot_rev, U_BOOT_DATE,
  102 + U_BOOT_TIME);
  103 +}
  104 +
  105 +void board_init_r(gd_t *id, ulong dummy)
  106 +{
  107 + struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
  108 +
  109 + /* enable JTAG */
  110 + writel(0xC0, &pmt->pmt_cfg_ctl);
  111 +
  112 + debug(">>spl:board_init_r()\n");
  113 +
  114 + mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,
  115 + CONFIG_SYS_SPL_MALLOC_SIZE);
  116 +
  117 +#ifdef CONFIG_SPL_BOARD_INIT
  118 + spl_board_init();
  119 +#endif
  120 +
  121 + clock_early_init();
  122 + serial_init();
  123 + preloader_console_init();
  124 +
  125 + start_cpu((u32)CONFIG_SYS_TEXT_BASE);
  126 + halt_avp();
  127 + /* not reached */
  128 +}
  129 +
  130 +int board_usb_init(const void *blob)
  131 +{
  132 + return 0;
  133 +}
arch/arm/cpu/arm720t/tegra20/Makefile
Diff comments   View file @ 3064f32
... ... @@ -28,7 +28,6 @@
28 28 LIB = $(obj)lib$(SOC).o
29 29  
30 30 COBJS-y += cpu.o
31   -COBJS-$(CONFIG_SPL_BUILD) += spl.o
32 31  
33 32 SRCS := $(COBJS-y:.o=.c)
34 33 OBJS := $(addprefix $(obj),$(COBJS-y))
arch/arm/cpu/arm720t/tegra20/board.h
View file @ 3064f32
1   -/*
2   - * (C) Copyright 2010-2011
3   - * NVIDIA Corporation <www.nvidia.com>
4   - *
5   - * See file CREDITS for list of people who contributed to this
6   - * project.
7   - *
8   - * This program is free software; you can redistribute it and/or
9   - * modify it under the terms of the GNU General Public License as
10   - * published by the Free Software Foundation; either version 2 of
11   - * the License, or (at your option) any later version.
12   - *
13   - * This program is distributed in the hope that it will be useful,
14   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
15   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   - * GNU General Public License for more details.
17   - *
18   - * You should have received a copy of the GNU General Public License
19   - * along with this program; if not, write to the Free Software
20   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   - * MA 02111-1307 USA
22   - */
23   -
24   -void board_init_uart_f(void);
25   -void gpio_config_uart(void);
arch/arm/cpu/arm720t/tegra20/cpu.c
Diff comments   View file @ 3064f32
... ... @@ -29,7 +29,7 @@
29 29 #include <asm/arch/pinmux.h>
30 30 #include <asm/arch/scu.h>
31 31 #include <common.h>
32   -#include "cpu.h"
  32 +#include "../tegra-common/cpu.h"
33 33  
34 34 /* Returns 1 if the current CPU executing is a Cortex-A9, else 0 */
35 35 int ap20_cpu_is_cortexa9(void)
arch/arm/cpu/arm720t/tegra20/cpu.h
View file @ 3064f32
1   -/*
2   - * (C) Copyright 2010-2011
3   - * NVIDIA Corporation <www.nvidia.com>
4   - *
5   - * See file CREDITS for list of people who contributed to this
6   - * project.
7   - *
8   - * This program is free software; you can redistribute it and/or
9   - * modify it under the terms of the GNU General Public License as
10   - * published by the Free Software Foundation; either version 2 of
11   - * the License, or (at your option) any later version.
12   - *
13   - * This program is distributed in the hope that it will be useful,
14   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
15   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   - * GNU General Public License for more details.
17   - *
18   - * You should have received a copy of the GNU General Public License
19   - * along with this program; if not, write to the Free Software
20   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   - * MA 02111-1307 USA
22   - */
23   -#include <asm/types.h>
24   -
25   -/* Stabilization delays, in usec */
26   -#define PLL_STABILIZATION_DELAY (300)
27   -#define IO_STABILIZATION_DELAY (1000)
28   -
29   -#define NVBL_PLLP_KHZ (216000)
30   -
31   -#define PLLX_ENABLED (1 << 30)
32   -#define CCLK_BURST_POLICY 0x20008888
33   -#define SUPER_CCLK_DIVIDER 0x80000000
34   -
35   -/* Calculate clock fractional divider value from ref and target frequencies */
36   -#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
37   -
38   -/* Calculate clock frequency value from reference and clock divider value */
39   -#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
40   -
41   -/* AVP/CPU ID */
42   -#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
43   -#define PG_UP_TAG_0 0x0
44   -
45   -#define CORESIGHT_UNLOCK 0xC5ACCE55;
46   -
47   -/* AP20-Specific Base Addresses */
48   -
49   -/* AP20 Base physical address of SDRAM. */
50   -#define AP20_BASE_PA_SDRAM 0x00000000
51   -/* AP20 Base physical address of internal SRAM. */
52   -#define AP20_BASE_PA_SRAM 0x40000000
53   -/* AP20 Size of internal SRAM (256KB). */
54   -#define AP20_BASE_PA_SRAM_SIZE 0x00040000
55   -/* AP20 Base physical address of flash. */
56   -#define AP20_BASE_PA_NOR_FLASH 0xD0000000
57   -/* AP20 Base physical address of boot information table. */
58   -#define AP20_BASE_PA_BOOT_INFO AP20_BASE_PA_SRAM
59   -
60   -/*
61   - * Super-temporary stacks for EXTREMELY early startup. The values chosen for
62   - * these addresses must be valid on ALL SOCs because this value is used before
63   - * we are able to differentiate between the SOC types.
64   - *
65   - * NOTE: The since CPU's stack will eventually be moved from IRAM to SDRAM, its
66   - * stack is placed below the AVP stack. Once the CPU stack has been moved,
67   - * the AVP is free to use the IRAM the CPU stack previously occupied if
68   - * it should need to do so.
69   - *
70   - * NOTE: In multi-processor CPU complex configurations, each processor will have
71   - * its own stack of size CPU_EARLY_BOOT_STACK_SIZE. CPU 0 will have a
72   - * limit of CPU_EARLY_BOOT_STACK_LIMIT. Each successive CPU will have a
73   - * stack limit that is CPU_EARLY_BOOT_STACK_SIZE less then the previous
74   - * CPU.
75   - */
76   -
77   -/* Common AVP early boot stack limit */
78   -#define AVP_EARLY_BOOT_STACK_LIMIT \
79   - (AP20_BASE_PA_SRAM + (AP20_BASE_PA_SRAM_SIZE/2))
80   -/* Common AVP early boot stack size */
81   -#define AVP_EARLY_BOOT_STACK_SIZE 0x1000
82   -/* Common CPU early boot stack limit */
83   -#define CPU_EARLY_BOOT_STACK_LIMIT \
84   - (AVP_EARLY_BOOT_STACK_LIMIT - AVP_EARLY_BOOT_STACK_SIZE)
85   -/* Common CPU early boot stack size */
86   -#define CPU_EARLY_BOOT_STACK_SIZE 0x1000
87   -
88   -#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
89   -#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
90   -#define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0)
91   -
92   -#define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4)
93   -#define FLOW_MODE_STOP 2
94   -#define HALT_COP_EVENT_JTAG (1 << 28)
95   -#define HALT_COP_EVENT_IRQ_1 (1 << 11)
96   -#define HALT_COP_EVENT_FIQ_1 (1 << 9)
97   -
98   -void start_cpu(u32 reset_vector);
99   -int ap20_cpu_is_cortexa9(void);
100   -void halt_avp(void) __attribute__ ((noreturn));
arch/arm/cpu/arm720t/tegra20/spl.c
View file @ 3064f32
1   -/*
2   - * (C) Copyright 2012
3   - * NVIDIA Inc, <www.nvidia.com>
4   - *
5   - * Allen Martin <amartin@nvidia.com>
6   - *
7   - * See file CREDITS for list of people who contributed to this
8   - * project.
9   - *
10   - * This program is free software; you can redistribute it and/or
11   - * modify it under the terms of the GNU General Public License as
12   - * published by the Free Software Foundation; either version 2 of
13   - * the License, or (at your option) any later version.
14   - *
15   - * This program is distributed in the hope that it will be useful,
16   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
17   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18   - * GNU General Public License for more details.
19   - *
20   - * You should have received a copy of the GNU General Public License
21   - * along with this program; if not, write to the Free Software
22   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23   - * MA 02111-1307 USA
24   - */
25   -#include <common.h>
26   -#include <asm/u-boot.h>
27   -#include <asm/utils.h>
28   -#include <asm/arch/sys_proto.h>
29   -#include <asm/arch/clock.h>
30   -#include <nand.h>
31   -#include <mmc.h>
32   -#include <fat.h>
33   -#include <version.h>
34   -#include <i2c.h>
35   -#include <image.h>
36   -#include <malloc.h>
37   -#include <linux/compiler.h>
38   -#include "board.h"
39   -#include "cpu.h"
40   -
41   -#include <asm/io.h>
42   -#include <asm/arch/tegra20.h>
43   -#include <asm/arch/clk_rst.h>
44   -#include <asm/arch/clock.h>
45   -#include <asm/arch/pmc.h>
46   -#include <asm/arch/pinmux.h>
47   -#include <asm/arch/scu.h>
48   -#include <common.h>
49   -
50   -DECLARE_GLOBAL_DATA_PTR;
51   -
52   -/* Define global data structure pointer to it*/
53   -static gd_t gdata __attribute__ ((section(".data")));
54   -static bd_t bdata __attribute__ ((section(".data")));
55   -
56   -inline void hang(void)
57   -{
58   - puts("### ERROR ### Please RESET the board ###\n");
59   - for (;;)
60   - ;
61   -}
62   -
63   -void board_init_f(ulong dummy)
64   -{
65   - board_init_uart_f();
66   -
67   - /* Initialize periph GPIOs */
68   -#ifdef CONFIG_SPI_UART_SWITCH
69   - gpio_early_init_uart();
70   -#else
71   - gpio_config_uart();
72   -#endif
73   -
74   - /*
75   - * We call relocate_code() with relocation target same as the
76   - * CONFIG_SYS_SPL_TEXT_BASE. This will result in relocation getting
77   - * skipped. Instead, only .bss initialization will happen. That's
78   - * all we need
79   - */
80   - debug(">>board_init_f()\n");
81   - relocate_code(CONFIG_SPL_STACK, &gdata, CONFIG_SPL_TEXT_BASE);
82   -}
83   -
84   -/* This requires UART clocks to be enabled */
85   -static void preloader_console_init(void)
86   -{
87   - const char *u_boot_rev = U_BOOT_VERSION;
88   -
89   - gd = &gdata;
90   - gd->bd = &bdata;
91   - gd->flags |= GD_FLG_RELOC;
92   - gd->baudrate = CONFIG_BAUDRATE;
93   -
94   - serial_init(); /* serial communications setup */
95   -
96   - gd->have_console = 1;
97   -
98   - /* Avoid a second "U-Boot" coming from this string */
99   - u_boot_rev = &u_boot_rev[7];
100   -
101   - printf("\nU-Boot SPL %s (%s - %s)\n", u_boot_rev, U_BOOT_DATE,
102   - U_BOOT_TIME);
103   -}
104   -
105   -void board_init_r(gd_t *id, ulong dummy)
106   -{
107   - struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
108   -
109   - /* enable JTAG */
110   - writel(0xC0, &pmt->pmt_cfg_ctl);
111   -
112   - debug(">>spl:board_init_r()\n");
113   -
114   - mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,
115   - CONFIG_SYS_SPL_MALLOC_SIZE);
116   -
117   -#ifdef CONFIG_SPL_BOARD_INIT
118   - spl_board_init();
119   -#endif
120   -
121   - clock_early_init();
122   - serial_init();
123   - preloader_console_init();
124   -
125   - start_cpu((u32)CONFIG_SYS_TEXT_BASE);
126   - halt_avp();
127   - /* not reached */
128   -}
129   -
130   -int board_usb_init(const void *blob)
131   -{
132   - return 0;
133   -}
arch/arm/cpu/armv7/tegra-common/Makefile
Diff comments   View file @ 3064f32
  1 +#
  2 +# (C) Copyright 2010,2011 Nvidia Corporation.
  3 +#
  4 +# (C) Copyright 2000-2003
  5 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  6 +#
  7 +# See file CREDITS for list of people who contributed to this
  8 +# project.
  9 +#
  10 +# This program is free software; you can redistribute it and/or
  11 +# modify it under the terms of the GNU General Public License as
  12 +# published by the Free Software Foundation; either version 2 of
  13 +# the License, or (at your option) any later version.
  14 +#
  15 +# This program is distributed in the hope that it will be useful,
  16 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18 +# GNU General Public License for more details.
  19 +#
  20 +# You should have received a copy of the GNU General Public License
  21 +# along with this program; if not, write to the Free Software
  22 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23 +# MA 02111-1307 USA
  24 +#
  25 +
  26 +include $(TOPDIR)/config.mk
  27 +
  28 +LIB = $(obj)libtegra-common.o
  29 +
  30 +COBJS-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o
  31 +
  32 +COBJS := $(COBJS-y)
  33 +SRCS := $(COBJS:.o=.c)
  34 +OBJS := $(addprefix $(obj),$(COBJS))
  35 +
  36 +all: $(obj).depend $(LIB)
  37 +
  38 +$(LIB): $(OBJS)
  39 + $(call cmd_link_o_target, $(OBJS))
  40 +
  41 +#########################################################################
  42 +
  43 +# defines $(obj).depend target
  44 +include $(SRCTREE)/rules.mk
  45 +
  46 +sinclude $(obj).depend
  47 +
  48 +#########################################################################
arch/arm/cpu/armv7/tegra-common/cmd_enterrcm.c
Diff comments   View file @ 3064f32
  1 +/*
  2 + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
  3 + *
  4 + * Derived from code (arch/arm/lib/reset.c) that is:
  5 + *
  6 + * (C) Copyright 2002
  7 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  8 + * Marius Groeger <mgroeger@sysgo.de>
  9 + *
  10 + * (C) Copyright 2002
  11 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  12 + * Alex Zuepke <azu@sysgo.de>
  13 + *
  14 + * (C) Copyright 2002
  15 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
  16 + *
  17 + * (C) Copyright 2004
  18 + * DAVE Srl
  19 + * http://www.dave-tech.it
  20 + * http://www.wawnet.biz
  21 + * mailto:info@wawnet.biz
  22 + *
  23 + * (C) Copyright 2004 Texas Insturments
  24 + *
  25 + * See file CREDITS for list of people who contributed to this
  26 + * project.
  27 + *
  28 + * This program is free software; you can redistribute it and/or
  29 + * modify it under the terms of the GNU General Public License as
  30 + * published by the Free Software Foundation; either version 2 of
  31 + * the License, or (at your option) any later version.
  32 + *
  33 + * This program is distributed in the hope that it will be useful,
  34 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  35 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  36 + * GNU General Public License for more details.
  37 + *
  38 + * You should have received a copy of the GNU General Public License
  39 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
  40 + */
  41 +
  42 +#include <common.h>
  43 +#include <asm/arch/tegra20.h>
  44 +#include <asm/arch/pmc.h>
  45 +
  46 +static int do_enterrcm(cmd_tbl_t *cmdtp, int flag, int argc,
  47 + char * const argv[])
  48 +{
  49 + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
  50 +
  51 + puts("Entering RCM...\n");
  52 + udelay(50000);
  53 +
  54 + pmc->pmc_scratch0 = 2;
  55 + disable_interrupts();
  56 + reset_cpu(0);
  57 +
  58 + return 0;
  59 +}
  60 +
  61 +U_BOOT_CMD(
  62 + enterrcm, 1, 0, do_enterrcm,
  63 + "reset Tegra and enter USB Recovery Mode",
  64 + ""
  65 +);
arch/arm/cpu/armv7/tegra20/Makefile
Diff comments   View file @ 3064f32
... ... @@ -28,7 +28,6 @@
28 28 LIB = $(obj)lib$(SOC).o
29 29  
30 30 COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o
31   -COBJS-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o
32 31  
33 32 COBJS := $(COBJS-y)
34 33 SRCS := $(COBJS:.o=.c)
arch/arm/cpu/armv7/tegra20/cmd_enterrcm.c
View file @ 3064f32
1   -/*
2   - * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3   - *
4   - * Derived from code (arch/arm/lib/reset.c) that is:
5   - *
6   - * (C) Copyright 2002
7   - * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8   - * Marius Groeger <mgroeger@sysgo.de>
9   - *
10   - * (C) Copyright 2002
11   - * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
12   - * Alex Zuepke <azu@sysgo.de>
13   - *
14   - * (C) Copyright 2002
15   - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
16   - *
17   - * (C) Copyright 2004
18   - * DAVE Srl
19   - * http://www.dave-tech.it
20   - * http://www.wawnet.biz
21   - * mailto:info@wawnet.biz
22   - *
23   - * (C) Copyright 2004 Texas Insturments
24   - *
25   - * See file CREDITS for list of people who contributed to this
26   - * project.
27   - *
28   - * This program is free software; you can redistribute it and/or
29   - * modify it under the terms of the GNU General Public License as
30   - * published by the Free Software Foundation; either version 2 of
31   - * the License, or (at your option) any later version.
32   - *
33   - * This program is distributed in the hope that it will be useful,
34   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
35   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
36   - * GNU General Public License for more details.
37   - *
38   - * You should have received a copy of the GNU General Public License
39   - * along with this program. If not, see <http://www.gnu.org/licenses/>.
40   - */
41   -
42   -#include <common.h>
43   -#include <asm/arch/tegra20.h>
44   -#include <asm/arch/pmc.h>
45   -
46   -static int do_enterrcm(cmd_tbl_t *cmdtp, int flag, int argc,
47   - char * const argv[])
48   -{
49   - struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
50   -
51   - puts("Entering RCM...\n");
52   - udelay(50000);
53   -
54   - pmc->pmc_scratch0 = 2;
55   - disable_interrupts();
56   - reset_cpu(0);
57   -
58   - return 0;
59   -}
60   -
61   -U_BOOT_CMD(
62   - enterrcm, 1, 0, do_enterrcm,
63   - "reset Tegra and enter USB Recovery Mode",
64   - ""
65   -);
arch/arm/cpu/tegra-common/Makefile
Diff comments   View file @ 3064f32
  1 +#
  2 +# (C) Copyright 2010,2011 Nvidia Corporation.
  3 +#
  4 +# (C) Copyright 2000-2008
  5 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  6 +#
  7 +# See file CREDITS for list of people who contributed to this
  8 +# project.
  9 +#
  10 +# This program is free software; you can redistribute it and/or
  11 +# modify it under the terms of the GNU General Public License as
  12 +# published by the Free Software Foundation; either version 2 of
  13 +# the License, or (at your option) any later version.
  14 +#
  15 +# This program is distributed in the hope that it will be useful,
  16 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18 +# GNU General Public License for more details.
  19 +#
  20 +# You should have received a copy of the GNU General Public License
  21 +# along with this program; if not, write to the Free Software
  22 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23 +# MA 02111-1307 USA
  24 +#
  25 +
  26 +include $(TOPDIR)/config.mk
  27 +
  28 +LIB = $(obj)libcputegra-common.o
  29 +
  30 +SOBJS += lowlevel_init.o
  31 +COBJS-y += ap.o board.o sys_info.o timer.o
  32 +
  33 +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
  34 +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
  35 +
  36 +all: $(obj).depend $(LIB)
  37 +
  38 +$(LIB): $(OBJS)
  39 + $(call cmd_link_o_target, $(OBJS))
  40 +
  41 +#########################################################################
  42 +
  43 +# defines $(obj).depend target
  44 +include $(SRCTREE)/rules.mk
  45 +
  46 +sinclude $(obj).depend
  47 +
  48 +#########################################################################
arch/arm/cpu/tegra-common/ap.c
Diff comments   View file @ 3064f32
  1 +/*
  2 +* (C) Copyright 2010-2011
  3 +* NVIDIA Corporation <www.nvidia.com>
  4 +*
  5 +* See file CREDITS for list of people who contributed to this
  6 +* project.
  7 +*
  8 +* This program is free software; you can redistribute it and/or
  9 +* modify it under the terms of the GNU General Public License as
  10 +* published by the Free Software Foundation; either version 2 of
  11 +* the License, or (at your option) any later version.
  12 +*
  13 +* This program is distributed in the hope that it will be useful,
  14 +* but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +* GNU General Public License for more details.
  17 +*
  18 +* You should have received a copy of the GNU General Public License
  19 +* along with this program; if not, write to the Free Software
  20 +* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +* MA 02111-1307 USA
  22 +*/
  23 +#include <asm/io.h>
  24 +#include <asm/arch/ap20.h>
  25 +#include <asm/arch/fuse.h>
  26 +#include <asm/arch/gp_padctrl.h>
  27 +#include <asm/arch/pmc.h>
  28 +#include <asm/arch/scu.h>
  29 +#include <asm/arch/warmboot.h>
  30 +#include <common.h>
  31 +
  32 +int tegra_get_chip_type(void)
  33 +{
  34 + struct apb_misc_gp_ctlr *gp;
  35 + struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
  36 + uint tegra_sku_id, rev;
  37 +
  38 + /*
  39 + * This is undocumented, Chip ID is bits 15:8 of the register
  40 + * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
  41 + * Tegra30
  42 + */
  43 + gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
  44 + rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
  45 +
  46 + tegra_sku_id = readl(&fuse->sku_info) & 0xff;
  47 +
  48 + switch (rev) {
  49 + case CHIPID_TEGRA20:
  50 + switch (tegra_sku_id) {
  51 + case SKU_ID_T20:
  52 + return TEGRA_SOC_T20;
  53 + case SKU_ID_T25SE:
  54 + case SKU_ID_AP25:
  55 + case SKU_ID_T25:
  56 + case SKU_ID_AP25E:
  57 + case SKU_ID_T25E:
  58 + return TEGRA_SOC_T25;
  59 + }
  60 + break;
  61 + }
  62 + /* unknown sku id */
  63 + return TEGRA_SOC_UNKNOWN;
  64 +}
  65 +
  66 +static void enable_scu(void)
  67 +{
  68 + struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
  69 + u32 reg;
  70 +
  71 + /* If SCU already setup/enabled, return */
  72 + if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE)
  73 + return;
  74 +
  75 + /* Invalidate all ways for all processors */
  76 + writel(0xFFFF, &scu->scu_inv_all);
  77 +
  78 + /* Enable SCU - bit 0 */
  79 + reg = readl(&scu->scu_ctrl);
  80 + reg |= SCU_CTRL_ENABLE;
  81 + writel(reg, &scu->scu_ctrl);
  82 +}
  83 +
  84 +static u32 get_odmdata(void)
  85 +{
  86 + /*
  87 + * ODMDATA is stored in the BCT in IRAM by the BootROM.
  88 + * The BCT start and size are stored in the BIT in IRAM.
  89 + * Read the data @ bct_start + (bct_size - 12). This works
  90 + * on T20 and T30 BCTs, which are locked down. If this changes
  91 + * in new chips (T114, etc.), we can revisit this algorithm.
  92 + */
  93 +
  94 + u32 bct_start, odmdata;
  95 +
  96 + bct_start = readl(AP20_BASE_PA_SRAM + NVBOOTINFOTABLE_BCTPTR);
  97 + odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
  98 +
  99 + return odmdata;
  100 +}
  101 +
  102 +static void init_pmc_scratch(void)
  103 +{
  104 + struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
  105 + u32 odmdata;
  106 + int i;
  107 +
  108 + /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
  109 + for (i = 0; i < 23; i++)
  110 + writel(0, &pmc->pmc_scratch1+i);
  111 +
  112 + /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
  113 + odmdata = get_odmdata();
  114 + writel(odmdata, &pmc->pmc_scratch20);
  115 +}
  116 +
  117 +void s_init(void)
  118 +{
  119 + /* Init PMC scratch memory */
  120 + init_pmc_scratch();
  121 +
  122 + enable_scu();
  123 +
  124 + /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
  125 + asm volatile(
  126 + "mrc p15, 0, r0, c1, c0, 1\n"
  127 + "orr r0, r0, #0x41\n"
  128 + "mcr p15, 0, r0, c1, c0, 1\n");
  129 +
  130 + /* FIXME: should have ap20's L2 disabled too? */
  131 +}
arch/arm/cpu/tegra-common/board.c
Diff comments   View file @ 3064f32
  1 +/*
  2 + * (C) Copyright 2010,2011
  3 + * NVIDIA Corporation <www.nvidia.com>
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#include <common.h>
  25 +#include <asm/io.h>
  26 +#include <asm/arch/clock.h>
  27 +#include <asm/arch/funcmux.h>
  28 +#include <asm/arch/pmc.h>
  29 +#include <asm/arch/sys_proto.h>
  30 +#include <asm/arch/tegra20.h>
  31 +#include <asm/arch/warmboot.h>
  32 +
  33 +DECLARE_GLOBAL_DATA_PTR;
  34 +
  35 +enum {
  36 + /* UARTs which we can enable */
  37 + UARTA = 1 << 0,
  38 + UARTB = 1 << 1,
  39 + UARTD = 1 << 3,
  40 + UART_COUNT = 4,
  41 +};
  42 +
  43 +/*
  44 + * Boot ROM initializes the odmdata in APBDEV_PMC_SCRATCH20_0,
  45 + * so we are using this value to identify memory size.
  46 + */
  47 +
  48 +unsigned int query_sdram_size(void)
  49 +{
  50 + struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
  51 + u32 reg;
  52 +
  53 + reg = readl(&pmc->pmc_scratch20);
  54 + debug("pmc->pmc_scratch20 (ODMData) = 0x%08x\n", reg);
  55 +
  56 + /* bits 31:28 in OdmData are used for RAM size */
  57 + switch ((reg) >> 28) {
  58 + case 1:
  59 + return 0x10000000; /* 256 MB */
  60 + case 2:
  61 + default:
  62 + return 0x20000000; /* 512 MB */
  63 + case 3:
  64 + return 0x40000000; /* 1GB */
  65 + }
  66 +}
  67 +
  68 +int dram_init(void)
  69 +{
  70 + /* We do not initialise DRAM here. We just query the size */
  71 + gd->ram_size = query_sdram_size();
  72 + return 0;
  73 +}
  74 +
  75 +#ifdef CONFIG_DISPLAY_BOARDINFO
  76 +int checkboard(void)
  77 +{
  78 + printf("Board: %s\n", sysinfo.board_string);
  79 + return 0;
  80 +}
  81 +#endif /* CONFIG_DISPLAY_BOARDINFO */
  82 +
  83 +static int uart_configs[] = {
  84 +#if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
  85 + FUNCMUX_UART1_UAA_UAB,
  86 +#elif defined(CONFIG_TEGRA_UARTA_GPU)
  87 + FUNCMUX_UART1_GPU,
  88 +#elif defined(CONFIG_TEGRA_UARTA_SDIO1)
  89 + FUNCMUX_UART1_SDIO1,
  90 +#else
  91 + FUNCMUX_UART1_IRRX_IRTX,
  92 +#endif
  93 + FUNCMUX_UART2_IRDA,
  94 + -1,
  95 + FUNCMUX_UART4_GMC,
  96 + -1,
  97 +};
  98 +
  99 +/**
  100 + * Set up the specified uarts
  101 + *
  102 + * @param uarts_ids Mask containing UARTs to init (UARTx)
  103 + */
  104 +static void setup_uarts(int uart_ids)
  105 +{
  106 + static enum periph_id id_for_uart[] = {
  107 + PERIPH_ID_UART1,
  108 + PERIPH_ID_UART2,
  109 + PERIPH_ID_UART3,
  110 + PERIPH_ID_UART4,
  111 + };
  112 + size_t i;
  113 +
  114 + for (i = 0; i < UART_COUNT; i++) {
  115 + if (uart_ids & (1 << i)) {
  116 + enum periph_id id = id_for_uart[i];
  117 +
  118 + funcmux_select(id, uart_configs[i]);
  119 + clock_ll_start_uart(id);
  120 + }
  121 + }
  122 +}
  123 +
  124 +void board_init_uart_f(void)
  125 +{
  126 + int uart_ids = 0; /* bit mask of which UART ids to enable */
  127 +
  128 +#ifdef CONFIG_TEGRA_ENABLE_UARTA
  129 + uart_ids |= UARTA;
  130 +#endif
  131 +#ifdef CONFIG_TEGRA_ENABLE_UARTB
  132 + uart_ids |= UARTB;
  133 +#endif
  134 +#ifdef CONFIG_TEGRA_ENABLE_UARTD
  135 + uart_ids |= UARTD;
  136 +#endif
  137 + setup_uarts(uart_ids);
  138 +}
  139 +
  140 +#ifndef CONFIG_SYS_DCACHE_OFF
  141 +void enable_caches(void)
  142 +{
  143 + /* Enable D-cache. I-cache is already enabled in start.S */
  144 + dcache_enable();
  145 +}
  146 +#endif
arch/arm/cpu/tegra-common/lowlevel_init.S
Diff comments   View file @ 3064f32
  1 +/*
  2 + * SoC-specific setup info
  3 + *
  4 + * (C) Copyright 2010,2011
  5 + * NVIDIA Corporation <www.nvidia.com>
  6 + *
  7 + * See file CREDITS for list of people who contributed to this
  8 + * project.
  9 + *
  10 + * This program is free software; you can redistribute it and/or
  11 + * modify it under the terms of the GNU General Public License as
  12 + * published by the Free Software Foundation; either version 2 of
  13 + * the License, or (at your option) any later version.
  14 + *
  15 + * This program is distributed in the hope that it will be useful,
  16 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18 + * GNU General Public License for more details.
  19 + *
  20 + * You should have received a copy of the GNU General Public License
  21 + * along with this program; if not, write to the Free Software
  22 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23 + * MA 02111-1307 USA
  24 + */
  25 +
  26 +#include <config.h>
  27 +#include <version.h>
  28 +#include <linux/linkage.h>
  29 +
  30 + .align 5
  31 +ENTRY(reset_cpu)
  32 + ldr r1, rstctl @ get addr for global reset
  33 + @ reg
  34 + ldr r3, [r1]
  35 + orr r3, r3, #0x10
  36 + str r3, [r1] @ force reset
  37 + mov r0, r0
  38 +_loop_forever:
  39 + b _loop_forever
  40 +rstctl:
  41 + .word PRM_RSTCTRL
  42 +ENDPROC(reset_cpu)
arch/arm/cpu/tegra-common/sys_info.c
Diff comments   View file @ 3064f32
  1 +/*
  2 + * (C) Copyright 2010,2011
  3 + * NVIDIA Corporation <www.nvidia.com>
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#include <common.h>
  25 +
  26 +#ifdef CONFIG_DISPLAY_CPUINFO
  27 +/* Print CPU information */
  28 +int print_cpuinfo(void)
  29 +{
  30 + puts("TEGRA20\n");
  31 +
  32 + /* TBD: Add printf of major/minor rev info, stepping, etc. */
  33 + return 0;
  34 +}
  35 +#endif /* CONFIG_DISPLAY_CPUINFO */
arch/arm/cpu/tegra-common/timer.c
Diff comments   View file @ 3064f32
  1 +/*
  2 + * (C) Copyright 2010,2011
  3 + * NVIDIA Corporation <www.nvidia.com>
  4 + *
  5 + * (C) Copyright 2008
  6 + * Texas Instruments
  7 + *
  8 + * Richard Woodruff <r-woodruff2@ti.com>
  9 + * Syed Moahmmed Khasim <khasim@ti.com>
  10 + *
  11 + * (C) Copyright 2002
  12 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  13 + * Marius Groeger <mgroeger@sysgo.de>
  14 + * Alex Zuepke <azu@sysgo.de>
  15 + *
  16 + * (C) Copyright 2002
  17 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
  18 + *
  19 + * See file CREDITS for list of people who contributed to this
  20 + * project.
  21 + *
  22 + * This program is free software; you can redistribute it and/or
  23 + * modify it under the terms of the GNU General Public License as
  24 + * published by the Free Software Foundation; either version 2 of
  25 + * the License, or (at your option) any later version.
  26 + *
  27 + * This program is distributed in the hope that it will be useful,
  28 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  29 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  30 + * GNU General Public License for more details.
  31 + *
  32 + * You should have received a copy of the GNU General Public License
  33 + * along with this program; if not, write to the Free Software
  34 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  35 + * MA 02111-1307 USA
  36 + */
  37 +
  38 +#include <common.h>
  39 +#include <asm/io.h>
  40 +#include <asm/arch/tegra20.h>
  41 +#include <asm/arch/timer.h>
  42 +
  43 +DECLARE_GLOBAL_DATA_PTR;
  44 +
  45 +/* counter runs at 1MHz */
  46 +#define TIMER_CLK 1000000
  47 +#define TIMER_LOAD_VAL 0xffffffff
  48 +
  49 +/* timer without interrupts */
  50 +ulong get_timer(ulong base)
  51 +{
  52 + return get_timer_masked() - base;
  53 +}
  54 +
  55 +/* delay x useconds */
  56 +void __udelay(unsigned long usec)
  57 +{
  58 + long tmo = usec * (TIMER_CLK / 1000) / 1000;
  59 + unsigned long now, last = timer_get_us();
  60 +
  61 + while (tmo > 0) {
  62 + now = timer_get_us();
  63 + if (last > now) /* count up timer overflow */
  64 + tmo -= TIMER_LOAD_VAL - last + now;
  65 + else
  66 + tmo -= now - last;
  67 + last = now;
  68 + }
  69 +}
  70 +
  71 +ulong get_timer_masked(void)
  72 +{
  73 + ulong now;
  74 +
  75 + /* current tick value */
  76 + now = timer_get_us() / (TIMER_CLK / CONFIG_SYS_HZ);
  77 +
  78 + if (now >= gd->lastinc) /* normal mode (non roll) */
  79 + /* move stamp forward with absolute diff ticks */
  80 + gd->tbl += (now - gd->lastinc);
  81 + else /* we have rollover of incrementer */
  82 + gd->tbl += ((TIMER_LOAD_VAL / (TIMER_CLK / CONFIG_SYS_HZ))
  83 + - gd->lastinc) + now;
  84 + gd->lastinc = now;
  85 + return gd->tbl;
  86 +}
  87 +
  88 +/*
  89 + * This function is derived from PowerPC code (read timebase as long long).
  90 + * On ARM it just returns the timer value.
  91 + */
  92 +unsigned long long get_ticks(void)
  93 +{
  94 + return get_timer(0);
  95 +}
  96 +
  97 +/*
  98 + * This function is derived from PowerPC code (timebase clock frequency).
  99 + * On ARM it returns the number of timer ticks per second.
  100 + */
  101 +ulong get_tbclk(void)
  102 +{
  103 + return CONFIG_SYS_HZ;
  104 +}
  105 +
  106 +unsigned long timer_get_us(void)
  107 +{
  108 + struct timerus *timer_base = (struct timerus *)NV_PA_TMRUS_BASE;
  109 +
  110 + return readl(&timer_base->cntr_1us);
  111 +}
arch/arm/cpu/tegra20-common/Makefile
Diff comments   View file @ 3064f32
... ... @@ -31,8 +31,7 @@
31 31  
32 32 LIB = $(obj)lib$(SOC)-common.o
33 33  
34   -SOBJS += lowlevel_init.o
35   -COBJS-y += ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o
  34 +COBJS-y += clock.o funcmux.o pinmux.o
36 35 COBJS-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o
37 36 COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
38 37 COBJS-$(CONFIG_TEGRA_PMU) += pmu.o
arch/arm/cpu/tegra20-common/ap20.c
View file @ 3064f32
1   -/*
2   -* (C) Copyright 2010-2011
3   -* NVIDIA Corporation <www.nvidia.com>
4   -*
5   -* See file CREDITS for list of people who contributed to this
6   -* project.
7   -*
8   -* This program is free software; you can redistribute it and/or
9   -* modify it under the terms of the GNU General Public License as
10   -* published by the Free Software Foundation; either version 2 of
11   -* the License, or (at your option) any later version.
12   -*
13   -* This program is distributed in the hope that it will be useful,
14   -* but WITHOUT ANY WARRANTY; without even the implied warranty of
15   -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   -* GNU General Public License for more details.
17   -*
18   -* You should have received a copy of the GNU General Public License
19   -* along with this program; if not, write to the Free Software
20   -* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   -* MA 02111-1307 USA
22   -*/
23   -#include <asm/io.h>
24   -#include <asm/arch/ap20.h>
25   -#include <asm/arch/fuse.h>
26   -#include <asm/arch/gp_padctrl.h>
27   -#include <asm/arch/pmc.h>
28   -#include <asm/arch/scu.h>
29   -#include <asm/arch/warmboot.h>
30   -#include <common.h>
31   -
32   -int tegra_get_chip_type(void)
33   -{
34   - struct apb_misc_gp_ctlr *gp;
35   - struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
36   - uint tegra_sku_id, rev;
37   -
38   - /*
39   - * This is undocumented, Chip ID is bits 15:8 of the register
40   - * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
41   - * Tegra30
42   - */
43   - gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
44   - rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
45   -
46   - tegra_sku_id = readl(&fuse->sku_info) & 0xff;
47   -
48   - switch (rev) {
49   - case CHIPID_TEGRA20:
50   - switch (tegra_sku_id) {
51   - case SKU_ID_T20:
52   - return TEGRA_SOC_T20;
53   - case SKU_ID_T25SE:
54   - case SKU_ID_AP25:
55   - case SKU_ID_T25:
56   - case SKU_ID_AP25E:
57   - case SKU_ID_T25E:
58   - return TEGRA_SOC_T25;
59   - }
60   - break;
61   - }
62   - /* unknown sku id */
63   - return TEGRA_SOC_UNKNOWN;
64   -}
65   -
66   -static void enable_scu(void)
67   -{
68   - struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
69   - u32 reg;
70   -
71   - /* If SCU already setup/enabled, return */
72   - if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE)
73   - return;
74   -
75   - /* Invalidate all ways for all processors */
76   - writel(0xFFFF, &scu->scu_inv_all);
77   -
78   - /* Enable SCU - bit 0 */
79   - reg = readl(&scu->scu_ctrl);
80   - reg |= SCU_CTRL_ENABLE;
81   - writel(reg, &scu->scu_ctrl);
82   -}
83   -
84   -static u32 get_odmdata(void)
85   -{
86   - /*
87   - * ODMDATA is stored in the BCT in IRAM by the BootROM.
88   - * The BCT start and size are stored in the BIT in IRAM.
89   - * Read the data @ bct_start + (bct_size - 12). This works
90   - * on T20 and T30 BCTs, which are locked down. If this changes
91   - * in new chips (T114, etc.), we can revisit this algorithm.
92   - */
93   -
94   - u32 bct_start, odmdata;
95   -
96   - bct_start = readl(AP20_BASE_PA_SRAM + NVBOOTINFOTABLE_BCTPTR);
97   - odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
98   -
99   - return odmdata;
100   -}
101   -
102   -static void init_pmc_scratch(void)
103   -{
104   - struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
105   - u32 odmdata;
106   - int i;
107   -
108   - /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
109   - for (i = 0; i < 23; i++)
110   - writel(0, &pmc->pmc_scratch1+i);
111   -
112   - /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
113   - odmdata = get_odmdata();
114   - writel(odmdata, &pmc->pmc_scratch20);
115   -}
116   -
117   -void s_init(void)
118   -{
119   - /* Init PMC scratch memory */
120   - init_pmc_scratch();
121   -
122   - enable_scu();
123   -
124   - /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
125   - asm volatile(
126   - "mrc p15, 0, r0, c1, c0, 1\n"
127   - "orr r0, r0, #0x41\n"
128   - "mcr p15, 0, r0, c1, c0, 1\n");
129   -
130   - /* FIXME: should have ap20's L2 disabled too? */
131   -}
arch/arm/cpu/tegra20-common/board.c
View file @ 3064f32
1   -/*
2   - * (C) Copyright 2010,2011
3   - * NVIDIA Corporation <www.nvidia.com>
4   - *
5   - * See file CREDITS for list of people who contributed to this
6   - * project.
7   - *
8   - * This program is free software; you can redistribute it and/or
9   - * modify it under the terms of the GNU General Public License as
10   - * published by the Free Software Foundation; either version 2 of
11   - * the License, or (at your option) any later version.
12   - *
13   - * This program is distributed in the hope that it will be useful,
14   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
15   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   - * GNU General Public License for more details.
17   - *
18   - * You should have received a copy of the GNU General Public License
19   - * along with this program; if not, write to the Free Software
20   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   - * MA 02111-1307 USA
22   - */
23   -
24   -#include <common.h>
25   -#include <asm/io.h>
26   -#include <asm/arch/clock.h>
27   -#include <asm/arch/funcmux.h>
28   -#include <asm/arch/pmc.h>
29   -#include <asm/arch/sys_proto.h>
30   -#include <asm/arch/tegra20.h>
31   -#include <asm/arch/warmboot.h>
32   -
33   -DECLARE_GLOBAL_DATA_PTR;
34   -
35   -enum {
36   - /* UARTs which we can enable */
37   - UARTA = 1 << 0,
38   - UARTB = 1 << 1,
39   - UARTD = 1 << 3,
40   - UART_COUNT = 4,
41   -};
42   -
43   -/*
44   - * Boot ROM initializes the odmdata in APBDEV_PMC_SCRATCH20_0,
45   - * so we are using this value to identify memory size.
46   - */
47   -
48   -unsigned int query_sdram_size(void)
49   -{
50   - struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
51   - u32 reg;
52   -
53   - reg = readl(&pmc->pmc_scratch20);
54   - debug("pmc->pmc_scratch20 (ODMData) = 0x%08x\n", reg);
55   -
56   - /* bits 31:28 in OdmData are used for RAM size */
57   - switch ((reg) >> 28) {
58   - case 1:
59   - return 0x10000000; /* 256 MB */
60   - case 2:
61   - default:
62   - return 0x20000000; /* 512 MB */
63   - case 3:
64   - return 0x40000000; /* 1GB */
65   - }
66   -}
67   -
68   -int dram_init(void)
69   -{
70   - /* We do not initialise DRAM here. We just query the size */
71   - gd->ram_size = query_sdram_size();
72   - return 0;
73   -}
74   -
75   -#ifdef CONFIG_DISPLAY_BOARDINFO
76   -int checkboard(void)
77   -{
78   - printf("Board: %s\n", sysinfo.board_string);
79   - return 0;
80   -}
81   -#endif /* CONFIG_DISPLAY_BOARDINFO */
82   -
83   -static int uart_configs[] = {
84   -#if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
85   - FUNCMUX_UART1_UAA_UAB,
86   -#elif defined(CONFIG_TEGRA_UARTA_GPU)
87   - FUNCMUX_UART1_GPU,
88   -#elif defined(CONFIG_TEGRA_UARTA_SDIO1)
89   - FUNCMUX_UART1_SDIO1,
90   -#else
91   - FUNCMUX_UART1_IRRX_IRTX,
92   -#endif
93   - FUNCMUX_UART2_IRDA,
94   - -1,
95   - FUNCMUX_UART4_GMC,
96   - -1,
97   -};
98   -
99   -/**
100   - * Set up the specified uarts
101   - *
102   - * @param uarts_ids Mask containing UARTs to init (UARTx)
103   - */
104   -static void setup_uarts(int uart_ids)
105   -{
106   - static enum periph_id id_for_uart[] = {
107   - PERIPH_ID_UART1,
108   - PERIPH_ID_UART2,
109   - PERIPH_ID_UART3,
110   - PERIPH_ID_UART4,
111   - };
112   - size_t i;
113   -
114   - for (i = 0; i < UART_COUNT; i++) {
115   - if (uart_ids & (1 << i)) {
116   - enum periph_id id = id_for_uart[i];
117   -
118   - funcmux_select(id, uart_configs[i]);
119   - clock_ll_start_uart(id);
120   - }
121   - }
122   -}
123   -
124   -void board_init_uart_f(void)
125   -{
126   - int uart_ids = 0; /* bit mask of which UART ids to enable */
127   -
128   -#ifdef CONFIG_TEGRA_ENABLE_UARTA
129   - uart_ids |= UARTA;
130   -#endif
131   -#ifdef CONFIG_TEGRA_ENABLE_UARTB
132   - uart_ids |= UARTB;
133   -#endif
134   -#ifdef CONFIG_TEGRA_ENABLE_UARTD
135   - uart_ids |= UARTD;
136   -#endif
137   - setup_uarts(uart_ids);
138   -}
139   -
140   -#ifndef CONFIG_SYS_DCACHE_OFF
141   -void enable_caches(void)
142   -{
143   - /* Enable D-cache. I-cache is already enabled in start.S */
144   - dcache_enable();
145   -}
146   -#endif
arch/arm/cpu/tegra20-common/lowlevel_init.S
View file @ 3064f32
1   -/*
2   - * SoC-specific setup info
3   - *
4   - * (C) Copyright 2010,2011
5   - * NVIDIA Corporation <www.nvidia.com>
6   - *
7   - * See file CREDITS for list of people who contributed to this
8   - * project.
9   - *
10   - * This program is free software; you can redistribute it and/or
11   - * modify it under the terms of the GNU General Public License as
12   - * published by the Free Software Foundation; either version 2 of
13   - * the License, or (at your option) any later version.
14   - *
15   - * This program is distributed in the hope that it will be useful,
16   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
17   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18   - * GNU General Public License for more details.
19   - *
20   - * You should have received a copy of the GNU General Public License
21   - * along with this program; if not, write to the Free Software
22   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23   - * MA 02111-1307 USA
24   - */
25   -
26   -#include <config.h>
27   -#include <version.h>
28   -#include <linux/linkage.h>
29   -
30   - .align 5
31   -ENTRY(reset_cpu)
32   - ldr r1, rstctl @ get addr for global reset
33   - @ reg
34   - ldr r3, [r1]
35   - orr r3, r3, #0x10
36   - str r3, [r1] @ force reset
37   - mov r0, r0
38   -_loop_forever:
39   - b _loop_forever
40   -rstctl:
41   - .word PRM_RSTCTRL
42   -ENDPROC(reset_cpu)
arch/arm/cpu/tegra20-common/sys_info.c
View file @ 3064f32
1   -/*
2   - * (C) Copyright 2010,2011
3   - * NVIDIA Corporation <www.nvidia.com>
4   - *
5   - * See file CREDITS for list of people who contributed to this
6   - * project.
7   - *
8   - * This program is free software; you can redistribute it and/or
9   - * modify it under the terms of the GNU General Public License as
10   - * published by the Free Software Foundation; either version 2 of
11   - * the License, or (at your option) any later version.
12   - *
13   - * This program is distributed in the hope that it will be useful,
14   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
15   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   - * GNU General Public License for more details.
17   - *
18   - * You should have received a copy of the GNU General Public License
19   - * along with this program; if not, write to the Free Software
20   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   - * MA 02111-1307 USA
22   - */
23   -
24   -#include <common.h>
25   -
26   -#ifdef CONFIG_DISPLAY_CPUINFO
27   -/* Print CPU information */
28   -int print_cpuinfo(void)
29   -{
30   - puts("TEGRA20\n");
31   -
32   - /* TBD: Add printf of major/minor rev info, stepping, etc. */
33   - return 0;
34   -}
35   -#endif /* CONFIG_DISPLAY_CPUINFO */
arch/arm/cpu/tegra20-common/timer.c
View file @ 3064f32
1   -/*
2   - * (C) Copyright 2010,2011
3   - * NVIDIA Corporation <www.nvidia.com>
4   - *
5   - * (C) Copyright 2008
6   - * Texas Instruments
7   - *
8   - * Richard Woodruff <r-woodruff2@ti.com>
9   - * Syed Moahmmed Khasim <khasim@ti.com>
10   - *
11   - * (C) Copyright 2002
12   - * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
13   - * Marius Groeger <mgroeger@sysgo.de>
14   - * Alex Zuepke <azu@sysgo.de>
15   - *
16   - * (C) Copyright 2002
17   - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
18   - *
19   - * See file CREDITS for list of people who contributed to this
20   - * project.
21   - *
22   - * This program is free software; you can redistribute it and/or
23   - * modify it under the terms of the GNU General Public License as
24   - * published by the Free Software Foundation; either version 2 of
25   - * the License, or (at your option) any later version.
26   - *
27   - * This program is distributed in the hope that it will be useful,
28   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
29   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30   - * GNU General Public License for more details.
31   - *
32   - * You should have received a copy of the GNU General Public License
33   - * along with this program; if not, write to the Free Software
34   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
35   - * MA 02111-1307 USA
36   - */
37   -
38   -#include <common.h>
39   -#include <asm/io.h>
40   -#include <asm/arch/tegra20.h>
41   -#include <asm/arch/timer.h>
42   -
43   -DECLARE_GLOBAL_DATA_PTR;
44   -
45   -/* counter runs at 1MHz */
46   -#define TIMER_CLK 1000000
47   -#define TIMER_LOAD_VAL 0xffffffff
48   -
49   -/* timer without interrupts */
50   -ulong get_timer(ulong base)
51   -{
52   - return get_timer_masked() - base;
53   -}
54   -
55   -/* delay x useconds */
56   -void __udelay(unsigned long usec)
57   -{
58   - long tmo = usec * (TIMER_CLK / 1000) / 1000;
59   - unsigned long now, last = timer_get_us();
60   -
61   - while (tmo > 0) {
62   - now = timer_get_us();
63   - if (last > now) /* count up timer overflow */
64   - tmo -= TIMER_LOAD_VAL - last + now;
65   - else
66   - tmo -= now - last;
67   - last = now;
68   - }
69   -}
70   -
71   -ulong get_timer_masked(void)
72   -{
73   - ulong now;
74   -
75   - /* current tick value */
76   - now = timer_get_us() / (TIMER_CLK / CONFIG_SYS_HZ);
77   -
78   - if (now >= gd->lastinc) /* normal mode (non roll) */
79   - /* move stamp forward with absolute diff ticks */
80   - gd->tbl += (now - gd->lastinc);
81   - else /* we have rollover of incrementer */
82   - gd->tbl += ((TIMER_LOAD_VAL / (TIMER_CLK / CONFIG_SYS_HZ))
83   - - gd->lastinc) + now;
84   - gd->lastinc = now;
85   - return gd->tbl;
86   -}
87   -
88   -/*
89   - * This function is derived from PowerPC code (read timebase as long long).
90   - * On ARM it just returns the timer value.
91   - */
92   -unsigned long long get_ticks(void)
93   -{
94   - return get_timer(0);
95   -}
96   -
97   -/*
98   - * This function is derived from PowerPC code (timebase clock frequency).
99   - * On ARM it returns the number of timer ticks per second.
100   - */
101   -ulong get_tbclk(void)
102   -{
103   - return CONFIG_SYS_HZ;
104   -}
105   -
106   -unsigned long timer_get_us(void)
107   -{
108   - struct timerus *timer_base = (struct timerus *)NV_PA_TMRUS_BASE;
109   -
110   - return readl(&timer_base->cntr_1us);
111   -}
... ... @@ -67,6 +67,8 @@
67 67  
68 68 ifeq ($(SOC),tegra20)
69 69 LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o
  70 +LIBS-y += arch/$(ARCH)/cpu/tegra-common/libcputegra-common.o
  71 +LIBS-y += $(CPUDIR)/tegra-common/libtegra-common.o
70 72 endif
71 73  
72 74 # Add GCC lib