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Commit 30c4383da3fa2652e551b0610e71360394aa51e1

Authored by Chris Packham
Committed by Stefan Roese
1 parent 2acc24fc28
Exists in smarc_8mq_lf_v2020.04 and in 11 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

ARM: mvebu: sync Armada-38x dts with Linux 4.20 

Sync the Armada-38x device tree files with Linux 4.20-rc5. The changes
not taken are new compatible strings for the uart and nand flash
controller. The nand binding is best updated if/when the mtd/nand
infrastructure is updated.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>

Showing 6 changed files with 237 additions and 289 deletions Side-by-side Diff

arch/arm/dts/armada-380.dtsi
Diff comments   View file @ 30c4383
  1 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
1 2 /*
2 3 * Device Tree Include file for Marvell Armada 380 SoC.
3 4 *
... ... @@ -6,44 +7,6 @@
6 7 * Lior Amsalem <alior@marvell.com>
7 8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9   - *
10   - * This file is dual-licensed: you can use it either under the terms
11   - * of the GPL or the X11 license, at your option. Note that this dual
12   - * licensing only applies to this file, and not this project as a
13   - * whole.
14   - *
15   - * a) This file is free software; you can redistribute it and/or
16   - * modify it under the terms of the GNU General Public License as
17   - * published by the Free Software Foundation; either version 2 of the
18   - * License, or (at your option) any later version.
19   - *
20   - * This file is distributed in the hope that it will be useful
21   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
22   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23   - * GNU General Public License for more details.
24   - *
25   - * Or, alternatively
26   - *
27   - * b) Permission is hereby granted, free of charge, to any person
28   - * obtaining a copy of this software and associated documentation
29   - * files (the "Software"), to deal in the Software without
30   - * restriction, including without limitation the rights to use
31   - * copy, modify, merge, publish, distribute, sublicense, and/or
32   - * sell copies of the Software, and to permit persons to whom the
33   - * Software is furnished to do so, subject to the following
34   - * conditions:
35   - *
36   - * The above copyright notice and this permission notice shall be
37   - * included in all copies or substantial portions of the Software.
38   - *
39   - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40   - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41   - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42   - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43   - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44   - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45   - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46   - * OTHER DEALINGS IN THE SOFTWARE.
47 10 */
48 11  
49 12 #include "armada-38x.dtsi"
... ... @@ -71,7 +34,7 @@
71 34 };
72 35 };
73 36  
74   - pcie-controller {
  37 + pcie {
75 38 compatible = "marvell,armada-370-pcie";
76 39 status = "disabled";
77 40 device_type = "pci";
... ... @@ -104,6 +67,7 @@
104 67 #interrupt-cells = <1>;
105 68 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
106 69 0x81000000 0 0 0x81000000 0x1 0 1 0>;
  70 + bus-range = <0x00 0xff>;
107 71 interrupt-map-mask = <0 0 0 0>;
108 72 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
109 73 marvell,pcie-port = <0>;
... ... @@ -122,6 +86,7 @@
122 86 #interrupt-cells = <1>;
123 87 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
124 88 0x81000000 0 0 0x81000000 0x2 0 1 0>;
  89 + bus-range = <0x00 0xff>;
125 90 interrupt-map-mask = <0 0 0 0>;
126 91 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
127 92 marvell,pcie-port = <1>;
... ... @@ -140,6 +105,7 @@
140 105 #interrupt-cells = <1>;
141 106 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
142 107 0x81000000 0 0 0x81000000 0x3 0 1 0>;
  108 + bus-range = <0x00 0xff>;
143 109 interrupt-map-mask = <0 0 0 0>;
144 110 interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
145 111 marvell,pcie-port = <2>;
arch/arm/dts/armada-385.dtsi
Diff comments   View file @ 30c4383
  1 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
1 2 /*
2 3 * Device Tree Include file for Marvell Armada 385 SoC.
3 4 *
... ... @@ -6,44 +7,6 @@
6 7 * Lior Amsalem <alior@marvell.com>
7 8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9   - *
10   - * This file is dual-licensed: you can use it either under the terms
11   - * of the GPL or the X11 license, at your option. Note that this dual
12   - * licensing only applies to this file, and not this project as a
13   - * whole.
14   - *
15   - * a) This file is free software; you can redistribute it and/or
16   - * modify it under the terms of the GNU General Public License as
17   - * published by the Free Software Foundation; either version 2 of the
18   - * License, or (at your option) any later version.
19   - *
20   - * This file is distributed in the hope that it will be useful
21   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
22   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23   - * GNU General Public License for more details.
24   - *
25   - * Or, alternatively
26   - *
27   - * b) Permission is hereby granted, free of charge, to any person
28   - * obtaining a copy of this software and associated documentation
29   - * files (the "Software"), to deal in the Software without
30   - * restriction, including without limitation the rights to use
31   - * copy, modify, merge, publish, distribute, sublicense, and/or
32   - * sell copies of the Software, and to permit persons to whom the
33   - * Software is furnished to do so, subject to the following
34   - * conditions:
35   - *
36   - * The above copyright notice and this permission notice shall be
37   - * included in all copies or substantial portions of the Software.
38   - *
39   - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40   - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41   - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42   - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43   - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44   - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45   - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46   - * OTHER DEALINGS IN THE SOFTWARE.
47 10 */
48 11  
49 12 #include "armada-38x.dtsi"
... ... @@ -70,13 +33,7 @@
70 33 };
71 34  
72 35 soc {
73   - internal-regs {
74   - pinctrl@18000 {
75   - compatible = "marvell,mv88f6820-pinctrl";
76   - };
77   - };
78   -
79   - pcie-controller {
  36 + pciec: pcie {
80 37 compatible = "marvell,armada-370-pcie";
81 38 status = "disabled";
82 39 device_type = "pci";
... ... @@ -106,7 +63,7 @@
106 63 * configured in x4 by the bootloader, then
107 64 * pcie@4,0 is not available.
108 65 */
109   - pcie@1,0 {
  66 + pcie1: pcie@1,0 {
110 67 device_type = "pci";
111 68 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
112 69 reg = <0x0800 0 0 0 0>;
... ... @@ -115,6 +72,7 @@
115 72 #interrupt-cells = <1>;
116 73 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
117 74 0x81000000 0 0 0x81000000 0x1 0 1 0>;
  75 + bus-range = <0x00 0xff>;
118 76 interrupt-map-mask = <0 0 0 0>;
119 77 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
120 78 marvell,pcie-port = <0>;
... ... @@ -124,7 +82,7 @@
124 82 };
125 83  
126 84 /* x1 port */
127   - pcie@2,0 {
  85 + pcie2: pcie@2,0 {
128 86 device_type = "pci";
129 87 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
130 88 reg = <0x1000 0 0 0 0>;
... ... @@ -133,6 +91,7 @@
133 91 #interrupt-cells = <1>;
134 92 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
135 93 0x81000000 0 0 0x81000000 0x2 0 1 0>;
  94 + bus-range = <0x00 0xff>;
136 95 interrupt-map-mask = <0 0 0 0>;
137 96 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
138 97 marvell,pcie-port = <1>;
... ... @@ -142,7 +101,7 @@
142 101 };
143 102  
144 103 /* x1 port */
145   - pcie@3,0 {
  104 + pcie3: pcie@3,0 {
146 105 device_type = "pci";
147 106 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
148 107 reg = <0x1800 0 0 0 0>;
... ... @@ -151,6 +110,7 @@
151 110 #interrupt-cells = <1>;
152 111 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
153 112 0x81000000 0 0 0x81000000 0x3 0 1 0>;
  113 + bus-range = <0x00 0xff>;
154 114 interrupt-map-mask = <0 0 0 0>;
155 115 interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
156 116 marvell,pcie-port = <2>;
... ... @@ -163,7 +123,7 @@
163 123 * x1 port only available when pcie@1,0 is
164 124 * configured as a x1 port
165 125 */
166   - pcie@4,0 {
  126 + pcie4: pcie@4,0 {
167 127 device_type = "pci";
168 128 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
169 129 reg = <0x2000 0 0 0 0>;
... ... @@ -172,6 +132,7 @@
172 132 #interrupt-cells = <1>;
173 133 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
174 134 0x81000000 0 0 0x81000000 0x4 0 1 0>;
  135 + bus-range = <0x00 0xff>;
175 136 interrupt-map-mask = <0 0 0 0>;
176 137 interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
177 138 marvell,pcie-port = <3>;
... ... @@ -181,5 +142,9 @@
181 142 };
182 143 };
183 144 };
  145 +};
  146 +
  147 +&pinctrl {
  148 + compatible = "marvell,mv88f6820-pinctrl";
184 149 };
arch/arm/dts/armada-388-clearfog.dts
Diff comments   View file @ 30c4383
... ... @@ -118,18 +118,7 @@
118 118 status = "okay";
119 119 };
120 120  
121   - spi1: spi@10680 {
122   - /*
123   - * CS0: W25Q32
124   - * CS1:
125   - * CS2: mikrobus
126   - */
127   - pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>;
128   - pinctrl-names = "default";
129   - status = "okay";
130   - };
131   -
132   - usb0: usb3@f8000 {
  121 + usb3@f8000 {
133 122 /* CON7, USB-A port on back of device */
134 123 status = "okay";
135 124 };
... ... @@ -320,6 +309,18 @@
320 309 marvell,pins = "mpp34";
321 310 marvell,function = "gpio";
322 311 };
  312 +};
  313 +
  314 +&spi1 {
  315 + /*
  316 + * Add SPI CS pins for clearfog:
  317 + * CS0: W25Q32
  318 + * CS1:
  319 + * CS2: mikrobus
  320 + */
  321 + pinctrl-0 = <&spi1_pins &mikro_spi_pins>;
  322 + pinctrl-names = "default";
  323 + status = "okay";
323 324 };
324 325  
325 326 /*
arch/arm/dts/armada-388.dtsi
Diff comments   View file @ 30c4383
  1 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
1 2 /*
2 3 * Device Tree Include file for Marvell Armada 388 SoC.
3 4 *
... ... @@ -5,39 +6,6 @@
5 6 *
6 7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 8 *
8   - * This file is dual-licensed: you can use it either under the terms
9   - * of the GPL or the X11 license, at your option. Note that this dual
10   - * licensing only applies to this file, and not this project as a
11   - * whole.
12   - *
13   - * a) This file is licensed under the terms of the GNU General Public
14   - * License version 2. This program is licensed "as is" without
15   - * any warranty of any kind, whether express or implied.
16   - *
17   - * Or, alternatively,
18   - *
19   - * b) Permission is hereby granted, free of charge, to any person
20   - * obtaining a copy of this software and associated documentation
21   - * files (the "Software"), to deal in the Software without
22   - * restriction, including without limitation the rights to use,
23   - * copy, modify, merge, publish, distribute, sublicense, and/or
24   - * sell copies of the Software, and to permit persons to whom the
25   - * Software is furnished to do so, subject to the following
26   - * conditions:
27   - *
28   - * The above copyright notice and this permission notice shall be
29   - * included in all copies or substantial portions of the Software.
30   - *
31   - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32   - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33   - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34   - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35   - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36   - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37   - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38   - * OTHER DEALINGS IN THE SOFTWARE.
39   - *
40   - *
41 9 * The main difference with the Armada 385 is that the 388 can handle two more
42 10 * SATA ports. So we can reuse the dtsi of the Armada 385, override the pinctrl
43 11 * property and the name of the SoC, and add the second SATA host which control
44 12  
... ... @@ -50,13 +18,8 @@
50 18 model = "Marvell Armada 388 family SoC";
51 19 compatible = "marvell,armada388", "marvell,armada385",
52 20 "marvell,armada380";
53   -
54 21 soc {
55 22 internal-regs {
56   - pinctrl@18000 {
57   - compatible = "marvell,mv88f6828-pinctrl";
58   - };
59   -
60 23 sata@e0000 {
61 24 compatible = "marvell,armada-380-ahci";
62 25 reg = <0xe0000 0x2000>;
... ... @@ -67,5 +30,9 @@
67 30  
68 31 };
69 32 };
  33 +};
  34 +
  35 +&pinctrl {
  36 + compatible = "marvell,mv88f6828-pinctrl";
70 37 };
arch/arm/dts/armada-38x-controlcenterdc.dts
Diff comments   View file @ 30c4383
... ... @@ -72,40 +72,6 @@
72 72 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
73 73  
74 74 internal-regs {
75   - spi0: spi@10600 {
76   - status = "okay";
77   - sc16is741: sc16is741@0 {
78   - compatible = "nxp,sc16is741";
79   - reg = <0>;
80   - clocks = <&sc16isclk>;
81   - spi-max-frequency = <4000000>;
82   - interrupt-parent = <&gpio0>;
83   - interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
84   - gpio-controller;
85   - #gpio-cells = <2>;
86   - };
87   - };
88   -
89   - spi1: spi@10680 {
90   - status = "okay";
91   - u-boot,dm-pre-reloc;
92   - spi-flash@0 {
93   - #address-cells = <1>;
94   - #size-cells = <1>;
95   - compatible = "n25q016a", "spi-flash";
96   - reg = <0>; /* Chip select 0 */
97   - spi-max-frequency = <108000000>;
98   - };
99   - spi-flash@1 {
100   - #address-cells = <1>;
101   - #size-cells = <1>;
102   - compatible = "n25q128a11", "spi-flash";
103   - reg = <1>; /* Chip select 1 */
104   - spi-max-frequency = <108000000>;
105   - u-boot,dm-pre-reloc;
106   - };
107   - };
108   -
109 75 I2C0: i2c@11000 {
110 76 status = "okay";
111 77 clock-frequency = <1000000>;
... ... @@ -584,6 +550,40 @@
584 550 label = "status-led";
585 551 gpios = <&gpio0 29 0>;
586 552 };
  553 + };
  554 +};
  555 +
  556 +&spi0 {
  557 + status = "okay";
  558 + sc16is741: sc16is741@0 {
  559 + compatible = "nxp,sc16is741";
  560 + reg = <0>;
  561 + clocks = <&sc16isclk>;
  562 + spi-max-frequency = <4000000>;
  563 + interrupt-parent = <&gpio0>;
  564 + interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
  565 + gpio-controller;
  566 + #gpio-cells = <2>;
  567 + };
  568 +};
  569 +
  570 +&spi1 {
  571 + status = "okay";
  572 + u-boot,dm-pre-reloc;
  573 + spi-flash@0 {
  574 + #address-cells = <1>;
  575 + #size-cells = <1>;
  576 + compatible = "n25q016a", "spi-flash";
  577 + reg = <0>; /* Chip select 0 */
  578 + spi-max-frequency = <108000000>;
  579 + };
  580 + spi-flash@1 {
  581 + #address-cells = <1>;
  582 + #size-cells = <1>;
  583 + compatible = "n25q128a11", "spi-flash";
  584 + reg = <1>; /* Chip select 1 */
  585 + spi-max-frequency = <108000000>;
  586 + u-boot,dm-pre-reloc;
587 587 };
588 588 };
arch/arm/dts/armada-38x.dtsi
Diff comments   View file @ 30c4383
  1 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
1 2 /*
2 3 * Device Tree Include file for Marvell Armada 38x family of SoCs.
3 4 *
... ... @@ -6,44 +7,6 @@
6 7 * Lior Amsalem <alior@marvell.com>
7 8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9   - *
10   - * This file is dual-licensed: you can use it either under the terms
11   - * of the GPL or the X11 license, at your option. Note that this dual
12   - * licensing only applies to this file, and not this project as a
13   - * whole.
14   - *
15   - * a) This file is free software; you can redistribute it and/or
16   - * modify it under the terms of the GNU General Public License as
17   - * published by the Free Software Foundation; either version 2 of the
18   - * License, or (at your option) any later version.
19   - *
20   - * This file is distributed in the hope that it will be useful
21   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
22   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23   - * GNU General Public License for more details.
24   - *
25   - * Or, alternatively
26   - *
27   - * b) Permission is hereby granted, free of charge, to any person
28   - * obtaining a copy of this software and associated documentation
29   - * files (the "Software"), to deal in the Software without
30   - * restriction, including without limitation the rights to use
31   - * copy, modify, merge, publish, distribute, sublicense, and/or
32   - * sell copies of the Software, and to permit persons to whom the
33   - * Software is furnished to do so, subject to the following
34   - * conditions:
35   - *
36   - * The above copyright notice and this permission notice shall be
37   - * included in all copies or substantial portions of the Software.
38   - *
39   - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40   - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41   - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42   - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43   - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44   - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45   - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46   - * OTHER DEALINGS IN THE SOFTWARE.
47 10 */
48 11  
49 12 #include "skeleton.dtsi"
... ... @@ -83,7 +46,7 @@
83 46 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
84 47 };
85 48  
86   - devbus-bootcs {
  49 + devbus_bootcs: devbus-bootcs {
87 50 compatible = "marvell,mvebu-devbus";
88 51 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
89 52 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
... ... @@ -93,7 +56,7 @@
93 56 status = "disabled";
94 57 };
95 58  
96   - devbus-cs0 {
  59 + devbus_cs0: devbus-cs0 {
97 60 compatible = "marvell,mvebu-devbus";
98 61 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
99 62 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
... ... @@ -103,7 +66,7 @@
103 66 status = "disabled";
104 67 };
105 68  
106   - devbus-cs1 {
  69 + devbus_cs1: devbus-cs1 {
107 70 compatible = "marvell,mvebu-devbus";
108 71 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
109 72 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
... ... @@ -113,7 +76,7 @@
113 76 status = "disabled";
114 77 };
115 78  
116   - devbus-cs2 {
  79 + devbus_cs2: devbus-cs2 {
117 80 compatible = "marvell,mvebu-devbus";
118 81 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
119 82 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
... ... @@ -123,7 +86,7 @@
123 86 status = "disabled";
124 87 };
125 88  
126   - devbus-cs3 {
  89 + devbus_cs3: devbus-cs3 {
127 90 compatible = "marvell,mvebu-devbus";
128 91 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
129 92 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
... ... @@ -145,6 +108,10 @@
145 108 reg = <0x8000 0x1000>;
146 109 cache-unified;
147 110 cache-level = <2>;
  111 + arm,double-linefill-incr = <0>;
  112 + arm,double-linefill-wrap = <0>;
  113 + arm,double-linefill = <0>;
  114 + prefetch-data = <1>;
148 115 };
149 116  
150 117 scu@c000 {
... ... @@ -152,6 +119,13 @@
152 119 reg = <0xc000 0x58>;
153 120 };
154 121  
  122 + timer@c200 {
  123 + compatible = "arm,cortex-a9-global-timer";
  124 + reg = <0xc200 0x20>;
  125 + interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
  126 + clocks = <&coreclk 2>;
  127 + };
  128 +
155 129 timer@c600 {
156 130 compatible = "arm,cortex-a9-twd-timer";
157 131 reg = <0xc600 0x20>;
158 132  
... ... @@ -168,32 +142,8 @@
168 142 <0xc100 0x100>;
169 143 };
170 144  
171   - spi0: spi@10600 {
172   - compatible = "marvell,armada-380-spi",
173   - "marvell,orion-spi";
174   - reg = <0x10600 0x50>;
175   - #address-cells = <1>;
176   - #size-cells = <0>;
177   - cell-index = <0>;
178   - interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
179   - clocks = <&coreclk 0>;
180   - status = "disabled";
181   - };
182   -
183   - spi1: spi@10680 {
184   - compatible = "marvell,armada-380-spi",
185   - "marvell,orion-spi";
186   - reg = <0x10680 0x50>;
187   - #address-cells = <1>;
188   - #size-cells = <0>;
189   - cell-index = <1>;
190   - interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
191   - clocks = <&coreclk 0>;
192   - status = "disabled";
193   - };
194   -
195 145 i2c0: i2c@11000 {
196   - compatible = "marvell,mv64xxx-i2c";
  146 + compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
197 147 reg = <0x11000 0x20>;
198 148 #address-cells = <1>;
199 149 #size-cells = <0>;
... ... @@ -204,7 +154,7 @@
204 154 };
205 155  
206 156 i2c1: i2c@11100 {
207   - compatible = "marvell,mv64xxx-i2c";
  157 + compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
208 158 reg = <0x11100 0x20>;
209 159 #address-cells = <1>;
210 160 #size-cells = <0>;
... ... @@ -258,19 +208,6 @@
258 208 marvell,function = "i2c0";
259 209 };
260 210  
261   - nand_pins: nand-pins {
262   - marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33",
263   - "mpp38", "mpp28", "mpp40", "mpp42",
264   - "mpp35", "mpp36", "mpp25", "mpp30",
265   - "mpp32";
266   - marvell,function = "dev";
267   - };
268   -
269   - nand_rb: nand-rb {
270   - marvell,pins = "mpp41";
271   - marvell,function = "nand";
272   - };
273   -
274 211 mdio_pins: mdio-pins {
275 212 marvell,pins = "mpp4", "mpp5";
276 213 marvell,function = "ge";
... ... @@ -298,6 +235,20 @@
298 235 marvell,function = "spi1";
299 236 };
300 237  
  238 + nand_pins: nand-pins {
  239 + marvell,pins = "mpp22", "mpp34", "mpp23",
  240 + "mpp33", "mpp38", "mpp28",
  241 + "mpp40", "mpp42", "mpp35",
  242 + "mpp36", "mpp25", "mpp30",
  243 + "mpp32";
  244 + marvell,function = "dev";
  245 + };
  246 +
  247 + nand_rb: nand-rb {
  248 + marvell,pins = "mpp41";
  249 + marvell,function = "nand";
  250 + };
  251 +
301 252 uart0_pins: uart-pins-0 {
302 253 marvell,pins = "mpp0", "mpp1";
303 254 marvell,function = "ua0";
304 255  
305 256  
306 257  
307 258  
308 259  
309 260  
... ... @@ -338,34 +289,42 @@
338 289 };
339 290  
340 291 gpio0: gpio@18100 {
341   - compatible = "marvell,orion-gpio";
342   - reg = <0x18100 0x40>;
  292 + compatible = "marvell,armada-370-gpio",
  293 + "marvell,orion-gpio";
  294 + reg = <0x18100 0x40>, <0x181c0 0x08>;
  295 + reg-names = "gpio", "pwm";
343 296 ngpios = <32>;
344 297 gpio-controller;
345 298 #gpio-cells = <2>;
  299 + #pwm-cells = <2>;
346 300 interrupt-controller;
347 301 #interrupt-cells = <2>;
348 302 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
349 303 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
350 304 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
351 305 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
  306 + clocks = <&coreclk 0>;
352 307 };
353 308  
354 309 gpio1: gpio@18140 {
355   - compatible = "marvell,orion-gpio";
356   - reg = <0x18140 0x40>;
  310 + compatible = "marvell,armada-370-gpio",
  311 + "marvell,orion-gpio";
  312 + reg = <0x18140 0x40>, <0x181c8 0x08>;
  313 + reg-names = "gpio", "pwm";
357 314 ngpios = <28>;
358 315 gpio-controller;
359 316 #gpio-cells = <2>;
  317 + #pwm-cells = <2>;
360 318 interrupt-controller;
361 319 #interrupt-cells = <2>;
362 320 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
363 321 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
364 322 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
365 323 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
  324 + clocks = <&coreclk 0>;
366 325 };
367 326  
368   - system-controller@18200 {
  327 + systemc: system-controller@18200 {
369 328 compatible = "marvell,armada-380-system-controller",
370 329 "marvell,armada-370-xp-system-controller";
371 330 reg = <0x18200 0x100>;
... ... @@ -386,7 +345,8 @@
386 345  
387 346 mbusc: mbus-controller@20000 {
388 347 compatible = "marvell,mbus-controller";
389   - reg = <0x20000 0x100>, <0x20180 0x20>;
  348 + reg = <0x20000 0x100>, <0x20180 0x20>,
  349 + <0x20250 0x8>;
390 350 };
391 351  
392 352 mpic: interrupt-controller@20a00 {
... ... @@ -399,7 +359,7 @@
399 359 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
400 360 };
401 361  
402   - timer@20300 {
  362 + timer: timer@20300 {
403 363 compatible = "marvell,armada-380-timer",
404 364 "marvell,armada-xp-timer";
405 365 reg = <0x20300 0x30>, <0x21040 0x30>;
406 366  
... ... @@ -413,14 +373,14 @@
413 373 clock-names = "nbclk", "fixed";
414 374 };
415 375  
416   - watchdog@20300 {
  376 + watchdog: watchdog@20300 {
417 377 compatible = "marvell,armada-380-wdt";
418 378 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
419 379 clocks = <&coreclk 2>, <&refclk>;
420 380 clock-names = "nbclk", "fixed";
421 381 };
422 382  
423   - cpurst@20800 {
  383 + cpurst: cpurst@20800 {
424 384 compatible = "marvell,armada-370-cpu-reset";
425 385 reg = <0x20800 0x10>;
426 386 };
427 387  
428 388  
... ... @@ -430,16 +390,37 @@
430 390 reg = <0x20d20 0x6c>;
431 391 };
432 392  
433   - coherency-fabric@21010 {
  393 + coherencyfab: coherency-fabric@21010 {
434 394 compatible = "marvell,armada-380-coherency-fabric";
435 395 reg = <0x21010 0x1c>;
436 396 };
437 397  
438   - pmsu@22000 {
  398 + pmsu: pmsu@22000 {
439 399 compatible = "marvell,armada-380-pmsu";
440 400 reg = <0x22000 0x1000>;
441 401 };
442 402  
  403 + /*
  404 + * As a special exception to the "order by
  405 + * register address" rule, the eth0 node is
  406 + * placed here to ensure that it gets
  407 + * registered as the first interface, since
  408 + * the network subsystem doesn't allow naming
  409 + * interfaces using DT aliases. Without this,
  410 + * the ordering of interfaces is different
  411 + * from the one used in U-Boot and the
  412 + * labeling of interfaces on the boards, which
  413 + * is very confusing for users.
  414 + */
  415 + eth0: ethernet@70000 {
  416 + compatible = "marvell,armada-370-neta";
  417 + reg = <0x70000 0x4000>;
  418 + interrupts-extended = <&mpic 8>;
  419 + clocks = <&gateclk 4>;
  420 + tx-csum-limit = <9800>;
  421 + status = "disabled";
  422 + };
  423 +
443 424 eth1: ethernet@30000 {
444 425 compatible = "marvell,armada-370-neta";
445 426 reg = <0x30000 0x4000>;
... ... @@ -456,7 +437,7 @@
456 437 status = "disabled";
457 438 };
458 439  
459   - usb@58000 {
  440 + usb0: usb@58000 {
460 441 compatible = "marvell,orion-ehci";
461 442 reg = <0x58000 0x500>;
462 443 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
... ... @@ -464,8 +445,8 @@
464 445 status = "disabled";
465 446 };
466 447  
467   - xor@60800 {
468   - compatible = "marvell,orion-xor";
  448 + xor0: xor@60800 {
  449 + compatible = "marvell,armada-380-xor", "marvell,orion-xor";
469 450 reg = <0x60800 0x100
470 451 0x60a00 0x100>;
471 452 clocks = <&gateclk 22>;
... ... @@ -484,8 +465,8 @@
484 465 };
485 466 };
486 467  
487   - xor@60900 {
488   - compatible = "marvell,orion-xor";
  468 + xor1: xor@60900 {
  469 + compatible = "marvell,armada-380-xor", "marvell,orion-xor";
489 470 reg = <0x60900 0x100
490 471 0x60b00 0x100>;
491 472 clocks = <&gateclk 28>;
... ... @@ -504,14 +485,6 @@
504 485 };
505 486 };
506 487  
507   - eth0: ethernet@70000 {
508   - compatible = "marvell,armada-370-neta";
509   - reg = <0x70000 0x4000>;
510   - interrupts-extended = <&mpic 8>;
511   - clocks = <&gateclk 4>;
512   - status = "disabled";
513   - };
514   -
515 488 mdio: mdio@72004 {
516 489 #address-cells = <1>;
517 490 #size-cells = <0>;
518 491  
... ... @@ -520,14 +493,29 @@
520 493 clocks = <&gateclk 4>;
521 494 };
522 495  
523   - rtc@a3800 {
  496 + cesa: crypto@90000 {
  497 + compatible = "marvell,armada-38x-crypto";
  498 + reg = <0x90000 0x10000>;
  499 + reg-names = "regs";
  500 + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
  501 + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
  502 + clocks = <&gateclk 23>, <&gateclk 21>,
  503 + <&gateclk 14>, <&gateclk 16>;
  504 + clock-names = "cesa0", "cesa1",
  505 + "cesaz0", "cesaz1";
  506 + marvell,crypto-srams = <&crypto_sram0>,
  507 + <&crypto_sram1>;
  508 + marvell,crypto-sram-size = <0x800>;
  509 + };
  510 +
  511 + rtc: rtc@a3800 {
524 512 compatible = "marvell,armada-380-rtc";
525 513 reg = <0xa3800 0x20>, <0x184a0 0x0c>;
526 514 reg-names = "rtc", "rtc-soc";
527 515 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
528 516 };
529 517  
530   - sata@a8000 {
  518 + ahci0: sata@a8000 {
531 519 compatible = "marvell,armada-380-ahci";
532 520 reg = <0xa8000 0x2000>;
533 521 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
... ... @@ -535,7 +523,15 @@
535 523 status = "disabled";
536 524 };
537 525  
538   - sata@e0000 {
  526 + bm: bm@c8000 {
  527 + compatible = "marvell,armada-380-neta-bm";
  528 + reg = <0xc8000 0xac>;
  529 + clocks = <&gateclk 13>;
  530 + internal-mem = <&bm_bppi>;
  531 + status = "disabled";
  532 + };
  533 +
  534 + ahci1: sata@e0000 {
539 535 compatible = "marvell,armada-380-ahci";
540 536 reg = <0xe0000 0x2000>;
541 537 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
542 538  
543 539  
544 540  
545 541  
... ... @@ -551,23 +547,23 @@
551 547 clock-output-names = "nand";
552 548 };
553 549  
554   - thermal@e8078 {
  550 + thermal: thermal@e8078 {
555 551 compatible = "marvell,armada380-thermal";
556   - reg = <0xe4078 0x4>, <0xe4074 0x4>;
  552 + reg = <0xe4078 0x4>, <0xe4070 0x8>;
557 553 status = "okay";
558 554 };
559 555  
560   - flash@d0000 {
  556 + nand_controller: nand-controller@d0000 {
561 557 compatible = "marvell,armada370-nand","marvell,mvebu-pxa3xx-nand";
562 558 reg = <0xd0000 0x54>;
563 559 #address-cells = <1>;
564   - #size-cells = <1>;
  560 + #size-cells = <0>;
565 561 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
566 562 clocks = <&coredivclk 0>;
567 563 status = "disabled";
568 564 };
569 565  
570   - sdhci@d8000 {
  566 + sdhci: sdhci@d8000 {
571 567 compatible = "marvell,armada-380-sdhci";
572 568 reg-names = "sdhci", "mbus", "conf-sdio3";
573 569 reg = <0xd8000 0x1000>,
... ... @@ -579,7 +575,7 @@
579 575 status = "disabled";
580 576 };
581 577  
582   - usb3@f0000 {
  578 + usb3_0: usb3@f0000 {
583 579 compatible = "marvell,armada-380-xhci";
584 580 reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
585 581 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
... ... @@ -587,7 +583,7 @@
587 583 status = "disabled";
588 584 };
589 585  
590   - usb3@f8000 {
  586 + usb3_1: usb3@f8000 {
591 587 compatible = "marvell,armada-380-xhci";
592 588 reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
593 589 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
594 590  
... ... @@ -595,10 +591,63 @@
595 591 status = "disabled";
596 592 };
597 593 };
  594 +
  595 + crypto_sram0: sa-sram0 {
  596 + compatible = "mmio-sram";
  597 + reg = <MBUS_ID(0x09, 0x19) 0 0x800>;
  598 + clocks = <&gateclk 23>;
  599 + #address-cells = <1>;
  600 + #size-cells = <1>;
  601 + ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>;
  602 + };
  603 +
  604 + crypto_sram1: sa-sram1 {
  605 + compatible = "mmio-sram";
  606 + reg = <MBUS_ID(0x09, 0x15) 0 0x800>;
  607 + clocks = <&gateclk 21>;
  608 + #address-cells = <1>;
  609 + #size-cells = <1>;
  610 + ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>;
  611 + };
  612 +
  613 + bm_bppi: bm-bppi {
  614 + compatible = "mmio-sram";
  615 + reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
  616 + ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
  617 + #address-cells = <1>;
  618 + #size-cells = <1>;
  619 + clocks = <&gateclk 13>;
  620 + no-memory-wc;
  621 + status = "disabled";
  622 + };
  623 +
  624 + spi0: spi@10600 {
  625 + compatible = "marvell,armada-380-spi",
  626 + "marvell,orion-spi";
  627 + reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
  628 + #address-cells = <1>;
  629 + #size-cells = <0>;
  630 + cell-index = <0>;
  631 + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  632 + clocks = <&coreclk 0>;
  633 + status = "disabled";
  634 + };
  635 +
  636 + spi1: spi@10680 {
  637 + compatible = "marvell,armada-380-spi",
  638 + "marvell,orion-spi";
  639 + reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
  640 + #address-cells = <1>;
  641 + #size-cells = <0>;
  642 + cell-index = <1>;
  643 + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
  644 + clocks = <&coreclk 0>;
  645 + status = "disabled";
  646 + };
598 647 };
599 648  
600 649 clocks {
601   - /* 2 GHz fixed main PLL */
  650 + /* 1 GHz fixed main PLL */
602 651 mainpll: mainpll {
603 652 compatible = "fixed-clock";
604 653 #clock-cells = <0>;