Commit 30ed21e40335404ddfd92738561ab646887e05a4
1 parent
f96ee85523
Exists in
smarc_8mq-imx_v2020.04_5.4.24_2.1.0
and in
3 other branches
MLK-23574-49 mx7ulp_val: Add 10x10 and 14x14 validation board support
Porting the iMX7ULP 10x10 validation board and 14x14 validation board codes from v2019.04 u-boot. Signed-off-by: Ye Li <ye.li@nxp.com>
Showing 13 changed files with 1366 additions and 0 deletions Side-by-side Diff
- arch/arm/dts/Makefile
- arch/arm/dts/imx7ulp-10x10-val.dts
- arch/arm/dts/imx7ulp-14x14-val.dts
- arch/arm/mach-imx/mx7ulp/Kconfig
- board/freescale/mx7ulp_val/Kconfig
- board/freescale/mx7ulp_val/Makefile
- board/freescale/mx7ulp_val/imximage.cfg
- board/freescale/mx7ulp_val/imximage_lpddr2.cfg
- board/freescale/mx7ulp_val/mx7ulp_val.c
- board/freescale/mx7ulp_val/plugin.S
- configs/mx7ulp_10x10_val_defconfig
- configs/mx7ulp_14x14_val_defconfig
- include/configs/mx7ulp_val.h
arch/arm/dts/Makefile
arch/arm/dts/imx7ulp-10x10-val.dts
1 | +/* | |
2 | + * Copyright 2016 Freescale Semiconductor, Inc. | |
3 | + * | |
4 | + * This program is free software; you can redistribute it and/or modify | |
5 | + * it under the terms of the GNU General Public License version 2 as | |
6 | + * published by the Free Software Foundation. | |
7 | + */ | |
8 | + | |
9 | +/dts-v1/; | |
10 | + | |
11 | +#include "imx7ulp.dtsi" | |
12 | + | |
13 | +/ { | |
14 | + model = "NXP i.MX7ULP 10x10 val"; | |
15 | + compatible = "fsl,imx7ulp-10x10-val", "fsl,imx7ulp", "Generic DT based system"; | |
16 | + | |
17 | + chosen { | |
18 | + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x40A60000,115200"; | |
19 | + stdout-path = &lpuart6; | |
20 | + }; | |
21 | + | |
22 | + memory { | |
23 | + device_type = "memory"; | |
24 | + reg = <0x60000000 0x40000000>; | |
25 | + }; | |
26 | +}; | |
27 | + | |
28 | +&iomuxc1 { | |
29 | + pinctrl-names = "default"; | |
30 | + | |
31 | + imx7ulp-10x10-val { | |
32 | + pinctrl_lpuart6: lpuart6grp { | |
33 | + fsl,pins = < | |
34 | + IMX7ULP_PAD_PTE11__LPUART6_RX 0x400 | |
35 | + IMX7ULP_PAD_PTE10__LPUART6_TX 0x400 | |
36 | + >; | |
37 | + }; | |
38 | + | |
39 | + pinctrl_usdhc1: usdhc1grp { | |
40 | + fsl,pins = < | |
41 | + IMX7ULP_PAD_PTE3__SDHC1_CMD 0x843 | |
42 | + IMX7ULP_PAD_PTE2__SDHC1_CLK 0x843 | |
43 | + IMX7ULP_PAD_PTE4__SDHC1_D3 0x843 | |
44 | + IMX7ULP_PAD_PTE5__SDHC1_D2 0x843 | |
45 | + IMX7ULP_PAD_PTE0__SDHC1_D1 0x843 | |
46 | + IMX7ULP_PAD_PTE1__SDHC1_D0 0x843 | |
47 | + >; | |
48 | + }; | |
49 | + | |
50 | + pinctrl_qspi1_1: qspi1grp_1 { | |
51 | + fsl,pins = < | |
52 | + IMX7ULP_PAD_PTB14__QSPIA_SS1_B 0x43 /* SS1 */ | |
53 | + IMX7ULP_PAD_PTB8__QSPIA_SS0_B 0x43 /* SS0 */ | |
54 | + IMX7ULP_PAD_PTB15__QSPIA_SCLK 0x43 /* SCLK */ | |
55 | + IMX7ULP_PAD_PTB16__QSPIA_DATA3 0x43 /* D3 */ | |
56 | + IMX7ULP_PAD_PTB17__QSPIA_DATA2 0x43 /* D2 */ | |
57 | + IMX7ULP_PAD_PTB18__QSPIA_DATA1 0x43 /* D1 */ | |
58 | + IMX7ULP_PAD_PTB19__QSPIA_DATA0 0x43 /* D0 */ | |
59 | + IMX7ULP_PAD_PTB5__PTB5 0x20003 | |
60 | + >; | |
61 | + }; | |
62 | + }; | |
63 | +}; | |
64 | + | |
65 | +&lpuart6 { /* console */ | |
66 | + pinctrl-names = "default"; | |
67 | + pinctrl-0 = <&pinctrl_lpuart6>; | |
68 | + status = "okay"; | |
69 | +}; | |
70 | + | |
71 | +&usdhc1 { | |
72 | + pinctrl-names = "default", "sleep"; | |
73 | + pinctrl-0 = <&pinctrl_usdhc1>; | |
74 | + pinctrl-1 = <&pinctrl_usdhc1>; | |
75 | + non-removable; | |
76 | + status = "okay"; | |
77 | +}; | |
78 | + | |
79 | +&qspi1 { | |
80 | + pinctrl-names = "default"; | |
81 | + pinctrl-0 = <&pinctrl_qspi1_1>; | |
82 | + status = "okay"; | |
83 | + | |
84 | + flash0: n25q512ax3@0 { | |
85 | + reg = <0>; | |
86 | + #address-cells = <1>; | |
87 | + #size-cells = <1>; | |
88 | + compatible = "micron,n25q512ax3", "jedec,spi-nor"; | |
89 | + spi-max-frequency = <29000000>; | |
90 | + }; | |
91 | +}; |
arch/arm/dts/imx7ulp-14x14-val.dts
1 | +/* | |
2 | + * Copyright 2016 Freescale Semiconductor, Inc. | |
3 | + * | |
4 | + * This program is free software; you can redistribute it and/or modify | |
5 | + * it under the terms of the GNU General Public License version 2 as | |
6 | + * published by the Free Software Foundation. | |
7 | + */ | |
8 | + | |
9 | +/dts-v1/; | |
10 | + | |
11 | +#include "imx7ulp.dtsi" | |
12 | + | |
13 | +/ { | |
14 | + model = "NXP i.MX7ULP 14x14 val"; | |
15 | + compatible = "fsl,imx7ulp-14x14-val", "fsl,imx7ulp", "Generic DT based system"; | |
16 | + | |
17 | + chosen { | |
18 | + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0000,115200"; | |
19 | + stdout-path = &lpuart4; | |
20 | + }; | |
21 | + | |
22 | + memory { | |
23 | + device_type = "memory"; | |
24 | + reg = <0x60000000 0x40000000>; | |
25 | + }; | |
26 | +}; | |
27 | + | |
28 | +&iomuxc1 { | |
29 | + pinctrl-names = "default"; | |
30 | + pinctrl-0 = <&pinctrl_hog_1>; | |
31 | + | |
32 | + imx7ulp-14x14-val { | |
33 | + pinctrl_hog_1: hoggrp-1 { | |
34 | + fsl,pins = < | |
35 | + IMX7ULP_PAD_PTC10__PTC10 0x30100 | |
36 | + IMX7ULP_PAD_PTC1__PTC1 0x20100 | |
37 | + >; | |
38 | + }; | |
39 | + | |
40 | + pinctrl_lpuart4: lpuart4grp { | |
41 | + fsl,pins = < | |
42 | + IMX7ULP_PAD_PTC3__LPUART4_RX 0x400 | |
43 | + IMX7ULP_PAD_PTC2__LPUART4_TX 0x400 | |
44 | + >; | |
45 | + }; | |
46 | + | |
47 | + pinctrl_usdhc1: usdhc1grp { | |
48 | + fsl,pins = < | |
49 | + IMX7ULP_PAD_PTE3__SDHC1_CMD 0x843 | |
50 | + IMX7ULP_PAD_PTE2__SDHC1_CLK 0x843 | |
51 | + IMX7ULP_PAD_PTE4__SDHC1_D3 0x843 | |
52 | + IMX7ULP_PAD_PTE5__SDHC1_D2 0x843 | |
53 | + IMX7ULP_PAD_PTE0__SDHC1_D1 0x843 | |
54 | + IMX7ULP_PAD_PTE1__SDHC1_D0 0x843 | |
55 | + >; | |
56 | + }; | |
57 | + pinctrl_qspi1_1: qspi1grp_1 { | |
58 | + fsl,pins = < | |
59 | + IMX7ULP_PAD_PTB8__QSPIA_SS0_B 0x43 /* SS0 */ | |
60 | + IMX7ULP_PAD_PTB15__QSPIA_SCLK 0x43 /* SCLK */ | |
61 | + IMX7ULP_PAD_PTB9__QSPIA_DQS 0x43 /* DQS */ | |
62 | + IMX7ULP_PAD_PTB16__QSPIA_DATA3 0x43 /* D3 */ | |
63 | + IMX7ULP_PAD_PTB17__QSPIA_DATA2 0x43 /* D2 */ | |
64 | + IMX7ULP_PAD_PTB18__QSPIA_DATA1 0x43 /* D1 */ | |
65 | + IMX7ULP_PAD_PTB19__QSPIA_DATA0 0x43 /* D0 */ | |
66 | + IMX7ULP_PAD_PTB12__PTB12 0x20003 | |
67 | + >; | |
68 | + }; | |
69 | + }; | |
70 | +}; | |
71 | + | |
72 | +&lpuart4 { /* console */ | |
73 | + pinctrl-names = "default"; | |
74 | + pinctrl-0 = <&pinctrl_lpuart4>; | |
75 | + status = "okay"; | |
76 | +}; | |
77 | + | |
78 | +&usdhc1 { | |
79 | + pinctrl-names = "default", "sleep"; | |
80 | + pinctrl-0 = <&pinctrl_usdhc1>; | |
81 | + pinctrl-1 = <&pinctrl_usdhc1>; | |
82 | + non-removable; | |
83 | + status = "okay"; | |
84 | +}; | |
85 | + | |
86 | +&qspi1 { | |
87 | + pinctrl-names = "default"; | |
88 | + pinctrl-0 = <&pinctrl_qspi1_1>; | |
89 | + status = "okay"; | |
90 | + | |
91 | + flash0: mt35xu512aba@0 { | |
92 | + reg = <0>; | |
93 | + #address-cells = <1>; | |
94 | + #size-cells = <1>; | |
95 | + compatible = "micron,mt35xu512aba", "jedec,spi-nor"; | |
96 | + spi-max-frequency = <29000000>; | |
97 | + }; | |
98 | +}; |
arch/arm/mach-imx/mx7ulp/Kconfig
... | ... | @@ -26,7 +26,16 @@ |
26 | 26 | bool "Support MX7ULP COM board" |
27 | 27 | select MX7ULP |
28 | 28 | select SYS_ARCH_TIMER |
29 | +config TARGET_MX7ULP_10X10_VAL | |
30 | + bool "Support mx7ulp 10x10 validation board" | |
31 | + select SYS_ARCH_TIMER | |
32 | + select MX7ULP | |
29 | 33 | |
34 | +config TARGET_MX7ULP_14X14_VAL | |
35 | + bool "Support mx7ulp 14x14 validation board" | |
36 | + select SYS_ARCH_TIMER | |
37 | + select MX7ULP | |
38 | + | |
30 | 39 | config TARGET_MX7ULP_EVK |
31 | 40 | bool "Support mx7ulp EVK board" |
32 | 41 | select MX7ULP |
... | ... | @@ -35,6 +44,7 @@ |
35 | 44 | endchoice |
36 | 45 | |
37 | 46 | source "board/ea/mx7ulp_com/Kconfig" |
47 | +source "board/freescale/mx7ulp_val/Kconfig" | |
38 | 48 | source "board/freescale/mx7ulp_evk/Kconfig" |
39 | 49 | |
40 | 50 | endif |
board/freescale/mx7ulp_val/Kconfig
board/freescale/mx7ulp_val/Makefile
board/freescale/mx7ulp_val/imximage.cfg
1 | +/* | |
2 | + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. | |
3 | + * | |
4 | + * SPDX-License-Identifier: GPL-2.0+ | |
5 | + * | |
6 | + * Refer docs/README.imxmage for more details about how-to configure | |
7 | + * and create imximage boot image | |
8 | + * | |
9 | + * The syntax is taken as close as possible with the kwbimage | |
10 | + */ | |
11 | + | |
12 | +#define __ASSEMBLY__ | |
13 | +#include <config.h> | |
14 | + | |
15 | +/* image version */ | |
16 | + | |
17 | +IMAGE_VERSION 2 | |
18 | + | |
19 | +/* | |
20 | + * Boot Device : one of | |
21 | + * spi/sd/nand/onenand, qspi/nor | |
22 | + */ | |
23 | + | |
24 | +BOOT_FROM sd | |
25 | + | |
26 | +#ifdef CONFIG_USE_IMXIMG_PLUGIN | |
27 | +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ | |
28 | +PLUGIN board/freescale/mx7ulp_val/plugin.bin 0x2F020000 | |
29 | +#else | |
30 | + | |
31 | +#ifdef CONFIG_IMX_HAB | |
32 | +CSF CONFIG_CSF_SIZE | |
33 | +#endif | |
34 | +/* | |
35 | + * Device Configuration Data (DCD) | |
36 | + * | |
37 | + * Each entry must have the format: | |
38 | + * Addr-type Address Value | |
39 | + * | |
40 | + * where: | |
41 | + * Addr-type register length (1,2 or 4 bytes) | |
42 | + * Address absolute address of the register | |
43 | + * value value to be stored in the register | |
44 | + */ | |
45 | +DATA 4 0x403f00e0 0x00000000 | |
46 | +DATA 4 0x403e0040 0x01000020 | |
47 | +DATA 4 0x403e0500 0x01000000 | |
48 | +DATA 4 0x403e050c 0x80808080 | |
49 | +DATA 4 0x403e0508 0x00160002 | |
50 | +DATA 4 0x403E0510 0x00000000 | |
51 | +DATA 4 0x403E0514 0x00000001 | |
52 | +DATA 4 0x403e0500 0x00000001 | |
53 | +CHECK_BITS_SET 4 0x403e0500 0x01000000 | |
54 | +DATA 4 0x403e050c 0x80808019 | |
55 | +CHECK_BITS_SET 4 0x403e050c 0x00000040 | |
56 | +DATA 4 0x403E0030 0x00000001 | |
57 | +DATA 4 0x403e0040 0x11000020 | |
58 | +DATA 4 0x403f00e0 0x42000000 | |
59 | + | |
60 | +DATA 4 0x40B300AC 0x40000000 | |
61 | + | |
62 | +DATA 4 0x40AD0128 0x00040000 | |
63 | +DATA 4 0x40AD00F8 0x00000000 | |
64 | +DATA 4 0x40AD00D8 0x00000180 | |
65 | +DATA 4 0x40AD0108 0x00000180 | |
66 | +DATA 4 0x40AD0104 0x00000180 | |
67 | +DATA 4 0x40AD0124 0x00010000 | |
68 | +DATA 4 0x40AD0080 0x0000018C | |
69 | +DATA 4 0x40AD0084 0x0000018C | |
70 | +DATA 4 0x40AD0088 0x0000018C | |
71 | +DATA 4 0x40AD008C 0x0000018C | |
72 | + | |
73 | +DATA 4 0x40AD0120 0x00010000 | |
74 | +DATA 4 0x40AD010C 0x00000180 | |
75 | +DATA 4 0x40AD0110 0x00000180 | |
76 | +DATA 4 0x40AD0114 0x00000180 | |
77 | +DATA 4 0x40AD0118 0x00000180 | |
78 | +DATA 4 0x40AD0090 0x00000180 | |
79 | +DATA 4 0x40AD0094 0x00000180 | |
80 | +DATA 4 0x40AD0098 0x00000180 | |
81 | +DATA 4 0x40AD009C 0x00000180 | |
82 | + | |
83 | +DATA 4 0x40AD00E0 0x00040000 | |
84 | +DATA 4 0x40AD00E4 0x00040000 | |
85 | + | |
86 | +DATA 4 0x40AB001C 0x00008000 | |
87 | +DATA 4 0x40AB0800 0xA1390003 | |
88 | +DATA 4 0x40AB085C 0x0D3900A0 | |
89 | +DATA 4 0x40AB0890 0x00400000 | |
90 | + | |
91 | +DATA 4 0x40AB0848 0x39373939 | |
92 | +DATA 4 0x40AB0850 0x2F313D36 | |
93 | +DATA 4 0x40AB081C 0x33333333 | |
94 | +DATA 4 0x40AB0820 0x33333333 | |
95 | +DATA 4 0x40AB0824 0x33333333 | |
96 | +DATA 4 0x40AB0828 0x33333333 | |
97 | + | |
98 | +DATA 4 0x40AB08C0 0x24922492 | |
99 | +DATA 4 0x40AB08B8 0x00000800 | |
100 | + | |
101 | +DATA 4 0x40AB0004 0x00020052 | |
102 | +DATA 4 0x40AB000C 0x424642F3 | |
103 | +DATA 4 0x40AB0010 0x00100A22 | |
104 | +DATA 4 0x40AB0038 0x00120556 | |
105 | +DATA 4 0x40AB0014 0x00C700DA | |
106 | +DATA 4 0x40AB0018 0x00211718 | |
107 | +DATA 4 0x40AB002C 0x0F9F26D2 | |
108 | +DATA 4 0x40AB0030 0x009F0E10 | |
109 | +DATA 4 0x40AB0040 0x0000004F | |
110 | +DATA 4 0x40AB0000 0x84190000 | |
111 | + | |
112 | +DATA 4 0x40AB001C 0x00008010 | |
113 | +DATA 4 0x40AB001C 0x003F8030 | |
114 | +DATA 4 0x40AB001C 0xFF0A8030 | |
115 | +DATA 4 0x40AB001C 0x04028030 | |
116 | +DATA 4 0x40AB001C 0x83018030 | |
117 | +DATA 4 0x40AB001C 0x01038030 | |
118 | + | |
119 | +DATA 4 0x40AB083C 0x20000000 | |
120 | + | |
121 | +DATA 4 0x40AB0020 0x00001800 | |
122 | +DATA 4 0x40AB0800 0xA1310003 | |
123 | +DATA 4 0x40AB001C 0x00000000 | |
124 | + | |
125 | +#endif |
board/freescale/mx7ulp_val/imximage_lpddr2.cfg
1 | +/* | |
2 | + * Copyright 2017 NXP | |
3 | + * | |
4 | + * SPDX-License-Identifier: GPL-2.0+ | |
5 | + * | |
6 | + * Refer docs/README.imxmage for more details about how-to configure | |
7 | + * and create imximage boot image | |
8 | + * | |
9 | + * The syntax is taken as close as possible with the kwbimage | |
10 | + */ | |
11 | + | |
12 | +#define __ASSEMBLY__ | |
13 | +#include <config.h> | |
14 | + | |
15 | +/* image version */ | |
16 | + | |
17 | +IMAGE_VERSION 2 | |
18 | + | |
19 | +/* | |
20 | + * Boot Device : one of | |
21 | + * spi/sd/nand/onenand, qspi/nor | |
22 | + */ | |
23 | + | |
24 | +BOOT_FROM sd | |
25 | + | |
26 | +#ifdef CONFIG_USE_IMXIMG_PLUGIN | |
27 | +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ | |
28 | +PLUGIN board/freescale/mx7ulp_val/plugin.bin 0x2F020000 | |
29 | +#else | |
30 | + | |
31 | +#ifdef CONFIG_IMX_HAB | |
32 | +CSF CONFIG_CSF_SIZE | |
33 | +#endif | |
34 | +/* | |
35 | + * Device Configuration Data (DCD) | |
36 | + * | |
37 | + * Each entry must have the format: | |
38 | + * Addr-type Address Value | |
39 | + * | |
40 | + * where: | |
41 | + * Addr-type register length (1,2 or 4 bytes) | |
42 | + * Address absolute address of the register | |
43 | + * value value to be stored in the register | |
44 | + */ | |
45 | +DATA 4 0x403f00e0 0x00000000 | |
46 | +DATA 4 0x403e0040 0x01000020 | |
47 | +DATA 4 0x403e0500 0x01000000 | |
48 | +DATA 4 0x403e050c 0x80808080 | |
49 | +DATA 4 0x403e0508 0x00160002 | |
50 | +DATA 4 0x403E0510 0x00000000 | |
51 | +DATA 4 0x403E0514 0x00000001 | |
52 | +DATA 4 0x403e0500 0x00000001 | |
53 | +CHECK_BITS_SET 4 0x403e0500 0x01000000 | |
54 | +DATA 4 0x403e050c 0x80808019 | |
55 | +CHECK_BITS_SET 4 0x403e050c 0x00000040 | |
56 | +DATA 4 0x403E0030 0x00000001 | |
57 | +DATA 4 0x403e0040 0x11000020 | |
58 | +DATA 4 0x403f00e0 0x42000000 | |
59 | + | |
60 | +DATA 4 0x40B300AC 0x40000000 | |
61 | + | |
62 | +DATA 4 0x40AD0128 0x00040000 | |
63 | +DATA 4 0x40AD00F8 0x00000000 | |
64 | +DATA 4 0x40AD00D8 0x0000018C | |
65 | +DATA 4 0x40AD0108 0x00000180 | |
66 | +DATA 4 0x40AD0104 0x00000180 | |
67 | +DATA 4 0x40AD0124 0x00010000 | |
68 | +DATA 4 0x40AD0080 0x0000018C | |
69 | +DATA 4 0x40AD0084 0x0000018C | |
70 | +DATA 4 0x40AD0088 0x0000018C | |
71 | +DATA 4 0x40AD008C 0x0000018C | |
72 | + | |
73 | +DATA 4 0x40AD0120 0x00010000 | |
74 | +DATA 4 0x40AD010C 0x00000180 | |
75 | +DATA 4 0x40AD0110 0x00000180 | |
76 | +DATA 4 0x40AD0114 0x00000180 | |
77 | +DATA 4 0x40AD0118 0x00000180 | |
78 | +DATA 4 0x40AD0090 0x00000180 | |
79 | +DATA 4 0x40AD0094 0x00000180 | |
80 | +DATA 4 0x40AD0098 0x00000180 | |
81 | +DATA 4 0x40AD009C 0x00000180 | |
82 | + | |
83 | +DATA 4 0x40AD00E0 0x00040000 | |
84 | +DATA 4 0x40AD00E4 0x00040000 | |
85 | + | |
86 | +DATA 4 0x40AB001C 0x00008000 | |
87 | +DATA 4 0x40AB0800 0xA1390003 | |
88 | +DATA 4 0x40AB085C 0x0D3900A0 | |
89 | +DATA 4 0x40AB0890 0x00400000 | |
90 | + | |
91 | +DATA 4 0x40AB0848 0x40404040 | |
92 | +DATA 4 0x40AB0850 0x40404040 | |
93 | +DATA 4 0x40AB081C 0x33333333 | |
94 | +DATA 4 0x40AB0820 0x33333333 | |
95 | +DATA 4 0x40AB0824 0x33333333 | |
96 | +DATA 4 0x40AB0828 0x33333333 | |
97 | + | |
98 | +DATA 4 0x40AB08C0 0x24922492 | |
99 | +DATA 4 0x40AB08B8 0x00000800 | |
100 | + | |
101 | +DATA 4 0x40AB0004 0x00020052 | |
102 | +DATA 4 0x40AB000C 0x292C42F3 | |
103 | +DATA 4 0x40AB0010 0x00100A22 | |
104 | +DATA 4 0x40AB0038 0x00120556 | |
105 | +DATA 4 0x40AB0014 0x00C700DB | |
106 | +DATA 4 0x40AB0018 0x00211708 | |
107 | +DATA 4 0x40AB002C 0x0F9F26D2 | |
108 | +DATA 4 0x40AB0030 0x009F0E10 | |
109 | +DATA 4 0x40AB0040 0x0000003F | |
110 | +DATA 4 0x40AB0000 0xC3110000 | |
111 | + | |
112 | +DATA 4 0x40AB001C 0x00008010 | |
113 | +DATA 4 0x40AB001C 0x00008018 | |
114 | +DATA 4 0x40AB001C 0x003F8030 | |
115 | +DATA 4 0x40AB001C 0x003F8038 | |
116 | +DATA 4 0x40AB001C 0xFF0A8030 | |
117 | +DATA 4 0x40AB001C 0xFF0A8038 | |
118 | +DATA 4 0x40AB001C 0x04028030 | |
119 | +DATA 4 0x40AB001C 0x04028038 | |
120 | +DATA 4 0x40AB001C 0x82018030 | |
121 | +DATA 4 0x40AB001C 0x82018038 | |
122 | +DATA 4 0x40AB001C 0x01038030 | |
123 | +DATA 4 0x40AB001C 0x01038038 | |
124 | + | |
125 | +DATA 4 0x40AB083C 0x20000000 | |
126 | + | |
127 | +DATA 4 0x40AB0020 0x00001800 | |
128 | +DATA 4 0x40AB0800 0xA1390003 | |
129 | +DATA 4 0x40AB0004 0x00020052 | |
130 | +DATA 4 0x40AB0404 0x00011006 | |
131 | +DATA 4 0x40AB001C 0x00000000 | |
132 | + | |
133 | +#endif |
board/freescale/mx7ulp_val/mx7ulp_val.c
1 | +/* | |
2 | + * Copyright (C) 2016 Freescale Semiconductor, Inc. | |
3 | + * Copyright 2017 NXP | |
4 | + * | |
5 | + * SPDX-License-Identifier: GPL-2.0+ | |
6 | + */ | |
7 | + | |
8 | +#include <asm/io.h> | |
9 | +#include <asm/arch/clock.h> | |
10 | +#include <asm/arch/sys_proto.h> | |
11 | +#include <asm/arch/mx7ulp-pins.h> | |
12 | +#include <asm/arch/iomux.h> | |
13 | +#include <asm/gpio.h> | |
14 | +#include <usb.h> | |
15 | + | |
16 | +DECLARE_GLOBAL_DATA_PTR; | |
17 | + | |
18 | +#define UART_PAD_CTRL (PAD_CTL_PUS_UP) | |
19 | + | |
20 | +#define GPIO_PAD_CTRL (PAD_CTL_OBE_ENABLE | PAD_CTL_IBE_ENABLE) | |
21 | + | |
22 | +#define OTG_ID_GPIO_PAD_CTRL (PAD_CTL_IBE_ENABLE) | |
23 | +#define OTG_PWR_GPIO_PAD_CTRL (PAD_CTL_OBE_ENABLE) | |
24 | + | |
25 | +#define QSPI_PAD_CTRL1 (PAD_CTL_PUS_UP | PAD_CTL_DSE) | |
26 | + | |
27 | +#define QSPI_PAD_CTRL0 (PAD_CTL_PUS_UP | PAD_CTL_DSE \ | |
28 | + | PAD_CTL_OBE_ENABLE) | |
29 | + | |
30 | + | |
31 | +int dram_init(void) | |
32 | +{ | |
33 | + gd->ram_size = PHYS_SDRAM_SIZE; | |
34 | + | |
35 | + return 0; | |
36 | +} | |
37 | + | |
38 | +#ifdef CONFIG_TARGET_MX7ULP_10X10_VAL | |
39 | +/* PTF11 and PTF10 also can mux to LPUART6 on 10x10 validation, depends on rework*/ | |
40 | +static iomux_cfg_t const lpuart6_pads[] = { | |
41 | + MX7ULP_PAD_PTE11__LPUART6_RX | MUX_PAD_CTRL(UART_PAD_CTRL), | |
42 | + MX7ULP_PAD_PTE10__LPUART6_TX | MUX_PAD_CTRL(UART_PAD_CTRL), | |
43 | +}; | |
44 | +#else | |
45 | +static iomux_cfg_t const lpuart4_pads[] = { | |
46 | + MX7ULP_PAD_PTC3__LPUART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL), | |
47 | + MX7ULP_PAD_PTC2__LPUART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL), | |
48 | +}; | |
49 | +#endif | |
50 | + | |
51 | +static void setup_iomux_uart(void) | |
52 | +{ | |
53 | +#ifdef CONFIG_TARGET_MX7ULP_10X10_VAL | |
54 | + mx7ulp_iomux_setup_multiple_pads(lpuart6_pads, ARRAY_SIZE(lpuart6_pads)); | |
55 | +#else | |
56 | + mx7ulp_iomux_setup_multiple_pads(lpuart4_pads, ARRAY_SIZE(lpuart4_pads)); | |
57 | +#endif | |
58 | +} | |
59 | + | |
60 | +#ifdef CONFIG_USB_EHCI_MX7 | |
61 | + | |
62 | +static iomux_cfg_t const usb_otg1_pads[] = { | |
63 | + | |
64 | +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2 | |
65 | + MX7ULP_PAD_PTC0__PTC0 | MUX_PAD_CTRL(OTG_ID_GPIO_PAD_CTRL), /* gpio for otgid */ | |
66 | + MX7ULP_PAD_PTC1__PTC1 | MUX_PAD_CTRL(OTG_PWR_GPIO_PAD_CTRL), /* gpio for power en */ | |
67 | +#else | |
68 | + /*Need rework for ID and PWR_EN pins on 14x14 ARM2*/ | |
69 | + MX7ULP_PAD_PTC18__PTC18 | MUX_PAD_CTRL(OTG_ID_GPIO_PAD_CTRL), /* gpio for otgid */ | |
70 | + MX7ULP_PAD_PTA31__PTA31 | MUX_PAD_CTRL(OTG_PWR_GPIO_PAD_CTRL), /* gpio for power en */ | |
71 | +#endif | |
72 | +}; | |
73 | + | |
74 | +#ifdef CONFIG_TARGET_MX7ULP_10X10_VAL | |
75 | +#define OTG0_ID_GPIO IMX_GPIO_NR(3, 0) | |
76 | +#define OTG0_PWR_EN IMX_GPIO_NR(3, 1) | |
77 | +#else | |
78 | +#define OTG0_ID_GPIO IMX_GPIO_NR(3, 18) | |
79 | +#define OTG0_PWR_EN IMX_GPIO_NR(1, 31) | |
80 | +#endif | |
81 | +static void setup_usb(void) | |
82 | +{ | |
83 | + mx7ulp_iomux_setup_multiple_pads(usb_otg1_pads, | |
84 | + ARRAY_SIZE(usb_otg1_pads)); | |
85 | + | |
86 | + gpio_request(OTG0_ID_GPIO, "otg_id"); | |
87 | + gpio_direction_input(OTG0_ID_GPIO); | |
88 | +} | |
89 | + | |
90 | +/*Needs to override the ehci power if controlled by GPIO */ | |
91 | +int board_ehci_power(int port, int on) | |
92 | +{ | |
93 | + switch (port) { | |
94 | + case 0: | |
95 | + if (on) | |
96 | + gpio_direction_output(OTG0_PWR_EN, 1); | |
97 | + else | |
98 | + gpio_direction_output(OTG0_PWR_EN, 0); | |
99 | + break; | |
100 | + default: | |
101 | + printf("MXC USB port %d not yet supported\n", port); | |
102 | + return -EINVAL; | |
103 | + } | |
104 | + | |
105 | + return 0; | |
106 | +} | |
107 | + | |
108 | +int board_usb_phy_mode(int port) | |
109 | +{ | |
110 | + int ret = 0; | |
111 | + | |
112 | + if (port == 0) { | |
113 | + ret = gpio_get_value(OTG0_ID_GPIO); | |
114 | + | |
115 | + if (ret) | |
116 | + return USB_INIT_DEVICE; | |
117 | + else | |
118 | + return USB_INIT_HOST; | |
119 | + } | |
120 | + | |
121 | + return USB_INIT_HOST; | |
122 | +} | |
123 | + | |
124 | +#endif | |
125 | + | |
126 | + | |
127 | +int board_early_init_f(void) | |
128 | +{ | |
129 | + setup_iomux_uart(); | |
130 | + | |
131 | + return 0; | |
132 | +} | |
133 | + | |
134 | +#ifdef CONFIG_FSL_QSPI | |
135 | +#ifdef CONFIG_TARGET_MX7ULP_10X10_VAL | |
136 | +static iomux_cfg_t const quadspi_pads[] = { | |
137 | + MX7ULP_PAD_PTB8__QSPIA_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL0), | |
138 | + MX7ULP_PAD_PTB14__QSPIA_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL0), | |
139 | + MX7ULP_PAD_PTB15__QSPIA_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL0), | |
140 | + MX7ULP_PAD_PTB16__QSPIA_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), | |
141 | + MX7ULP_PAD_PTB17__QSPIA_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), | |
142 | + MX7ULP_PAD_PTB18__QSPIA_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), | |
143 | + MX7ULP_PAD_PTB19__QSPIA_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), | |
144 | + | |
145 | + MX7ULP_PAD_PTB5__PTB5 | MUX_PAD_CTRL(GPIO_PAD_CTRL), | |
146 | +}; | |
147 | + | |
148 | +#define QSPI_RST_GPIO IMX_GPIO_NR(2, 5) | |
149 | +#else | |
150 | +/* MT35XU512ABA supports 8 bits I/O, since our driver only support 4, so mux 4 data pins*/ | |
151 | +static iomux_cfg_t const quadspi_pads[] = { | |
152 | + MX7ULP_PAD_PTB8__QSPIA_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL0), | |
153 | + MX7ULP_PAD_PTB9__QSPIA_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1), | |
154 | + MX7ULP_PAD_PTB15__QSPIA_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL0), | |
155 | + MX7ULP_PAD_PTB16__QSPIA_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), | |
156 | + MX7ULP_PAD_PTB17__QSPIA_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), | |
157 | + MX7ULP_PAD_PTB18__QSPIA_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), | |
158 | + MX7ULP_PAD_PTB19__QSPIA_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), | |
159 | + | |
160 | + MX7ULP_PAD_PTB12__PTB12 | MUX_PAD_CTRL(GPIO_PAD_CTRL), | |
161 | +}; | |
162 | + | |
163 | +#define QSPI_RST_GPIO IMX_GPIO_NR(2, 12) | |
164 | + | |
165 | +#endif | |
166 | +int board_qspi_init(void) | |
167 | +{ | |
168 | + u32 val; | |
169 | + mx7ulp_iomux_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads)); | |
170 | + /* enable clock */ | |
171 | + val = readl(PCC1_RBASE + 0x94); | |
172 | + | |
173 | + if (!(val & 0x20000000)) { | |
174 | + writel(0x03000003, (PCC1_RBASE + 0x94)); | |
175 | + writel(0x43000003, (PCC1_RBASE + 0x94)); | |
176 | + } | |
177 | + | |
178 | + /* Enable QSPI as a wakeup source on B0 */ | |
179 | + if (soc_rev() >= CHIP_REV_2_0) | |
180 | + setbits_le32(SIM0_RBASE + WKPU_WAKEUP_EN, WKPU_QSPI_CHANNEL); | |
181 | + | |
182 | + gpio_request(QSPI_RST_GPIO, "qspi_reset"); | |
183 | + gpio_direction_output(QSPI_RST_GPIO, 0); | |
184 | + mdelay(10); | |
185 | + gpio_direction_output(QSPI_RST_GPIO, 1); | |
186 | + return 0; | |
187 | +} | |
188 | +#endif | |
189 | + | |
190 | +int board_init(void) | |
191 | +{ | |
192 | + /* address of boot parameters */ | |
193 | + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; | |
194 | + | |
195 | +#ifdef CONFIG_USB_EHCI_MX7 | |
196 | + setup_usb(); | |
197 | +#endif | |
198 | + | |
199 | +#ifdef CONFIG_FSL_QSPI | |
200 | + board_qspi_init(); | |
201 | +#endif | |
202 | + | |
203 | + return 0; | |
204 | +} | |
205 | + | |
206 | +int board_late_init(void) | |
207 | +{ | |
208 | + return 0; | |
209 | +} | |
210 | + | |
211 | +int checkboard(void) | |
212 | +{ | |
213 | +#ifdef CONFIG_TARGET_MX7ULP_10X10_VAL | |
214 | + printf("Board: i.MX7ULP 10x10 Validation board\n"); | |
215 | +#else | |
216 | + printf("Board: i.MX7ULP 14x14 Validation board\n"); | |
217 | +#endif | |
218 | + return 0; | |
219 | +} |
board/freescale/mx7ulp_val/plugin.S
1 | +/* | |
2 | + * Copyright (C) 2016 Freescale Semiconductor, Inc. | |
3 | + * Copyright 2017 NXP | |
4 | + * | |
5 | + * SPDX-License-Identifier: GPL-2.0+ | |
6 | + */ | |
7 | + | |
8 | +#include <config.h> | |
9 | + | |
10 | +.macro imx7ulp_ddr_freq_decrease | |
11 | + ldr r2, =0x403f0000 | |
12 | + ldr r3, =0x00000000 | |
13 | + str r3, [r2, #0xe0] | |
14 | + | |
15 | + ldr r2, =0x403e0000 | |
16 | + ldr r3, =0x01000020 | |
17 | + str r3, [r2, #0x40] | |
18 | + ldr r3, =0x01000000 | |
19 | + str r3, [r2, #0x500] | |
20 | + | |
21 | + ldr r3, =0x80808080 | |
22 | + str r3, [r2, #0x50c] | |
23 | + ldr r3, =0x00160002 | |
24 | + str r3, [r2, #0x508] | |
25 | + ldr r3, =0x00000000 | |
26 | + str r3, [r2, #0x510] | |
27 | + ldr r3, =0x00000001 | |
28 | + str r3, [r2, #0x514] | |
29 | + ldr r3, =0x00000001 | |
30 | + str r3, [r2, #0x500] | |
31 | + | |
32 | + ldr r3, =0x01000000 | |
33 | +wait1: | |
34 | + ldr r4, [r2, #0x500] | |
35 | + and r4, r3 | |
36 | + cmp r4, r3 | |
37 | + bne wait1 | |
38 | + | |
39 | + ldr r3, =0x80808019 | |
40 | + str r3, [r2, #0x50c] | |
41 | + | |
42 | + ldr r3, =0x00000040 | |
43 | +wait2: | |
44 | + ldr r4, [r2, #0x50c] | |
45 | + and r4, r3 | |
46 | + cmp r4, r3 | |
47 | + bne wait2 | |
48 | + | |
49 | + ldr r3, =0x00000001 | |
50 | + str r3, [r2, #0x30] | |
51 | + ldr r3, =0x11000020 | |
52 | + str r3, [r2, #0x40] | |
53 | + | |
54 | + ldr r2, =0x403f0000 | |
55 | + ldr r3, =0x42000000 | |
56 | + str r3, [r2, #0xe0] | |
57 | + | |
58 | +.endm | |
59 | + | |
60 | +.macro imx7ulp_arm2_lpddr3_setting | |
61 | + | |
62 | + imx7ulp_ddr_freq_decrease | |
63 | + | |
64 | + /* Enable MMDC PCC clock */ | |
65 | + ldr r2, =0x40b30000 | |
66 | + ldr r3, =0x40000000 | |
67 | + str r3, [r2, #0xac] | |
68 | + | |
69 | + /* Configure DDR pad */ | |
70 | + ldr r0, =0x40ad0000 | |
71 | + ldr r1, =0x00040000 | |
72 | + str r1, [r0, #0x128] | |
73 | + ldr r1, =0x0 | |
74 | + str r1, [r0, #0xf8] | |
75 | + ldr r1, =0x00000180 | |
76 | + str r1, [r0, #0xd8] | |
77 | + ldr r1, =0x00000180 | |
78 | + str r1, [r0, #0x108] | |
79 | + ldr r1, =0x00000180 | |
80 | + str r1, [r0, #0x104] | |
81 | + ldr r1, =0x00010000 | |
82 | + str r1, [r0, #0x124] | |
83 | + ldr r1, =0x0000018C | |
84 | + str r1, [r0, #0x80] | |
85 | + ldr r1, =0x0000018C | |
86 | + str r1, [r0, #0x84] | |
87 | + ldr r1, =0x0000018C | |
88 | + str r1, [r0, #0x88] | |
89 | + ldr r1, =0x0000018C | |
90 | + str r1, [r0, #0x8c] | |
91 | + | |
92 | + ldr r1, =0x00010000 | |
93 | + str r1, [r0, #0x120] | |
94 | + ldr r1, =0x00000180 | |
95 | + str r1, [r0, #0x10c] | |
96 | + ldr r1, =0x00000180 | |
97 | + str r1, [r0, #0x110] | |
98 | + ldr r1, =0x00000180 | |
99 | + str r1, [r0, #0x114] | |
100 | + ldr r1, =0x00000180 | |
101 | + str r1, [r0, #0x118] | |
102 | + ldr r1, =0x00000180 | |
103 | + str r1, [r0, #0x90] | |
104 | + ldr r1, =0x00000180 | |
105 | + str r1, [r0, #0x94] | |
106 | + ldr r1, =0x00000180 | |
107 | + str r1, [r0, #0x98] | |
108 | + ldr r1, =0x00000180 | |
109 | + str r1, [r0, #0x9c] | |
110 | + ldr r1, =0x00040000 | |
111 | + str r1, [r0, #0xe0] | |
112 | + ldr r1, =0x00040000 | |
113 | + str r1, [r0, #0xe4] | |
114 | + | |
115 | + ldr r0, =0x40ab0000 | |
116 | + ldr r1, =0x00008000 | |
117 | + str r1, [r0, #0x1c] | |
118 | + ldr r1, =0xA1390003 | |
119 | + str r1, [r0, #0x800] | |
120 | + ldr r1, =0x0D3900A0 | |
121 | + str r1, [r0, #0x85c] | |
122 | + ldr r1, =0x00400000 | |
123 | + str r1, [r0, #0x890] | |
124 | + | |
125 | + ldr r1, =0x39373939 | |
126 | + str r1, [r0, #0x848] | |
127 | + ldr r1, =0x2F313D36 | |
128 | + str r1, [r0, #0x850] | |
129 | + ldr r1, =0x33333333 | |
130 | + str r1, [r0, #0x81c] | |
131 | + ldr r1, =0x33333333 | |
132 | + str r1, [r0, #0x820] | |
133 | + ldr r1, =0x33333333 | |
134 | + str r1, [r0, #0x824] | |
135 | + ldr r1, =0x33333333 | |
136 | + str r1, [r0, #0x828] | |
137 | + | |
138 | + ldr r1, =0x24922492 | |
139 | + str r1, [r0, #0x8c0] | |
140 | + ldr r1, =0x00000800 | |
141 | + str r1, [r0, #0x8b8] | |
142 | + | |
143 | + ldr r1, =0x00020052 | |
144 | + str r1, [r0, #0x4] | |
145 | + ldr r1, =0x424642F3 | |
146 | + str r1, [r0, #0xc] | |
147 | + ldr r1, =0x00100A22 | |
148 | + str r1, [r0, #0x10] | |
149 | + ldr r1, =0x00120556 | |
150 | + str r1, [r0, #0x38] | |
151 | + ldr r1, =0x00C700DA | |
152 | + str r1, [r0, #0x14] | |
153 | + ldr r1, =0x00211718 | |
154 | + str r1, [r0, #0x18] | |
155 | + | |
156 | + ldr r1, =0x0F9F26D2 | |
157 | + str r1, [r0, #0x2c] | |
158 | + ldr r1, =0x009F0E10 | |
159 | + str r1, [r0, #0x30] | |
160 | + ldr r1, =0x0000004F | |
161 | + str r1, [r0, #0x40] | |
162 | + ldr r1, =0x84190000 | |
163 | + str r1, [r0, #0x0] | |
164 | + | |
165 | + ldr r1, =0x00008010 | |
166 | + str r1, [r0, #0x1c] | |
167 | + ldr r1, =0x003F8030 | |
168 | + str r1, [r0, #0x1c] | |
169 | + ldr r1, =0xFF0A8030 | |
170 | + str r1, [r0, #0x1c] | |
171 | + ldr r1, =0x04028030 | |
172 | + str r1, [r0, #0x1c] | |
173 | + ldr r1, =0x83018030 | |
174 | + str r1, [r0, #0x1c] | |
175 | + ldr r1, =0x01038030 | |
176 | + str r1, [r0, #0x1c] | |
177 | + | |
178 | + ldr r1, =0x20000000 | |
179 | + str r1, [r0, #0x83c] | |
180 | + | |
181 | + ldr r1, =0x00001800 | |
182 | + str r1, [r0, #0x20] | |
183 | + ldr r1, =0xA1310003 | |
184 | + str r1, [r0, #0x800] | |
185 | + ldr r1, =0x00000000 | |
186 | + str r1, [r0, #0x1c] | |
187 | + | |
188 | +.endm | |
189 | + | |
190 | +.macro imx7ulp_arm2_lpddr2_setting | |
191 | + | |
192 | + imx7ulp_ddr_freq_decrease | |
193 | + | |
194 | + /* Enable MMDC PCC clock */ | |
195 | + ldr r2, =0x40b30000 | |
196 | + ldr r3, =0x40000000 | |
197 | + str r3, [r2, #0xac] | |
198 | + | |
199 | + /* Configure DDR pad */ | |
200 | + ldr r0, =0x40ad0000 | |
201 | + ldr r1, =0x00040000 | |
202 | + str r1, [r0, #0x128] | |
203 | + ldr r1, =0x0 | |
204 | + str r1, [r0, #0xf8] | |
205 | + ldr r1, =0x0000018C | |
206 | + str r1, [r0, #0xd8] | |
207 | + ldr r1, =0x00000180 | |
208 | + str r1, [r0, #0x108] | |
209 | + ldr r1, =0x00000180 | |
210 | + str r1, [r0, #0x104] | |
211 | + ldr r1, =0x00010000 | |
212 | + str r1, [r0, #0x124] | |
213 | + ldr r1, =0x0000018C | |
214 | + str r1, [r0, #0x80] | |
215 | + ldr r1, =0x0000018C | |
216 | + str r1, [r0, #0x84] | |
217 | + ldr r1, =0x0000018C | |
218 | + str r1, [r0, #0x88] | |
219 | + ldr r1, =0x0000018C | |
220 | + str r1, [r0, #0x8c] | |
221 | + | |
222 | + ldr r1, =0x00010000 | |
223 | + str r1, [r0, #0x120] | |
224 | + ldr r1, =0x00000180 | |
225 | + str r1, [r0, #0x10c] | |
226 | + ldr r1, =0x00000180 | |
227 | + str r1, [r0, #0x110] | |
228 | + ldr r1, =0x00000180 | |
229 | + str r1, [r0, #0x114] | |
230 | + ldr r1, =0x00000180 | |
231 | + str r1, [r0, #0x118] | |
232 | + ldr r1, =0x00000180 | |
233 | + str r1, [r0, #0x90] | |
234 | + ldr r1, =0x00000180 | |
235 | + str r1, [r0, #0x94] | |
236 | + ldr r1, =0x00000180 | |
237 | + str r1, [r0, #0x98] | |
238 | + ldr r1, =0x00000180 | |
239 | + str r1, [r0, #0x9c] | |
240 | + ldr r1, =0x00040000 | |
241 | + str r1, [r0, #0xe0] | |
242 | + ldr r1, =0x00040000 | |
243 | + str r1, [r0, #0xe4] | |
244 | + | |
245 | + ldr r0, =0x40ab0000 | |
246 | + ldr r1, =0x00008000 | |
247 | + str r1, [r0, #0x1c] | |
248 | + ldr r1, =0xA1390003 | |
249 | + str r1, [r0, #0x800] | |
250 | + ldr r1, =0x0D3900A0 | |
251 | + str r1, [r0, #0x85c] | |
252 | + ldr r1, =0x00400000 | |
253 | + str r1, [r0, #0x890] | |
254 | + | |
255 | + ldr r1, =0x40404040 | |
256 | + str r1, [r0, #0x848] | |
257 | + ldr r1, =0x40404040 | |
258 | + str r1, [r0, #0x850] | |
259 | + ldr r1, =0x33333333 | |
260 | + str r1, [r0, #0x81c] | |
261 | + ldr r1, =0x33333333 | |
262 | + str r1, [r0, #0x820] | |
263 | + ldr r1, =0x33333333 | |
264 | + str r1, [r0, #0x824] | |
265 | + ldr r1, =0x33333333 | |
266 | + str r1, [r0, #0x828] | |
267 | + | |
268 | + ldr r1, =0x24922492 | |
269 | + str r1, [r0, #0x8c0] | |
270 | + ldr r1, =0x00000800 | |
271 | + str r1, [r0, #0x8b8] | |
272 | + | |
273 | + ldr r1, =0x00020052 | |
274 | + str r1, [r0, #0x4] | |
275 | + ldr r1, =0x292C42F3 | |
276 | + str r1, [r0, #0xc] | |
277 | + ldr r1, =0x00100A22 | |
278 | + str r1, [r0, #0x10] | |
279 | + ldr r1, =0x00120556 | |
280 | + str r1, [r0, #0x38] | |
281 | + ldr r1, =0x00C700DB | |
282 | + str r1, [r0, #0x14] | |
283 | + ldr r1, =0x00211708 | |
284 | + str r1, [r0, #0x18] | |
285 | + | |
286 | + ldr r1, =0x0F9F26D2 | |
287 | + str r1, [r0, #0x2c] | |
288 | + ldr r1, =0x009F0E10 | |
289 | + str r1, [r0, #0x30] | |
290 | + ldr r1, =0x0000003F | |
291 | + str r1, [r0, #0x40] | |
292 | + ldr r1, =0xC3110000 | |
293 | + str r1, [r0, #0x0] | |
294 | + | |
295 | + ldr r1, =0x00008010 | |
296 | + str r1, [r0, #0x1c] | |
297 | + ldr r1, =0x00008018 | |
298 | + str r1, [r0, #0x1c] | |
299 | + ldr r1, =0x003F8030 | |
300 | + str r1, [r0, #0x1c] | |
301 | + ldr r1, =0x003F8038 | |
302 | + str r1, [r0, #0x1c] | |
303 | + ldr r1, =0xFF0A8030 | |
304 | + str r1, [r0, #0x1c] | |
305 | + ldr r1, =0xFF0A8038 | |
306 | + str r1, [r0, #0x1c] | |
307 | + ldr r1, =0x04028030 | |
308 | + str r1, [r0, #0x1c] | |
309 | + ldr r1, =0x04028038 | |
310 | + str r1, [r0, #0x1c] | |
311 | + ldr r1, =0x82018030 | |
312 | + str r1, [r0, #0x1c] | |
313 | + ldr r1, =0x82018038 | |
314 | + str r1, [r0, #0x1c] | |
315 | + ldr r1, =0x01038030 | |
316 | + str r1, [r0, #0x1c] | |
317 | + ldr r1, =0x01038038 | |
318 | + str r1, [r0, #0x1c] | |
319 | + | |
320 | + ldr r1, =0x20000000 | |
321 | + str r1, [r0, #0x83c] | |
322 | + | |
323 | + ldr r1, =0x00001800 | |
324 | + str r1, [r0, #0x20] | |
325 | + ldr r1, =0xA1390003 | |
326 | + str r1, [r0, #0x800] | |
327 | + ldr r1, =0x00020052 | |
328 | + str r1, [r0, #0x4] | |
329 | + ldr r1, =0x00011006 | |
330 | + str r1, [r0, #0x404] | |
331 | + ldr r1, =0x00000000 | |
332 | + str r1, [r0, #0x1c] | |
333 | + | |
334 | +.endm | |
335 | + | |
336 | + | |
337 | +.macro imx7ulp_clock_gating | |
338 | +.endm | |
339 | + | |
340 | +.macro imx7ulp_qos_setting | |
341 | +.endm | |
342 | + | |
343 | +.macro imx7ulp_ddr_setting | |
344 | +#if defined (CONFIG_TARGET_MX7ULP_10X10_VAL) | |
345 | + imx7ulp_arm2_lpddr2_setting | |
346 | +#else | |
347 | + imx7ulp_arm2_lpddr3_setting | |
348 | +#endif | |
349 | +.endm | |
350 | + | |
351 | +/* include the common plugin code here */ | |
352 | +#include <asm/arch/mx7ulp_plugin.S> |
configs/mx7ulp_10x10_val_defconfig
1 | +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_val/imximage_lpddr2.cfg" | |
2 | +CONFIG_ARM=y | |
3 | +CONFIG_ARCH_MX7ULP=y | |
4 | +CONFIG_SYS_TEXT_BASE=0x67800000 | |
5 | +CONFIG_ENV_SIZE=0x2000 | |
6 | +CONFIG_ENV_OFFSET=0xE0000 | |
7 | +CONFIG_DM_GPIO=y | |
8 | +CONFIG_TARGET_MX7ULP_10X10_VAL=y | |
9 | +CONFIG_NR_DRAM_BANKS=1 | |
10 | +CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-10x10-val" | |
11 | +CONFIG_DEFAULT_FDT_FILE="imx7ulp-10x10-val.dtb" | |
12 | +CONFIG_BOUNCE_BUFFER=y | |
13 | +CONFIG_BOARD_LATE_INIT=y | |
14 | +CONFIG_BOARD_EARLY_INIT_F=y | |
15 | +CONFIG_HUSH_PARSER=y | |
16 | +CONFIG_CMD_BOOTZ=y | |
17 | +CONFIG_CMD_MEMTEST=y | |
18 | +CONFIG_CMD_FUSE=y | |
19 | +CONFIG_CMD_GPIO=y | |
20 | +CONFIG_CMD_I2C=y | |
21 | +CONFIG_CMD_MMC=y | |
22 | +CONFIG_CMD_FAT=y | |
23 | +CONFIG_CMD_PING=y | |
24 | +CONFIG_CMD_DHCP=y | |
25 | +CONFIG_OF_CONTROL=y | |
26 | +CONFIG_ENV_IS_IN_MMC=y | |
27 | +CONFIG_SYS_RELOC_GD_ENV_ADDR=y | |
28 | +CONFIG_DM=y | |
29 | +CONFIG_IMX_RGPIO2P=y | |
30 | +# CONFIG_MXC_GPIO is not set | |
31 | +CONFIG_DM_I2C=y | |
32 | +CONFIG_SYS_I2C_IMX_LPI2C=y | |
33 | +CONFIG_DM_MMC=y | |
34 | +CONFIG_SUPPORT_EMMC_BOOT=y | |
35 | +CONFIG_FSL_USDHC=y | |
36 | +CONFIG_MTD=y | |
37 | +CONFIG_PINCTRL=y | |
38 | +CONFIG_PINCTRL_IMX7ULP=y | |
39 | +CONFIG_DM_REGULATOR=y | |
40 | +CONFIG_DM_REGULATOR_FIXED=y | |
41 | +CONFIG_DM_REGULATOR_GPIO=y | |
42 | +CONFIG_DM_SERIAL=y | |
43 | +CONFIG_FSL_LPUART=y | |
44 | +CONFIG_CMD_SF=y | |
45 | +CONFIG_FSL_QSPI=y | |
46 | +CONFIG_SPI=y | |
47 | +CONFIG_DM_SPI=y | |
48 | +CONFIG_DM_SPI_FLASH=y | |
49 | +CONFIG_SPI_FLASH=y | |
50 | +CONFIG_SPI_FLASH_STMICRO=y | |
51 | +CONFIG_SF_DEFAULT_BUS=0 | |
52 | +CONFIG_SF_DEFAULT_CS=0 | |
53 | +CONFIG_SF_DEFAULT_SPEED=40000000 | |
54 | +CONFIG_SF_DEFAULT_MODE=0 | |
55 | +CONFIG_ULP_WATCHDOG=y | |
56 | +CONFIG_CMD_USB=y | |
57 | +CONFIG_USB=y | |
58 | +CONFIG_DM_USB=y | |
59 | +CONFIG_USB_EHCI_HCD=y | |
60 | +CONFIG_MXC_USB_OTG_HACTIVE=y | |
61 | +CONFIG_USB_STORAGE=y | |
62 | +CONFIG_CMD_USB_MASS_STORAGE=y | |
63 | +CONFIG_USB_HOST_ETHER=y | |
64 | +CONFIG_USB_ETHER_ASIX=y | |
65 | +CONFIG_USB_ETHER_RTL8152=y | |
66 | +CONFIG_DM_ETH=y | |
67 | + | |
68 | +CONFIG_USB_GADGET=y | |
69 | +CONFIG_USB_GADGET_DOWNLOAD=y | |
70 | +CONFIG_USB_GADGET_MANUFACTURER="FSL" | |
71 | +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | |
72 | +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | |
73 | +CONFIG_CI_UDC=y |
configs/mx7ulp_14x14_val_defconfig
1 | +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_val/imximage.cfg" | |
2 | +CONFIG_ARM=y | |
3 | +CONFIG_ARCH_MX7ULP=y | |
4 | +CONFIG_SYS_TEXT_BASE=0x67800000 | |
5 | +CONFIG_ENV_SIZE=0x2000 | |
6 | +CONFIG_ENV_OFFSET=0xE0000 | |
7 | +CONFIG_DM_GPIO=y | |
8 | +CONFIG_TARGET_MX7ULP_14X14_VAL=y | |
9 | +CONFIG_NR_DRAM_BANKS=1 | |
10 | +CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-14x14-val" | |
11 | +CONFIG_DEFAULT_FDT_FILE="imx7ulp-14x14-val.dtb" | |
12 | +CONFIG_BOUNCE_BUFFER=y | |
13 | +CONFIG_BOARD_LATE_INIT=y | |
14 | +CONFIG_BOARD_EARLY_INIT_F=y | |
15 | +CONFIG_HUSH_PARSER=y | |
16 | +CONFIG_CMD_BOOTZ=y | |
17 | +CONFIG_CMD_MEMTEST=y | |
18 | +CONFIG_CMD_FUSE=y | |
19 | +CONFIG_CMD_GPIO=y | |
20 | +CONFIG_CMD_I2C=y | |
21 | +CONFIG_CMD_MMC=y | |
22 | +CONFIG_CMD_FAT=y | |
23 | +CONFIG_CMD_PING=y | |
24 | +CONFIG_CMD_DHCP=y | |
25 | +CONFIG_OF_CONTROL=y | |
26 | +CONFIG_ENV_IS_IN_MMC=y | |
27 | +CONFIG_SYS_RELOC_GD_ENV_ADDR=y | |
28 | +CONFIG_DM=y | |
29 | +CONFIG_IMX_RGPIO2P=y | |
30 | +# CONFIG_MXC_GPIO is not set | |
31 | +CONFIG_DM_I2C=y | |
32 | +CONFIG_SYS_I2C_IMX_LPI2C=y | |
33 | +CONFIG_DM_MMC=y | |
34 | +CONFIG_SUPPORT_EMMC_BOOT=y | |
35 | +CONFIG_FSL_USDHC=y | |
36 | +CONFIG_MTD=y | |
37 | +CONFIG_PINCTRL=y | |
38 | +CONFIG_PINCTRL_IMX7ULP=y | |
39 | +CONFIG_DM_REGULATOR=y | |
40 | +CONFIG_DM_REGULATOR_FIXED=y | |
41 | +CONFIG_DM_REGULATOR_GPIO=y | |
42 | +CONFIG_DM_SERIAL=y | |
43 | +CONFIG_FSL_LPUART=y | |
44 | +CONFIG_CMD_SF=y | |
45 | +CONFIG_FSL_QSPI=y | |
46 | +CONFIG_SPI=y | |
47 | +CONFIG_DM_SPI=y | |
48 | +CONFIG_DM_SPI_FLASH=y | |
49 | +CONFIG_SPI_FLASH=y | |
50 | +CONFIG_SPI_FLASH_STMICRO=y | |
51 | +CONFIG_SF_DEFAULT_BUS=0 | |
52 | +CONFIG_SF_DEFAULT_CS=0 | |
53 | +CONFIG_SF_DEFAULT_SPEED=40000000 | |
54 | +CONFIG_SF_DEFAULT_MODE=0 | |
55 | +CONFIG_ULP_WATCHDOG=y | |
56 | +CONFIG_CMD_USB=y | |
57 | +CONFIG_USB=y | |
58 | +CONFIG_DM_USB=y | |
59 | +CONFIG_USB_EHCI_HCD=y | |
60 | +CONFIG_MXC_USB_OTG_HACTIVE=y | |
61 | +CONFIG_USB_STORAGE=y | |
62 | +CONFIG_CMD_USB_MASS_STORAGE=y | |
63 | +CONFIG_USB_HOST_ETHER=y | |
64 | +CONFIG_USB_ETHER_ASIX=y | |
65 | +CONFIG_USB_ETHER_RTL8152=y | |
66 | +CONFIG_DM_ETH=y | |
67 | + | |
68 | +CONFIG_USB_GADGET=y | |
69 | +CONFIG_USB_GADGET_DOWNLOAD=y | |
70 | +CONFIG_USB_GADGET_MANUFACTURER="FSL" | |
71 | +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | |
72 | +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | |
73 | +CONFIG_CI_UDC=y |
include/configs/mx7ulp_val.h
1 | +/* SPDX-License-Identifier: GPL-2.0+ */ | |
2 | +/* | |
3 | + * Copyright (C) 2016 Freescale Semiconductor, Inc. | |
4 | + * Copyright 2017 NXP | |
5 | + * | |
6 | + * Configuration settings for the Freescale i.MX7ULP Validationbbbb board. | |
7 | + */ | |
8 | + | |
9 | +#ifndef __MX7ULP_VAL_CONFIG_H | |
10 | +#define __MX7ULP_VAL_CONFIG_H | |
11 | + | |
12 | +#include <linux/sizes.h> | |
13 | +#include <asm/arch/imx-regs.h> | |
14 | +#include "imx_env.h" | |
15 | + | |
16 | +#define CONFIG_BOARD_POSTCLK_INIT | |
17 | +#define CONFIG_SYS_BOOTM_LEN 0x1000000 | |
18 | + | |
19 | +#define CONFIG_SYS_FSL_USDHC_NUM 2 | |
20 | + | |
21 | +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 | |
22 | +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ | |
23 | +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ | |
24 | +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ | |
25 | +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 | |
26 | + | |
27 | +/* Using ULP WDOG for reset */ | |
28 | +#define WDOG_BASE_ADDR WDG1_RBASE | |
29 | + | |
30 | + | |
31 | +#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */ | |
32 | + | |
33 | +#define CONFIG_INITRD_TAG | |
34 | +#define CONFIG_CMDLINE_TAG | |
35 | +#define CONFIG_SETUP_MEMORY_TAGS | |
36 | +/*#define CONFIG_REVISION_TAG*/ | |
37 | + | |
38 | +/* Size of malloc() pool */ | |
39 | +#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) | |
40 | + | |
41 | +/* UART */ | |
42 | +#ifdef CONFIG_TARGET_MX7ULP_10X10_VAL | |
43 | +#define LPUART_BASE LPUART6_RBASE | |
44 | +#else | |
45 | +#define LPUART_BASE LPUART4_RBASE | |
46 | +#endif | |
47 | + | |
48 | +/* allow to overwrite serial and ethaddr */ | |
49 | +#define CONFIG_ENV_OVERWRITE | |
50 | +#define CONFIG_BAUDRATE 115200 | |
51 | + | |
52 | +#define CONFIG_SYS_CACHELINE_SIZE 64 | |
53 | + | |
54 | +/* Miscellaneous configurable options */ | |
55 | +#define CONFIG_SYS_PROMPT "=> " | |
56 | +#define CONFIG_SYS_CBSIZE 512 | |
57 | + | |
58 | +/* Print Buffer Size */ | |
59 | +#define CONFIG_SYS_MAXARGS 256 | |
60 | + | |
61 | +/* Physical Memory Map */ | |
62 | + | |
63 | +#define PHYS_SDRAM 0x60000000ul | |
64 | +#ifdef CONFIG_TARGET_MX7ULP_10X10_VAL | |
65 | +#define PHYS_SDRAM_SIZE SZ_1G /*LPDDR2 1G*/ | |
66 | +#define CONFIG_SYS_MEMTEST_END 0x9E000000 | |
67 | +#else | |
68 | +#define PHYS_SDRAM_SIZE SZ_512M | |
69 | +#define CONFIG_SYS_MEMTEST_END 0x7E000000 | |
70 | +#endif | |
71 | +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM | |
72 | +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM | |
73 | + | |
74 | +#define CONFIG_LOADADDR 0x60800000 | |
75 | + | |
76 | +#ifdef CONFIG_TARGET_MX7ULP_10X10_VAL | |
77 | +#define CONFIG_DEFAULT_FDT_FILE "imx7ulp-10x10-val.dtb" | |
78 | +#else | |
79 | +#define CONFIG_DEFAULT_FDT_FILE "imx7ulp-14x14-val.dtb" | |
80 | +#endif | |
81 | + | |
82 | +#define CONFIG_MFG_ENV_SETTINGS \ | |
83 | + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ | |
84 | + "initrd_addr=0x66800000\0" \ | |
85 | + "initrd_high=0xffffffff\0" \ | |
86 | + "sd_dev=1\0" | |
87 | + | |
88 | +#define CONFIG_EXTRA_ENV_SETTINGS \ | |
89 | + CONFIG_MFG_ENV_SETTINGS \ | |
90 | + "script=boot.scr\0" \ | |
91 | + "image=zImage\0" \ | |
92 | + "console=ttyLP0\0" \ | |
93 | + "fdt_high=0xffffffff\0" \ | |
94 | + "initrd_high=0xffffffff\0" \ | |
95 | + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ | |
96 | + "fdt_addr=0x63000000\0" \ | |
97 | + "boot_fdt=try\0" \ | |
98 | + "earlycon=lpuart32,0x402D0000\0" \ | |
99 | + "ip_dyn=yes\0" \ | |
100 | + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ | |
101 | + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ | |
102 | + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ | |
103 | + "mmcautodetect=yes\0" \ | |
104 | + "mmcargs=setenv bootargs console=${console},${baudrate} " \ | |
105 | + "root=${mmcroot}\0" \ | |
106 | + "loadbootscript=" \ | |
107 | + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ | |
108 | + "bootscript=echo Running bootscript from mmc ...; " \ | |
109 | + "source\0" \ | |
110 | + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ | |
111 | + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ | |
112 | + "mmcboot=echo Booting from mmc ...; " \ | |
113 | + "run mmcargs; " \ | |
114 | + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ | |
115 | + "if run loadfdt; then " \ | |
116 | + "bootz ${loadaddr} - ${fdt_addr}; " \ | |
117 | + "else " \ | |
118 | + "if test ${boot_fdt} = try; then " \ | |
119 | + "bootz; " \ | |
120 | + "else " \ | |
121 | + "echo WARN: Cannot load the DT; " \ | |
122 | + "fi; " \ | |
123 | + "fi; " \ | |
124 | + "else " \ | |
125 | + "bootz; " \ | |
126 | + "fi;\0" \ | |
127 | + | |
128 | +#define CONFIG_BOOTCOMMAND \ | |
129 | + "mmc dev ${mmcdev}; if mmc rescan; then " \ | |
130 | + "if run loadbootscript; then " \ | |
131 | + "run bootscript; " \ | |
132 | + "else " \ | |
133 | + "if run loadimage; then " \ | |
134 | + "run mmcboot; " \ | |
135 | + "fi; " \ | |
136 | + "fi; " \ | |
137 | + "fi" | |
138 | + | |
139 | + | |
140 | +#define CONFIG_SYS_HZ 1000 | |
141 | +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
142 | + | |
143 | +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
144 | +#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K | |
145 | + | |
146 | +#define CONFIG_SYS_INIT_SP_OFFSET \ | |
147 | + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
148 | +#define CONFIG_SYS_INIT_SP_ADDR \ | |
149 | + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
150 | + | |
151 | +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) | |
152 | +#define CONFIG_CMD_CACHE | |
153 | +#endif | |
154 | + | |
155 | +/* USB Configs */ | |
156 | +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) | |
157 | + | |
158 | +/* QSPI configs */ | |
159 | +#ifdef CONFIG_FSL_QSPI | |
160 | +#define CONFIG_SYS_FSL_QSPI_AHB | |
161 | +#ifdef CONFIG_TARGET_MX7ULP_10X10_VAL | |
162 | +#define FSL_QSPI_FLASH_NUM 2 | |
163 | +#define FSL_QSPI_FLASH_SIZE SZ_32M | |
164 | +#else | |
165 | +#define FSL_QSPI_FLASH_NUM 1 | |
166 | +#define FSL_QSPI_FLASH_SIZE SZ_64M | |
167 | +#endif | |
168 | +#define QSPI0_BASE_ADDR 0x410A5000 | |
169 | +#define QSPI0_AMBA_BASE 0xC0000000 | |
170 | +#endif | |
171 | + | |
172 | +#endif /* __CONFIG_H */ |