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Commit 312aca4e6964812007c8218c0b4b0737e9e0f46a

Authored by Vitaly Andrianov
Committed by Tom Rini
1 parent 66c98a0c38
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

net: keystone_net: move serdes setup to initialization function 

On Keystone2 devices serdes must be initialized before accessing MDIO bus.
This commit moves the keystone2_net_serdes_setup() from keystone2_eth_open
to keystone2_emac_initialize to meet that requirement.

This also eliminates unnecessary serdes initializatin every time when the
keystone2_eth_open is being called.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Nishanth Menon <nm@ti.com>

Showing 1 changed file with 2 additions and 2 deletions Inline Diff

drivers/net/keystone_net.c
Diff comments   View file @ 312aca4
1 /* 1 /*
2 * Ethernet driver for TI K2HK EVM. 2 * Ethernet driver for TI K2HK EVM.
3 * 3 *
4 * (C) Copyright 2012-2014 4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com> 5 * Texas Instruments Incorporated, <www.ti.com>
6 * 6 *
7 * SPDX-License-Identifier: GPL-2.0+ 7 * SPDX-License-Identifier: GPL-2.0+
8 */ 8 */
9 #include <common.h> 9 #include <common.h>
10 #include <command.h> 10 #include <command.h>
11 11
12 #include <net.h> 12 #include <net.h>
13 #include <phy.h> 13 #include <phy.h>
14 #include <errno.h> 14 #include <errno.h>
15 #include <miiphy.h> 15 #include <miiphy.h>
16 #include <malloc.h> 16 #include <malloc.h>
17 #include <asm/ti-common/keystone_nav.h> 17 #include <asm/ti-common/keystone_nav.h>
18 #include <asm/ti-common/keystone_net.h> 18 #include <asm/ti-common/keystone_net.h>
19 #include <asm/ti-common/keystone_serdes.h> 19 #include <asm/ti-common/keystone_serdes.h>
20 20
21 unsigned int emac_open; 21 unsigned int emac_open;
22 static struct mii_dev *mdio_bus; 22 static struct mii_dev *mdio_bus;
23 static unsigned int sys_has_mdio = 1; 23 static unsigned int sys_has_mdio = 1;
24 24
25 #ifdef KEYSTONE2_EMAC_GIG_ENABLE 25 #ifdef KEYSTONE2_EMAC_GIG_ENABLE
26 #define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x) 26 #define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x)
27 #else 27 #else
28 #define emac_gigabit_enable(x) /* no gigabit to enable */ 28 #define emac_gigabit_enable(x) /* no gigabit to enable */
29 #endif 29 #endif
30 30
31 #define RX_BUFF_NUMS 24 31 #define RX_BUFF_NUMS 24
32 #define RX_BUFF_LEN 1520 32 #define RX_BUFF_LEN 1520
33 #define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN 33 #define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
34 #define SGMII_ANEG_TIMEOUT 4000 34 #define SGMII_ANEG_TIMEOUT 4000
35 35
36 static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16); 36 static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16);
37 37
38 struct rx_buff_desc net_rx_buffs = { 38 struct rx_buff_desc net_rx_buffs = {
39 .buff_ptr = rx_buffs, 39 .buff_ptr = rx_buffs,
40 .num_buffs = RX_BUFF_NUMS, 40 .num_buffs = RX_BUFF_NUMS,
41 .buff_len = RX_BUFF_LEN, 41 .buff_len = RX_BUFF_LEN,
42 .rx_flow = 22, 42 .rx_flow = 22,
43 }; 43 };
44 44
45 static void keystone2_net_serdes_setup(void); 45 static void keystone2_net_serdes_setup(void);
46 46
47 int keystone2_eth_read_mac_addr(struct eth_device *dev) 47 int keystone2_eth_read_mac_addr(struct eth_device *dev)
48 { 48 {
49 struct eth_priv_t *eth_priv; 49 struct eth_priv_t *eth_priv;
50 u32 maca = 0; 50 u32 maca = 0;
51 u32 macb = 0; 51 u32 macb = 0;
52 52
53 eth_priv = (struct eth_priv_t *)dev->priv; 53 eth_priv = (struct eth_priv_t *)dev->priv;
54 54
55 /* Read the e-fuse mac address */ 55 /* Read the e-fuse mac address */
56 if (eth_priv->slave_port == 1) { 56 if (eth_priv->slave_port == 1) {
57 maca = __raw_readl(MAC_ID_BASE_ADDR); 57 maca = __raw_readl(MAC_ID_BASE_ADDR);
58 macb = __raw_readl(MAC_ID_BASE_ADDR + 4); 58 macb = __raw_readl(MAC_ID_BASE_ADDR + 4);
59 } 59 }
60 60
61 dev->enetaddr[0] = (macb >> 8) & 0xff; 61 dev->enetaddr[0] = (macb >> 8) & 0xff;
62 dev->enetaddr[1] = (macb >> 0) & 0xff; 62 dev->enetaddr[1] = (macb >> 0) & 0xff;
63 dev->enetaddr[2] = (maca >> 24) & 0xff; 63 dev->enetaddr[2] = (maca >> 24) & 0xff;
64 dev->enetaddr[3] = (maca >> 16) & 0xff; 64 dev->enetaddr[3] = (maca >> 16) & 0xff;
65 dev->enetaddr[4] = (maca >> 8) & 0xff; 65 dev->enetaddr[4] = (maca >> 8) & 0xff;
66 dev->enetaddr[5] = (maca >> 0) & 0xff; 66 dev->enetaddr[5] = (maca >> 0) & 0xff;
67 67
68 return 0; 68 return 0;
69 } 69 }
70 70
71 /* MDIO */ 71 /* MDIO */
72 72
73 static int keystone2_mdio_reset(struct mii_dev *bus) 73 static int keystone2_mdio_reset(struct mii_dev *bus)
74 { 74 {
75 u_int32_t clkdiv; 75 u_int32_t clkdiv;
76 struct mdio_regs *adap_mdio = bus->priv; 76 struct mdio_regs *adap_mdio = bus->priv;
77 77
78 clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; 78 clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
79 79
80 writel((clkdiv & 0xffff) | MDIO_CONTROL_ENABLE | 80 writel((clkdiv & 0xffff) | MDIO_CONTROL_ENABLE |
81 MDIO_CONTROL_FAULT | MDIO_CONTROL_FAULT_ENABLE, 81 MDIO_CONTROL_FAULT | MDIO_CONTROL_FAULT_ENABLE,
82 &adap_mdio->control); 82 &adap_mdio->control);
83 83
84 while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE) 84 while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE)
85 ; 85 ;
86 86
87 return 0; 87 return 0;
88 } 88 }
89 89
90 /** 90 /**
91 * keystone2_mdio_read - read a PHY register via MDIO interface. 91 * keystone2_mdio_read - read a PHY register via MDIO interface.
92 * Blocks until operation is complete. 92 * Blocks until operation is complete.
93 */ 93 */
94 static int keystone2_mdio_read(struct mii_dev *bus, 94 static int keystone2_mdio_read(struct mii_dev *bus,
95 int addr, int devad, int reg) 95 int addr, int devad, int reg)
96 { 96 {
97 int tmp; 97 int tmp;
98 struct mdio_regs *adap_mdio = bus->priv; 98 struct mdio_regs *adap_mdio = bus->priv;
99 99
100 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) 100 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
101 ; 101 ;
102 102
103 writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_READ | 103 writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_READ |
104 ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16), 104 ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16),
105 &adap_mdio->useraccess0); 105 &adap_mdio->useraccess0);
106 106
107 /* Wait for command to complete */ 107 /* Wait for command to complete */
108 while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO) 108 while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO)
109 ; 109 ;
110 110
111 if (tmp & MDIO_USERACCESS0_ACK) 111 if (tmp & MDIO_USERACCESS0_ACK)
112 return tmp & 0xffff; 112 return tmp & 0xffff;
113 113
114 return -1; 114 return -1;
115 } 115 }
116 116
117 /** 117 /**
118 * keystone2_mdio_write - write to a PHY register via MDIO interface. 118 * keystone2_mdio_write - write to a PHY register via MDIO interface.
119 * Blocks until operation is complete. 119 * Blocks until operation is complete.
120 */ 120 */
121 static int keystone2_mdio_write(struct mii_dev *bus, 121 static int keystone2_mdio_write(struct mii_dev *bus,
122 int addr, int devad, int reg, u16 val) 122 int addr, int devad, int reg, u16 val)
123 { 123 {
124 struct mdio_regs *adap_mdio = bus->priv; 124 struct mdio_regs *adap_mdio = bus->priv;
125 125
126 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) 126 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
127 ; 127 ;
128 128
129 writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_WRITE | 129 writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_WRITE |
130 ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16) | 130 ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16) |
131 (val & 0xffff), &adap_mdio->useraccess0); 131 (val & 0xffff), &adap_mdio->useraccess0);
132 132
133 /* Wait for command to complete */ 133 /* Wait for command to complete */
134 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) 134 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
135 ; 135 ;
136 136
137 return 0; 137 return 0;
138 } 138 }
139 139
140 static void __attribute__((unused)) 140 static void __attribute__((unused))
141 keystone2_eth_gigabit_enable(struct eth_device *dev) 141 keystone2_eth_gigabit_enable(struct eth_device *dev)
142 { 142 {
143 u_int16_t data; 143 u_int16_t data;
144 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; 144 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
145 145
146 if (sys_has_mdio) { 146 if (sys_has_mdio) {
147 data = keystone2_mdio_read(mdio_bus, eth_priv->phy_addr, 147 data = keystone2_mdio_read(mdio_bus, eth_priv->phy_addr,
148 MDIO_DEVAD_NONE, 0); 148 MDIO_DEVAD_NONE, 0);
149 /* speed selection MSB */ 149 /* speed selection MSB */
150 if (!(data & (1 << 6))) 150 if (!(data & (1 << 6)))
151 return; 151 return;
152 } 152 }
153 153
154 /* 154 /*
155 * Check if link detected is giga-bit 155 * Check if link detected is giga-bit
156 * If Gigabit mode detected, enable gigbit in MAC 156 * If Gigabit mode detected, enable gigbit in MAC
157 */ 157 */
158 writel(readl(DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + 158 writel(readl(DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) +
159 CPGMACSL_REG_CTL) | 159 CPGMACSL_REG_CTL) |
160 EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE, 160 EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
161 DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL); 161 DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL);
162 } 162 }
163 163
164 int keystone_sgmii_link_status(int port) 164 int keystone_sgmii_link_status(int port)
165 { 165 {
166 u32 status = 0; 166 u32 status = 0;
167 167
168 status = __raw_readl(SGMII_STATUS_REG(port)); 168 status = __raw_readl(SGMII_STATUS_REG(port));
169 169
170 return (status & SGMII_REG_STATUS_LOCK) && 170 return (status & SGMII_REG_STATUS_LOCK) &&
171 (status & SGMII_REG_STATUS_LINK); 171 (status & SGMII_REG_STATUS_LINK);
172 } 172 }
173 173
174 int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface) 174 int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface)
175 { 175 {
176 unsigned int i, status, mask; 176 unsigned int i, status, mask;
177 unsigned int mr_adv_ability, control; 177 unsigned int mr_adv_ability, control;
178 178
179 switch (interface) { 179 switch (interface) {
180 case SGMII_LINK_MAC_MAC_AUTONEG: 180 case SGMII_LINK_MAC_MAC_AUTONEG:
181 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE | 181 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
182 SGMII_REG_MR_ADV_LINK | 182 SGMII_REG_MR_ADV_LINK |
183 SGMII_REG_MR_ADV_FULL_DUPLEX | 183 SGMII_REG_MR_ADV_FULL_DUPLEX |
184 SGMII_REG_MR_ADV_GIG_MODE); 184 SGMII_REG_MR_ADV_GIG_MODE);
185 control = (SGMII_REG_CONTROL_MASTER | 185 control = (SGMII_REG_CONTROL_MASTER |
186 SGMII_REG_CONTROL_AUTONEG); 186 SGMII_REG_CONTROL_AUTONEG);
187 187
188 break; 188 break;
189 case SGMII_LINK_MAC_PHY: 189 case SGMII_LINK_MAC_PHY:
190 case SGMII_LINK_MAC_PHY_FORCED: 190 case SGMII_LINK_MAC_PHY_FORCED:
191 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE; 191 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
192 control = SGMII_REG_CONTROL_AUTONEG; 192 control = SGMII_REG_CONTROL_AUTONEG;
193 193
194 break; 194 break;
195 case SGMII_LINK_MAC_MAC_FORCED: 195 case SGMII_LINK_MAC_MAC_FORCED:
196 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE | 196 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
197 SGMII_REG_MR_ADV_LINK | 197 SGMII_REG_MR_ADV_LINK |
198 SGMII_REG_MR_ADV_FULL_DUPLEX | 198 SGMII_REG_MR_ADV_FULL_DUPLEX |
199 SGMII_REG_MR_ADV_GIG_MODE); 199 SGMII_REG_MR_ADV_GIG_MODE);
200 control = SGMII_REG_CONTROL_MASTER; 200 control = SGMII_REG_CONTROL_MASTER;
201 201
202 break; 202 break;
203 case SGMII_LINK_MAC_FIBER: 203 case SGMII_LINK_MAC_FIBER:
204 mr_adv_ability = 0x20; 204 mr_adv_ability = 0x20;
205 control = SGMII_REG_CONTROL_AUTONEG; 205 control = SGMII_REG_CONTROL_AUTONEG;
206 206
207 break; 207 break;
208 default: 208 default:
209 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE; 209 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
210 control = SGMII_REG_CONTROL_AUTONEG; 210 control = SGMII_REG_CONTROL_AUTONEG;
211 } 211 }
212 212
213 __raw_writel(0, SGMII_CTL_REG(port)); 213 __raw_writel(0, SGMII_CTL_REG(port));
214 214
215 /* 215 /*
216 * Wait for the SerDes pll to lock, 216 * Wait for the SerDes pll to lock,
217 * but don't trap if lock is never read 217 * but don't trap if lock is never read
218 */ 218 */
219 for (i = 0; i < 1000; i++) { 219 for (i = 0; i < 1000; i++) {
220 udelay(2000); 220 udelay(2000);
221 status = __raw_readl(SGMII_STATUS_REG(port)); 221 status = __raw_readl(SGMII_STATUS_REG(port));
222 if ((status & SGMII_REG_STATUS_LOCK) != 0) 222 if ((status & SGMII_REG_STATUS_LOCK) != 0)
223 break; 223 break;
224 } 224 }
225 225
226 __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port)); 226 __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port));
227 __raw_writel(control, SGMII_CTL_REG(port)); 227 __raw_writel(control, SGMII_CTL_REG(port));
228 228
229 229
230 mask = SGMII_REG_STATUS_LINK; 230 mask = SGMII_REG_STATUS_LINK;
231 231
232 if (control & SGMII_REG_CONTROL_AUTONEG) 232 if (control & SGMII_REG_CONTROL_AUTONEG)
233 mask |= SGMII_REG_STATUS_AUTONEG; 233 mask |= SGMII_REG_STATUS_AUTONEG;
234 234
235 status = __raw_readl(SGMII_STATUS_REG(port)); 235 status = __raw_readl(SGMII_STATUS_REG(port));
236 if ((status & mask) == mask) 236 if ((status & mask) == mask)
237 return 0; 237 return 0;
238 238
239 printf("\n%s Waiting for SGMII auto negotiation to complete", 239 printf("\n%s Waiting for SGMII auto negotiation to complete",
240 phy_dev->dev->name); 240 phy_dev->dev->name);
241 while ((status & mask) != mask) { 241 while ((status & mask) != mask) {
242 /* 242 /*
243 * Timeout reached ? 243 * Timeout reached ?
244 */ 244 */
245 if (i > SGMII_ANEG_TIMEOUT) { 245 if (i > SGMII_ANEG_TIMEOUT) {
246 puts(" TIMEOUT !\n"); 246 puts(" TIMEOUT !\n");
247 phy_dev->link = 0; 247 phy_dev->link = 0;
248 return 0; 248 return 0;
249 } 249 }
250 250
251 if (ctrlc()) { 251 if (ctrlc()) {
252 puts("user interrupt!\n"); 252 puts("user interrupt!\n");
253 phy_dev->link = 0; 253 phy_dev->link = 0;
254 return -EINTR; 254 return -EINTR;
255 } 255 }
256 256
257 if ((i++ % 500) == 0) 257 if ((i++ % 500) == 0)
258 printf("."); 258 printf(".");
259 259
260 udelay(1000); /* 1 ms */ 260 udelay(1000); /* 1 ms */
261 status = __raw_readl(SGMII_STATUS_REG(port)); 261 status = __raw_readl(SGMII_STATUS_REG(port));
262 } 262 }
263 puts(" done\n"); 263 puts(" done\n");
264 264
265 return 0; 265 return 0;
266 } 266 }
267 267
268 int mac_sl_reset(u32 port) 268 int mac_sl_reset(u32 port)
269 { 269 {
270 u32 i, v; 270 u32 i, v;
271 271
272 if (port >= DEVICE_N_GMACSL_PORTS) 272 if (port >= DEVICE_N_GMACSL_PORTS)
273 return GMACSL_RET_INVALID_PORT; 273 return GMACSL_RET_INVALID_PORT;
274 274
275 /* Set the soft reset bit */ 275 /* Set the soft reset bit */
276 writel(CPGMAC_REG_RESET_VAL_RESET, 276 writel(CPGMAC_REG_RESET_VAL_RESET,
277 DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET); 277 DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
278 278
279 /* Wait for the bit to clear */ 279 /* Wait for the bit to clear */
280 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) { 280 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
281 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET); 281 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
282 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) != 282 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
283 CPGMAC_REG_RESET_VAL_RESET) 283 CPGMAC_REG_RESET_VAL_RESET)
284 return GMACSL_RET_OK; 284 return GMACSL_RET_OK;
285 } 285 }
286 286
287 /* Timeout on the reset */ 287 /* Timeout on the reset */
288 return GMACSL_RET_WARN_RESET_INCOMPLETE; 288 return GMACSL_RET_WARN_RESET_INCOMPLETE;
289 } 289 }
290 290
291 int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg) 291 int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
292 { 292 {
293 u32 v, i; 293 u32 v, i;
294 int ret = GMACSL_RET_OK; 294 int ret = GMACSL_RET_OK;
295 295
296 if (port >= DEVICE_N_GMACSL_PORTS) 296 if (port >= DEVICE_N_GMACSL_PORTS)
297 return GMACSL_RET_INVALID_PORT; 297 return GMACSL_RET_INVALID_PORT;
298 298
299 if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) { 299 if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) {
300 cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN; 300 cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN;
301 ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG; 301 ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG;
302 } 302 }
303 303
304 /* Must wait if the device is undergoing reset */ 304 /* Must wait if the device is undergoing reset */
305 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) { 305 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
306 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET); 306 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
307 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) != 307 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
308 CPGMAC_REG_RESET_VAL_RESET) 308 CPGMAC_REG_RESET_VAL_RESET)
309 break; 309 break;
310 } 310 }
311 311
312 if (i == DEVICE_EMACSL_RESET_POLL_COUNT) 312 if (i == DEVICE_EMACSL_RESET_POLL_COUNT)
313 return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE; 313 return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE;
314 314
315 writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN); 315 writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
316 writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL); 316 writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
317 317
318 #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L) 318 #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
319 /* Map RX packet flow priority to 0 */ 319 /* Map RX packet flow priority to 0 */
320 writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP); 320 writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP);
321 #endif 321 #endif
322 322
323 return ret; 323 return ret;
324 } 324 }
325 325
326 int ethss_config(u32 ctl, u32 max_pkt_size) 326 int ethss_config(u32 ctl, u32 max_pkt_size)
327 { 327 {
328 u32 i; 328 u32 i;
329 329
330 /* Max length register */ 330 /* Max length register */
331 writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN); 331 writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN);
332 332
333 /* Control register */ 333 /* Control register */
334 writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL); 334 writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL);
335 335
336 /* All statistics enabled by default */ 336 /* All statistics enabled by default */
337 writel(CPSW_REG_VAL_STAT_ENABLE_ALL, 337 writel(CPSW_REG_VAL_STAT_ENABLE_ALL,
338 DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN); 338 DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN);
339 339
340 /* Reset and enable the ALE */ 340 /* Reset and enable the ALE */
341 writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE | 341 writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE |
342 CPSW_REG_VAL_ALE_CTL_BYPASS, 342 CPSW_REG_VAL_ALE_CTL_BYPASS,
343 DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL); 343 DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL);
344 344
345 /* All ports put into forward mode */ 345 /* All ports put into forward mode */
346 for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++) 346 for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++)
347 writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE, 347 writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE,
348 DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i)); 348 DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i));
349 349
350 return 0; 350 return 0;
351 } 351 }
352 352
353 int ethss_start(void) 353 int ethss_start(void)
354 { 354 {
355 int i; 355 int i;
356 struct mac_sl_cfg cfg; 356 struct mac_sl_cfg cfg;
357 357
358 cfg.max_rx_len = MAX_SIZE_STREAM_BUFFER; 358 cfg.max_rx_len = MAX_SIZE_STREAM_BUFFER;
359 cfg.ctl = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL; 359 cfg.ctl = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL;
360 360
361 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) { 361 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) {
362 mac_sl_reset(i); 362 mac_sl_reset(i);
363 mac_sl_config(i, &cfg); 363 mac_sl_config(i, &cfg);
364 } 364 }
365 365
366 return 0; 366 return 0;
367 } 367 }
368 368
369 int ethss_stop(void) 369 int ethss_stop(void)
370 { 370 {
371 int i; 371 int i;
372 372
373 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) 373 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++)
374 mac_sl_reset(i); 374 mac_sl_reset(i);
375 375
376 return 0; 376 return 0;
377 } 377 }
378 378
379 int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num) 379 int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num)
380 { 380 {
381 if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE) 381 if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE)
382 num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE; 382 num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE;
383 383
384 return ksnav_send(&netcp_pktdma, buffer, 384 return ksnav_send(&netcp_pktdma, buffer,
385 num_bytes, (slave_port_num) << 16); 385 num_bytes, (slave_port_num) << 16);
386 } 386 }
387 387
388 /* Eth device open */ 388 /* Eth device open */
389 static int keystone2_eth_open(struct eth_device *dev, bd_t *bis) 389 static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
390 { 390 {
391 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; 391 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
392 struct phy_device *phy_dev = eth_priv->phy_dev; 392 struct phy_device *phy_dev = eth_priv->phy_dev;
393 393
394 debug("+ emac_open\n"); 394 debug("+ emac_open\n");
395 395
396 net_rx_buffs.rx_flow = eth_priv->rx_flow; 396 net_rx_buffs.rx_flow = eth_priv->rx_flow;
397 397
398 sys_has_mdio = 398 sys_has_mdio =
399 (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0; 399 (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0;
400 400
401 keystone2_net_serdes_setup();
402
403 if (sys_has_mdio) 401 if (sys_has_mdio)
404 keystone2_mdio_reset(mdio_bus); 402 keystone2_mdio_reset(mdio_bus);
405 403
406 keystone_sgmii_config(phy_dev, eth_priv->slave_port - 1, 404 keystone_sgmii_config(phy_dev, eth_priv->slave_port - 1,
407 eth_priv->sgmii_link_type); 405 eth_priv->sgmii_link_type);
408 406
409 udelay(10000); 407 udelay(10000);
410 408
411 /* On chip switch configuration */ 409 /* On chip switch configuration */
412 ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE); 410 ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE);
413 411
414 /* TODO: add error handling code */ 412 /* TODO: add error handling code */
415 if (qm_init()) { 413 if (qm_init()) {
416 printf("ERROR: qm_init()\n"); 414 printf("ERROR: qm_init()\n");
417 return -1; 415 return -1;
418 } 416 }
419 if (ksnav_init(&netcp_pktdma, &net_rx_buffs)) { 417 if (ksnav_init(&netcp_pktdma, &net_rx_buffs)) {
420 qm_close(); 418 qm_close();
421 printf("ERROR: netcp_init()\n"); 419 printf("ERROR: netcp_init()\n");
422 return -1; 420 return -1;
423 } 421 }
424 422
425 /* 423 /*
426 * Streaming switch configuration. If not present this 424 * Streaming switch configuration. If not present this
427 * statement is defined to void in target.h. 425 * statement is defined to void in target.h.
428 * If present this is usually defined to a series of register writes 426 * If present this is usually defined to a series of register writes
429 */ 427 */
430 hw_config_streaming_switch(); 428 hw_config_streaming_switch();
431 429
432 if (sys_has_mdio) { 430 if (sys_has_mdio) {
433 keystone2_mdio_reset(mdio_bus); 431 keystone2_mdio_reset(mdio_bus);
434 432
435 phy_startup(phy_dev); 433 phy_startup(phy_dev);
436 if (phy_dev->link == 0) { 434 if (phy_dev->link == 0) {
437 ksnav_close(&netcp_pktdma); 435 ksnav_close(&netcp_pktdma);
438 qm_close(); 436 qm_close();
439 return -1; 437 return -1;
440 } 438 }
441 } 439 }
442 440
443 emac_gigabit_enable(dev); 441 emac_gigabit_enable(dev);
444 442
445 ethss_start(); 443 ethss_start();
446 444
447 debug("- emac_open\n"); 445 debug("- emac_open\n");
448 446
449 emac_open = 1; 447 emac_open = 1;
450 448
451 return 0; 449 return 0;
452 } 450 }
453 451
454 /* Eth device close */ 452 /* Eth device close */
455 void keystone2_eth_close(struct eth_device *dev) 453 void keystone2_eth_close(struct eth_device *dev)
456 { 454 {
457 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; 455 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
458 struct phy_device *phy_dev = eth_priv->phy_dev; 456 struct phy_device *phy_dev = eth_priv->phy_dev;
459 457
460 debug("+ emac_close\n"); 458 debug("+ emac_close\n");
461 459
462 if (!emac_open) 460 if (!emac_open)
463 return; 461 return;
464 462
465 ethss_stop(); 463 ethss_stop();
466 464
467 ksnav_close(&netcp_pktdma); 465 ksnav_close(&netcp_pktdma);
468 qm_close(); 466 qm_close();
469 phy_shutdown(phy_dev); 467 phy_shutdown(phy_dev);
470 468
471 emac_open = 0; 469 emac_open = 0;
472 470
473 debug("- emac_close\n"); 471 debug("- emac_close\n");
474 } 472 }
475 473
476 /* 474 /*
477 * This function sends a single packet on the network and returns 475 * This function sends a single packet on the network and returns
478 * positive number (number of bytes transmitted) or negative for error 476 * positive number (number of bytes transmitted) or negative for error
479 */ 477 */
480 static int keystone2_eth_send_packet(struct eth_device *dev, 478 static int keystone2_eth_send_packet(struct eth_device *dev,
481 void *packet, int length) 479 void *packet, int length)
482 { 480 {
483 int ret_status = -1; 481 int ret_status = -1;
484 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; 482 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
485 struct phy_device *phy_dev = eth_priv->phy_dev; 483 struct phy_device *phy_dev = eth_priv->phy_dev;
486 484
487 genphy_update_link(phy_dev); 485 genphy_update_link(phy_dev);
488 if (phy_dev->link == 0) 486 if (phy_dev->link == 0)
489 return -1; 487 return -1;
490 488
491 if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0) 489 if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0)
492 return ret_status; 490 return ret_status;
493 491
494 return length; 492 return length;
495 } 493 }
496 494
497 /* 495 /*
498 * This function handles receipt of a packet from the network 496 * This function handles receipt of a packet from the network
499 */ 497 */
500 static int keystone2_eth_rcv_packet(struct eth_device *dev) 498 static int keystone2_eth_rcv_packet(struct eth_device *dev)
501 { 499 {
502 void *hd; 500 void *hd;
503 int pkt_size; 501 int pkt_size;
504 u32 *pkt; 502 u32 *pkt;
505 503
506 hd = ksnav_recv(&netcp_pktdma, &pkt, &pkt_size); 504 hd = ksnav_recv(&netcp_pktdma, &pkt, &pkt_size);
507 if (hd == NULL) 505 if (hd == NULL)
508 return 0; 506 return 0;
509 507
510 NetReceive((uchar *)pkt, pkt_size); 508 NetReceive((uchar *)pkt, pkt_size);
511 509
512 ksnav_release_rxhd(&netcp_pktdma, hd); 510 ksnav_release_rxhd(&netcp_pktdma, hd);
513 511
514 return pkt_size; 512 return pkt_size;
515 } 513 }
516 514
517 /* 515 /*
518 * This function initializes the EMAC hardware. 516 * This function initializes the EMAC hardware.
519 */ 517 */
520 int keystone2_emac_initialize(struct eth_priv_t *eth_priv) 518 int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
521 { 519 {
522 int res; 520 int res;
523 struct eth_device *dev; 521 struct eth_device *dev;
524 struct phy_device *phy_dev; 522 struct phy_device *phy_dev;
525 523
526 dev = malloc(sizeof(struct eth_device)); 524 dev = malloc(sizeof(struct eth_device));
527 if (dev == NULL) 525 if (dev == NULL)
528 return -1; 526 return -1;
529 527
530 memset(dev, 0, sizeof(struct eth_device)); 528 memset(dev, 0, sizeof(struct eth_device));
531 529
532 strcpy(dev->name, eth_priv->int_name); 530 strcpy(dev->name, eth_priv->int_name);
533 dev->priv = eth_priv; 531 dev->priv = eth_priv;
534 532
535 keystone2_eth_read_mac_addr(dev); 533 keystone2_eth_read_mac_addr(dev);
536 534
537 dev->iobase = 0; 535 dev->iobase = 0;
538 dev->init = keystone2_eth_open; 536 dev->init = keystone2_eth_open;
539 dev->halt = keystone2_eth_close; 537 dev->halt = keystone2_eth_close;
540 dev->send = keystone2_eth_send_packet; 538 dev->send = keystone2_eth_send_packet;
541 dev->recv = keystone2_eth_rcv_packet; 539 dev->recv = keystone2_eth_rcv_packet;
542 540
543 eth_register(dev); 541 eth_register(dev);
544 542
545 /* Register MDIO bus if it's not registered yet */ 543 /* Register MDIO bus if it's not registered yet */
546 if (!mdio_bus) { 544 if (!mdio_bus) {
547 mdio_bus = mdio_alloc(); 545 mdio_bus = mdio_alloc();
548 mdio_bus->read = keystone2_mdio_read; 546 mdio_bus->read = keystone2_mdio_read;
549 mdio_bus->write = keystone2_mdio_write; 547 mdio_bus->write = keystone2_mdio_write;
550 mdio_bus->reset = keystone2_mdio_reset; 548 mdio_bus->reset = keystone2_mdio_reset;
551 mdio_bus->priv = (void *)EMAC_MDIO_BASE_ADDR; 549 mdio_bus->priv = (void *)EMAC_MDIO_BASE_ADDR;
552 sprintf(mdio_bus->name, "ethernet-mdio"); 550 sprintf(mdio_bus->name, "ethernet-mdio");
553 551
554 res = mdio_register(mdio_bus); 552 res = mdio_register(mdio_bus);
555 if (res) 553 if (res)
556 return res; 554 return res;
557 } 555 }
556
557 keystone2_net_serdes_setup();
558 558
559 /* Create phy device and bind it with driver */ 559 /* Create phy device and bind it with driver */
560 #ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE 560 #ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
561 phy_dev = phy_connect(mdio_bus, eth_priv->phy_addr, 561 phy_dev = phy_connect(mdio_bus, eth_priv->phy_addr,
562 dev, PHY_INTERFACE_MODE_SGMII); 562 dev, PHY_INTERFACE_MODE_SGMII);
563 phy_config(phy_dev); 563 phy_config(phy_dev);
564 #else 564 #else
565 phy_dev = phy_find_by_mask(mdio_bus, 1 << eth_priv->phy_addr, 565 phy_dev = phy_find_by_mask(mdio_bus, 1 << eth_priv->phy_addr,
566 PHY_INTERFACE_MODE_SGMII); 566 PHY_INTERFACE_MODE_SGMII);
567 phy_dev->dev = dev; 567 phy_dev->dev = dev;
568 #endif 568 #endif
569 eth_priv->phy_dev = phy_dev; 569 eth_priv->phy_dev = phy_dev;
570 570
571 return 0; 571 return 0;
572 } 572 }
573 573
574 struct ks2_serdes ks2_serdes_sgmii_156p25mhz = { 574 struct ks2_serdes ks2_serdes_sgmii_156p25mhz = {
575 .clk = SERDES_CLOCK_156P25M, 575 .clk = SERDES_CLOCK_156P25M,
576 .rate = SERDES_RATE_5G, 576 .rate = SERDES_RATE_5G,
577 .rate_mode = SERDES_QUARTER_RATE, 577 .rate_mode = SERDES_QUARTER_RATE,
578 .intf = SERDES_PHY_SGMII, 578 .intf = SERDES_PHY_SGMII,
579 .loopback = 0, 579 .loopback = 0,
580 }; 580 };
581 581
582 static void keystone2_net_serdes_setup(void) 582 static void keystone2_net_serdes_setup(void)
583 { 583 {
584 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE, 584 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE,
585 &ks2_serdes_sgmii_156p25mhz, 585 &ks2_serdes_sgmii_156p25mhz,
586 CONFIG_KSNET_SERDES_LANES_PER_SGMII); 586 CONFIG_KSNET_SERDES_LANES_PER_SGMII);
587 587
588 #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L) 588 #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
589 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE, 589 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE,
590 &ks2_serdes_sgmii_156p25mhz, 590 &ks2_serdes_sgmii_156p25mhz,
591 CONFIG_KSNET_SERDES_LANES_PER_SGMII); 591 CONFIG_KSNET_SERDES_LANES_PER_SGMII);
592 #endif 592 #endif
593 593
594 /* wait till setup */ 594 /* wait till setup */
595 udelay(5000); 595 udelay(5000);