keystone2: ddr3: eliminate using global ddr3_size variable

KS2 ddr3 initialization uses ddr3_size global variable before u-boot relocation. Even if the variable is not being used after relocation, writing to it corrupts relocation table. This patch removes the global ddr3_size variable and uses local one instead. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Tested-by: Nishanth Menon <nm@ti.com>

keystone2: ddr3: eliminate using global ddr3_size variable
KS2 ddr3 initialization uses ddr3_size global variable before u-boot relocation. Even if the variable is not being used after relocation, writing to it corrupts relocation table. This patch removes the global ddr3_size variable and uses local one instead. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Tested-by: Nishanth Menon <nm@ti.com>
Vitaly Andrianov · Tom Rini
1 parent bba379d498
Showing 6 changed files with 17 additions and 36 deletions Side-by-side Diff
arch/arm/cpu/armv7/keystone/ddr3.c
arch/arm/include/asm/arch-keystone/ddr3.h
board/ti/ks2_evm/board.c
board/ti/ks2_evm/ddr3_k2e.c
board/ti/ks2_evm/ddr3_k2hk.c
board/ti/ks2_evm/ddr3_k2l.c
@@ -263,17 +263,14 @@
 }
 #endif
  
-void ddr3_init_ecc(u32 base)
+void ddr3_init_ecc(u32 base, u32 ddr3_size)
 {
-	u32 ddr3_size;
-
 	if (!ddr3_ecc_support_rmw(base)) {
 		ddr3_disable_ecc(base);
 		return;
 	}
  
 	ddr3_ecc_init_range(base);
-	ddr3_size = ddr3_get_size();
 	ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size);
  
 	/* mapping DDR3 ECC system interrupt from CIC2 to GIC */
@@ -48,10 +48,9 @@
 	unsigned int sdrfc;
 };
  
-void ddr3_init(void);
-int ddr3_get_size(void);
+u32 ddr3_init(void);
 void ddr3_reset_ddrphy(void);
-void ddr3_init_ecc(u32 base);
+void ddr3_init_ecc(u32 base, u32 ddr3_size);
 void ddr3_disable_ecc(u32 base);
 void ddr3_check_ecc_int(u32 base);
 int ddr3_ecc_support_rmw(u32 base);
@@ -35,12 +35,14 @@
  
 int dram_init(void)
 {
-	ddr3_init();
+	u32 ddr3_size;
  
+	ddr3_size = ddr3_init();
+
 	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
 				    CONFIG_MAX_RAM_BANK_SIZE);
 	aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
-	ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE);
+	ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
 	return 0;
 }
  
@@ -11,11 +11,11 @@
 #include "ddr3_cfg.h"
 #include <asm/arch/ddr3.h>
  
-static int ddr3_size;
 static struct pll_init_data ddr3_400 = DDR3_PLL_400;
  
-void ddr3_init(void)
+u32 ddr3_init(void)
 {
+	u32 ddr3_size;
 	char dimm_name[32];
  
 	if (~(readl(KS2_PLL_CNTRL_BASE + KS2_RSTCTRL_RSTYPE) & 0x1))
  
  
@@ -43,14 +43,12 @@
 		printf("DRAM: 4 GiB\n");
 		ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_4g);
 		ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_4g);
+	} else {
+		printf("Unknown SO-DIMM. Cannot configure DDR3\n");
+		while (1)
+			;
 	}
-}
  
-/**
- * ddr3_get_size - return ddr3 size in GiB
- */
-int ddr3_get_size(void)
-{
 	return ddr3_size;
 }
@@ -12,14 +12,13 @@
 #include <asm/arch/ddr3.h>
 #include <asm/arch/hardware.h>
  
-static int ddr3_size;
-
 struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
 struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
  
-void ddr3_init(void)
+u32 ddr3_init(void)
 {
 	char dimm_name[32];
+	u32 ddr3_size;
  
 	ddr3_get_dimm_params(dimm_name);
  
  
@@ -93,13 +92,7 @@
 	/* Apply the workaround for PG 1.0 and 1.1 Silicons */
 	if (cpu_revision() <= 1)
 		ddr3_err_reset_workaround();
-}
  
-/**
- * ddr3_get_size - return ddr3 size in GiB
- */
-int ddr3_get_size(void)
-{
 	return ddr3_size;
 }
@@ -11,29 +11,21 @@
 #include "ddr3_cfg.h"
 #include <asm/arch/ddr3.h>
  
-static int ddr3_size;
 static struct pll_init_data ddr3_400 = DDR3_PLL_400;
  
-void ddr3_init(void)
+u32 ddr3_init(void)
 {
 	init_pll(&ddr3_400);
  
 	/* No SO-DIMM, 2GB discreet DDR */
 	printf("DRAM: 2 GiB\n");
-	ddr3_size = 2;
  
 	/* Reset DDR3 PHY after PLL enabled */
 	ddr3_reset_ddrphy();
  
 	ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_2g);
 	ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_2g);
-}
  
-/**
- * ddr3_get_size - return ddr3 size in GiB
- */
-int ddr3_get_size(void)
-{
-	return ddr3_size;
+	return 2;
 }
...	...	@@ -263,17 +263,14 @@
263	263	}
264	264	#endif
265	265
266		-void ddr3_init_ecc(u32 base)
	266	+void ddr3_init_ecc(u32 base, u32 ddr3_size)
267	267	{
268		- u32 ddr3_size;
269		-
270	268	if (!ddr3_ecc_support_rmw(base)) {
271	269	ddr3_disable_ecc(base);
272	270	return;
273	271	}
274	272
275	273	ddr3_ecc_init_range(base);
276		- ddr3_size = ddr3_get_size();
277	274	ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size);
278	275
279	276	/* mapping DDR3 ECC system interrupt from CIC2 to GIC */
...	...	@@ -48,10 +48,9 @@
48	48	unsigned int sdrfc;
49	49	};
50	50
51		-void ddr3_init(void);
52		-int ddr3_get_size(void);
	51	+u32 ddr3_init(void);
53	52	void ddr3_reset_ddrphy(void);
54		-void ddr3_init_ecc(u32 base);
	53	+void ddr3_init_ecc(u32 base, u32 ddr3_size);
55	54	void ddr3_disable_ecc(u32 base);
56	55	void ddr3_check_ecc_int(u32 base);
57	56	int ddr3_ecc_support_rmw(u32 base);
...	...	@@ -35,12 +35,14 @@
35	35
36	36	int dram_init(void)
37	37	{
38		- ddr3_init();
	38	+ u32 ddr3_size;
39	39
	40	+ ddr3_size = ddr3_init();
	41	+
40	42	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
41	43	CONFIG_MAX_RAM_BANK_SIZE);
42	44	aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
43		- ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE);
	45	+ ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
44	46	return 0;
45	47	}
46	48
...	...	@@ -11,11 +11,11 @@
11	11	#include "ddr3_cfg.h"
12	12	#include <asm/arch/ddr3.h>
13	13
14		-static int ddr3_size;
15	14	static struct pll_init_data ddr3_400 = DDR3_PLL_400;
16	15
17		-void ddr3_init(void)
	16	+u32 ddr3_init(void)
18	17	{
	18	+ u32 ddr3_size;
19	19	char dimm_name[32];
20	20
21	21	if (~(readl(KS2_PLL_CNTRL_BASE + KS2_RSTCTRL_RSTYPE) & 0x1))
22	22
23	23
...	...	@@ -43,14 +43,12 @@
43	43	printf("DRAM: 4 GiB\n");
44	44	ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_4g);
45	45	ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_4g);
	46	+ } else {
	47	+ printf("Unknown SO-DIMM. Cannot configure DDR3\n");
	48	+ while (1)
	49	+ ;
46	50	}
47		-}
48	51
49		-/**
50		- * ddr3_get_size - return ddr3 size in GiB
51		- */
52		-int ddr3_get_size(void)
53		-{
54	52	return ddr3_size;
55	53	}
...	...	@@ -12,14 +12,13 @@
12	12	#include <asm/arch/ddr3.h>
13	13	#include <asm/arch/hardware.h>
14	14
15		-static int ddr3_size;
16		-
17	15	struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
18	16	struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
19	17
20		-void ddr3_init(void)
	18	+u32 ddr3_init(void)
21	19	{
22	20	char dimm_name[32];
	21	+ u32 ddr3_size;
23	22
24	23	ddr3_get_dimm_params(dimm_name);
25	24
26	25
...	...	@@ -93,13 +92,7 @@
93	92	/* Apply the workaround for PG 1.0 and 1.1 Silicons */
94	93	if (cpu_revision() <= 1)
95	94	ddr3_err_reset_workaround();
96		-}
97	95
98		-/**
99		- * ddr3_get_size - return ddr3 size in GiB
100		- */
101		-int ddr3_get_size(void)
102		-{
103	96	return ddr3_size;
104	97	}
...	...	@@ -11,29 +11,21 @@
11	11	#include "ddr3_cfg.h"
12	12	#include <asm/arch/ddr3.h>
13	13
14		-static int ddr3_size;
15	14	static struct pll_init_data ddr3_400 = DDR3_PLL_400;
16	15
17		-void ddr3_init(void)
	16	+u32 ddr3_init(void)
18	17	{
19	18	init_pll(&ddr3_400);
20	19
21	20	/* No SO-DIMM, 2GB discreet DDR */
22	21	printf("DRAM: 2 GiB\n");
23		- ddr3_size = 2;
24	22
25	23	/* Reset DDR3 PHY after PLL enabled */
26	24	ddr3_reset_ddrphy();
27	25
28	26	ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_2g);
29	27	ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_2g);
30		-}
31	28
32		-/**
33		- * ddr3_get_size - return ddr3 size in GiB
34		- */
35		-int ddr3_get_size(void)
36		-{
37		- return ddr3_size;
	29	+ return 2;
38	30	}