Eric Lee / smarc-uboot | Embedian Git Server

Commit 3163aaa63fced54bbd6fd190ece0f89b473076ab

Authored by Jagannadha Sutradharudu Teki 2014-01-11 17:43:11 +0800

Exists in master and in 50 other branches

sf: Add quad read/write commands support

This patch add quad commands support like
- QUAD_PAGE_PROGRAM => for write program
- QUAD_OUTPUT_FAST ->> for read program

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

Showing 5 changed files with 113 additions and 89 deletions Inline Diff

drivers/mtd/spi/sf_internal.h
drivers/mtd/spi/sf_ops.c
drivers/mtd/spi/sf_probe.c
include/spi.h
include/spi_flash.h

drivers/mtd/spi/sf_internal.h

Diff comments View file @ 3163aaa

 /*
  * SPI flash internal definitions
  *
  * Copyright (C) 2008 Atmel Corporation
  * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef _SF_INTERNAL_H_
 #define _SF_INTERNAL_H_
 #define SPI_FLASH_16MB_BOUN		0x1000000
 /* SECT flags */
 #define SECT_4K				(1 << 1)
 #define SECT_32K			(1 << 2)
 #define E_FSR				(1 << 3)
 /* Erase commands */
 #define CMD_ERASE_4K			0x20
 #define CMD_ERASE_32K			0x52
 #define CMD_ERASE_CHIP			0xc7
 #define CMD_ERASE_64K			0xd8
 /* Write commands */
 #define CMD_WRITE_STATUS		0x01
 #define CMD_PAGE_PROGRAM		0x02
 #define CMD_WRITE_DISABLE		0x04
 #define CMD_READ_STATUS			0x05
+#define CMD_QUAD_PAGE_PROGRAM		0x32
 #define CMD_READ_STATUS1		0x35
 #define CMD_WRITE_ENABLE		0x06
 #define CMD_READ_CONFIG			0x35
 #define CMD_FLAG_STATUS			0x70
 /* Read commands */
 #define CMD_READ_ARRAY_SLOW		0x03
 #define CMD_READ_ARRAY_FAST		0x0b
 #define CMD_READ_DUAL_OUTPUT_FAST	0x3b
 #define CMD_READ_DUAL_IO_FAST		0xbb
+#define CMD_READ_QUAD_OUTPUT_FAST	0x6b
 #define CMD_READ_ID			0x9f
 /* Bank addr access commands */
 #ifdef CONFIG_SPI_FLASH_BAR
 # define CMD_BANKADDR_BRWR		0x17
 # define CMD_BANKADDR_BRRD		0x16
 # define CMD_EXTNADDR_WREAR		0xC5
 # define CMD_EXTNADDR_RDEAR		0xC8
 #endif
 /* Common status */
 #define STATUS_WIP			0x01
 #define STATUS_PEC			0x80
 /* Flash timeout values */
 #define SPI_FLASH_PROG_TIMEOUT		(2 * CONFIG_SYS_HZ)
 #define SPI_FLASH_PAGE_ERASE_TIMEOUT	(5 * CONFIG_SYS_HZ)
 #define SPI_FLASH_SECTOR_ERASE_TIMEOUT	(10 * CONFIG_SYS_HZ)
 /* SST specific */
 #ifdef CONFIG_SPI_FLASH_SST
 # define SST_WP			0x01	/* Supports AAI word program */
 # define CMD_SST_BP		0x02    /* Byte Program */
 # define CMD_SST_AAI_WP		0xAD	/* Auto Address Incr Word Program */
 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
 		const void *buf);
 #endif
 /* Send a single-byte command to the device and read the response */
 int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
 /*
  * Send a multi-byte command to the device and read the response. Used
  * for flash array reads, etc.
  */
 int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
 		size_t cmd_len, void *data, size_t data_len);
 /*
  * Send a multi-byte command to the device followed by (optional)
  * data. Used for programming the flash array, etc.
  */
 int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
 		const void *data, size_t data_len);
 /* Flash erase(sectors) operation, support all possible erase commands */
 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
 /* Program the status register */
 int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
 /* Set quad enbale bit */
 int spi_flash_set_qeb(struct spi_flash *flash);
 /* Enable writing on the SPI flash */
 static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
 {
 	return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0);
 }
 /* Disable writing on the SPI flash */
 static inline int spi_flash_cmd_write_disable(struct spi_flash *flash)
 {
 	return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0);
 }
 /*
  * Send the read status command to the device and wait for the wip
  * (write-in-progress) bit to clear itself.
  */
 int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout);
 /*
  * Used for spi_flash write operation
  * - SPI claim
  * - spi_flash_cmd_write_enable
  * - spi_flash_cmd_write
  * - spi_flash_cmd_wait_ready
  * - SPI release
  */
 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
 		size_t cmd_len, const void *buf, size_t buf_len);
 /*
  * Flash write operation, support all possible write commands.
  * Write the requested data out breaking it up into multiple write
  * commands as needed per the write size.
  */
 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
 		size_t len, const void *buf);
 /*
  * Same as spi_flash_cmd_read() except it also claims/releases the SPI
  * bus. Used as common part of the ->read() operation.
  */
 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
 		size_t cmd_len, void *data, size_t data_len);
 /* Flash read operation, support all possible read commands */
 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
 		size_t len, void *data);
 #endif /* _SF_INTERNAL_H_ */

drivers/mtd/spi/sf_ops.c

Diff comments View file @ 3163aaa

1	/*	1	/*
2	* SPI flash operations	2	* SPI flash operations
3	*	3	*
4	* Copyright (C) 2008 Atmel Corporation	4	* Copyright (C) 2008 Atmel Corporation
5	* Copyright (C) 2010 Reinhard Meyer, EMK Elektronik	5	* Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
6	* Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.	6	* Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
7	*	7	*
8	* SPDX-License-Identifier: GPL-2.0+	8	* SPDX-License-Identifier: GPL-2.0+
9	*/	9	*/
10		10
11	#include <common.h>	11	#include <common.h>
12	#include <spi.h>	12	#include <spi.h>
13	#include <spi_flash.h>	13	#include <spi_flash.h>
14	#include <watchdog.h>	14	#include <watchdog.h>
15		15
16	#include "sf_internal.h"	16	#include "sf_internal.h"
17		17
18	static void spi_flash_addr(u32 addr, u8 *cmd)	18	static void spi_flash_addr(u32 addr, u8 *cmd)
19	{	19	{
20	/* cmd[0] is actual command */	20	/* cmd[0] is actual command */
21	cmd[1] = addr >> 16;	21	cmd[1] = addr >> 16;
22	cmd[2] = addr >> 8;	22	cmd[2] = addr >> 8;
23	cmd[3] = addr >> 0;	23	cmd[3] = addr >> 0;
24	}	24	}
25		25
26	int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)	26	int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
27	{	27	{
28	u8 cmd;	28	u8 cmd;
29	int ret;	29	int ret;
30		30
31	cmd = CMD_WRITE_STATUS;	31	cmd = CMD_WRITE_STATUS;
32	ret = spi_flash_write_common(flash, &cmd, 1, &sr, 1);	32	ret = spi_flash_write_common(flash, &cmd, 1, &sr, 1);
33	if (ret < 0) {	33	if (ret < 0) {
34	debug("SF: fail to write status register\n");	34	debug("SF: fail to write status register\n");
35	return ret;	35	return ret;
36	}	36	}
37		37
38	return 0;	38	return 0;
39	}	39	}
40		40
41	#ifdef CONFIG_SPI_FLASH_BAR	41	#ifdef CONFIG_SPI_FLASH_BAR
42	static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)	42	static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
43	{	43	{
44	u8 cmd;	44	u8 cmd;
45	int ret;	45	int ret;
46		46
47	if (flash->bank_curr == bank_sel) {	47	if (flash->bank_curr == bank_sel) {
48	debug("SF: not require to enable bank%d\n", bank_sel);	48	debug("SF: not require to enable bank%d\n", bank_sel);
49	return 0;	49	return 0;
50	}	50	}
51		51
52	cmd = flash->bank_write_cmd;	52	cmd = flash->bank_write_cmd;
53	ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);	53	ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
54	if (ret < 0) {	54	if (ret < 0) {
55	debug("SF: fail to write bank register\n");	55	debug("SF: fail to write bank register\n");
56	return ret;	56	return ret;
57	}	57	}
58	flash->bank_curr = bank_sel;	58	flash->bank_curr = bank_sel;
59		59
60	return 0;	60	return 0;
61	}	61	}
62		62
63	static int spi_flash_bank(struct spi_flash *flash, u32 offset)	63	static int spi_flash_bank(struct spi_flash *flash, u32 offset)
64	{	64	{
65	u8 bank_sel;	65	u8 bank_sel;
66	int ret;	66	int ret;
67		67
68	bank_sel = offset / SPI_FLASH_16MB_BOUN;	68	bank_sel = offset / SPI_FLASH_16MB_BOUN;
69		69
70	ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);	70	ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
71	if (ret) {	71	if (ret) {
72	debug("SF: fail to set bank%d\n", bank_sel);	72	debug("SF: fail to set bank%d\n", bank_sel);
73	return ret;	73	return ret;
74	}	74	}
75		75
76	return 0;	76	return 0;
77	}	77	}
78	#endif	78	#endif
79		79
80	int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)	80	int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
81	{	81	{
82	struct spi_slave *spi = flash->spi;	82	struct spi_slave *spi = flash->spi;
83	unsigned long timebase;	83	unsigned long timebase;
84	int ret;	84	int ret;
85	u8 status;	85	u8 status;
86	u8 check_status = 0x0;	86	u8 check_status = 0x0;
87	u8 poll_bit = STATUS_WIP;	87	u8 poll_bit = STATUS_WIP;
88	u8 cmd = flash->poll_cmd;	88	u8 cmd = flash->poll_cmd;
89		89
90	if (cmd == CMD_FLAG_STATUS) {	90	if (cmd == CMD_FLAG_STATUS) {
91	poll_bit = STATUS_PEC;	91	poll_bit = STATUS_PEC;
92	check_status = poll_bit;	92	check_status = poll_bit;
93	}	93	}
94		94
95	ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN);	95	ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN);
96	if (ret) {	96	if (ret) {
97	debug("SF: fail to read %s status register\n",	97	debug("SF: fail to read %s status register\n",
98	cmd == CMD_READ_STATUS ? "read" : "flag");	98	cmd == CMD_READ_STATUS ? "read" : "flag");
99	return ret;	99	return ret;
100	}	100	}
101		101
102	timebase = get_timer(0);	102	timebase = get_timer(0);
103	do {	103	do {
104	WATCHDOG_RESET();	104	WATCHDOG_RESET();
105		105
106	ret = spi_xfer(spi, 8, NULL, &status, 0);	106	ret = spi_xfer(spi, 8, NULL, &status, 0);
107	if (ret)	107	if (ret)
108	return -1;	108	return -1;
109		109
110	if ((status & poll_bit) == check_status)	110	if ((status & poll_bit) == check_status)
111	break;	111	break;
112		112
113	} while (get_timer(timebase) < timeout);	113	} while (get_timer(timebase) < timeout);
114		114
115	spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);	115	spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
116		116
117	if ((status & poll_bit) == check_status)	117	if ((status & poll_bit) == check_status)
118	return 0;	118	return 0;
119		119
120	/* Timed out */	120	/* Timed out */
121	debug("SF: time out!\n");	121	debug("SF: time out!\n");
122	return -1;	122	return -1;
123	}	123	}
124		124
125	int spi_flash_write_common(struct spi_flash flash, const u8 cmd,	125	int spi_flash_write_common(struct spi_flash flash, const u8 cmd,
126	size_t cmd_len, const void *buf, size_t buf_len)	126	size_t cmd_len, const void *buf, size_t buf_len)
127	{	127	{
128	struct spi_slave *spi = flash->spi;	128	struct spi_slave *spi = flash->spi;
129	unsigned long timeout = SPI_FLASH_PROG_TIMEOUT;	129	unsigned long timeout = SPI_FLASH_PROG_TIMEOUT;
130	int ret;	130	int ret;
131		131
132	if (buf == NULL)	132	if (buf == NULL)
133	timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;	133	timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
134		134
135	ret = spi_claim_bus(flash->spi);	135	ret = spi_claim_bus(flash->spi);
136	if (ret) {	136	if (ret) {
137	debug("SF: unable to claim SPI bus\n");	137	debug("SF: unable to claim SPI bus\n");
138	return ret;	138	return ret;
139	}	139	}
140		140
141	ret = spi_flash_cmd_write_enable(flash);	141	ret = spi_flash_cmd_write_enable(flash);
142	if (ret < 0) {	142	if (ret < 0) {
143	debug("SF: enabling write failed\n");	143	debug("SF: enabling write failed\n");
144	return ret;	144	return ret;
145	}	145	}
146		146
147	ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len);	147	ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len);
148	if (ret < 0) {	148	if (ret < 0) {
149	debug("SF: write cmd failed\n");	149	debug("SF: write cmd failed\n");
150	return ret;	150	return ret;
151	}	151	}
152		152
153	ret = spi_flash_cmd_wait_ready(flash, timeout);	153	ret = spi_flash_cmd_wait_ready(flash, timeout);
154	if (ret < 0) {	154	if (ret < 0) {
155	debug("SF: write %s timed out\n",	155	debug("SF: write %s timed out\n",
156	timeout == SPI_FLASH_PROG_TIMEOUT ?	156	timeout == SPI_FLASH_PROG_TIMEOUT ?
157	"program" : "page erase");	157	"program" : "page erase");
158	return ret;	158	return ret;
159	}	159	}
160		160
161	spi_release_bus(spi);	161	spi_release_bus(spi);
162		162
163	return ret;	163	return ret;
164	}	164	}
165		165
166	int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)	166	int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
167	{	167	{
168	u32 erase_size;	168	u32 erase_size;
169	u8 cmd[4];	169	u8 cmd[4];
170	int ret = -1;	170	int ret = -1;
171		171
172	erase_size = flash->erase_size;	172	erase_size = flash->erase_size;
173	if (offset % erase_size \|\| len % erase_size) {	173	if (offset % erase_size \|\| len % erase_size) {
174	debug("SF: Erase offset/length not multiple of erase size\n");	174	debug("SF: Erase offset/length not multiple of erase size\n");
175	return -1;	175	return -1;
176	}	176	}
177		177
178	cmd[0] = flash->erase_cmd;	178	cmd[0] = flash->erase_cmd;
179	while (len) {	179	while (len) {
180	#ifdef CONFIG_SPI_FLASH_BAR	180	#ifdef CONFIG_SPI_FLASH_BAR
181	ret = spi_flash_bank(flash, offset);	181	ret = spi_flash_bank(flash, offset);
182	if (ret < 0)	182	if (ret < 0)
183	return ret;	183	return ret;
184	#endif	184	#endif
185	spi_flash_addr(offset, cmd);	185	spi_flash_addr(offset, cmd);
186		186
187	debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],	187	debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
188	cmd[2], cmd[3], offset);	188	cmd[2], cmd[3], offset);
189		189
190	ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);	190	ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
191	if (ret < 0) {	191	if (ret < 0) {
192	debug("SF: erase failed\n");	192	debug("SF: erase failed\n");
193	break;	193	break;
194	}	194	}
195		195
196	offset += erase_size;	196	offset += erase_size;
197	len -= erase_size;	197	len -= erase_size;
198	}	198	}
199		199
200	return ret;	200	return ret;
201	}	201	}
202		202
203	int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,	203	int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
204	size_t len, const void *buf)	204	size_t len, const void *buf)
205	{	205	{
206	unsigned long byte_addr, page_size;	206	unsigned long byte_addr, page_size;
207	size_t chunk_len, actual;	207	size_t chunk_len, actual;
208	u8 cmd[4];	208	u8 cmd[4];
209	int ret = -1;	209	int ret = -1;
210		210
211	page_size = flash->page_size;	211	page_size = flash->page_size;
212		212
213	cmd[0] = CMD_PAGE_PROGRAM;	213	cmd[0] = flash->write_cmd;
214	for (actual = 0; actual < len; actual += chunk_len) {	214	for (actual = 0; actual < len; actual += chunk_len) {
215	#ifdef CONFIG_SPI_FLASH_BAR	215	#ifdef CONFIG_SPI_FLASH_BAR
216	ret = spi_flash_bank(flash, offset);	216	ret = spi_flash_bank(flash, offset);
217	if (ret < 0)	217	if (ret < 0)
218	return ret;	218	return ret;
219	#endif	219	#endif
220	byte_addr = offset % page_size;	220	byte_addr = offset % page_size;
221	chunk_len = min(len - actual, page_size - byte_addr);	221	chunk_len = min(len - actual, page_size - byte_addr);
222		222
223	if (flash->spi->max_write_size)	223	if (flash->spi->max_write_size)
224	chunk_len = min(chunk_len, flash->spi->max_write_size);	224	chunk_len = min(chunk_len, flash->spi->max_write_size);
225		225
226	spi_flash_addr(offset, cmd);	226	spi_flash_addr(offset, cmd);
227		227
228	debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",	228	debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
229	buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);	229	buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
230		230
231	ret = spi_flash_write_common(flash, cmd, sizeof(cmd),	231	ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
232	buf + actual, chunk_len);	232	buf + actual, chunk_len);
233	if (ret < 0) {	233	if (ret < 0) {
234	debug("SF: write failed\n");	234	debug("SF: write failed\n");
235	break;	235	break;
236	}	236	}
237		237
238	offset += chunk_len;	238	offset += chunk_len;
239	}	239	}
240		240
241	return ret;	241	return ret;
242	}	242	}
243		243
244	int spi_flash_read_common(struct spi_flash flash, const u8 cmd,	244	int spi_flash_read_common(struct spi_flash flash, const u8 cmd,
245	size_t cmd_len, void *data, size_t data_len)	245	size_t cmd_len, void *data, size_t data_len)
246	{	246	{
247	struct spi_slave *spi = flash->spi;	247	struct spi_slave *spi = flash->spi;
248	int ret;	248	int ret;
249		249
250	ret = spi_claim_bus(flash->spi);	250	ret = spi_claim_bus(flash->spi);
251	if (ret) {	251	if (ret) {
252	debug("SF: unable to claim SPI bus\n");	252	debug("SF: unable to claim SPI bus\n");
253	return ret;	253	return ret;
254	}	254	}
255		255
256	ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);	256	ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
257	if (ret < 0) {	257	if (ret < 0) {
258	debug("SF: read cmd failed\n");	258	debug("SF: read cmd failed\n");
259	return ret;	259	return ret;
260	}	260	}
261		261
262	spi_release_bus(spi);	262	spi_release_bus(spi);
263		263
264	return ret;	264	return ret;
265	}	265	}
266		266
267	int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,	267	int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
268	size_t len, void *data)	268	size_t len, void *data)
269	{	269	{
270	u8 cmd[5], bank_sel = 0;	270	u8 cmd[5], bank_sel = 0;
271	u32 remain_len, read_len;	271	u32 remain_len, read_len;
272	int ret = -1;	272	int ret = -1;
273		273
274	/* Handle memory-mapped SPI */	274	/* Handle memory-mapped SPI */
275	if (flash->memory_map) {	275	if (flash->memory_map) {
276	ret = spi_claim_bus(flash->spi);	276	ret = spi_claim_bus(flash->spi);
277	if (ret) {	277	if (ret) {
278	debug("SF: unable to claim SPI bus\n");	278	debug("SF: unable to claim SPI bus\n");
279	return ret;	279	return ret;
280	}	280	}
281	spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP);	281	spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP);
282	memcpy(data, flash->memory_map + offset, len);	282	memcpy(data, flash->memory_map + offset, len);
283	spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP_END);	283	spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
284	spi_release_bus(flash->spi);	284	spi_release_bus(flash->spi);
285	return 0;	285	return 0;
286	}	286	}
287		287
288	cmd[0] = flash->read_cmd;	288	cmd[0] = flash->read_cmd;
289	cmd[4] = 0x00;	289	cmd[4] = 0x00;
290		290
291	while (len) {	291	while (len) {
292	#ifdef CONFIG_SPI_FLASH_BAR	292	#ifdef CONFIG_SPI_FLASH_BAR
293	bank_sel = offset / SPI_FLASH_16MB_BOUN;	293	bank_sel = offset / SPI_FLASH_16MB_BOUN;
294		294
295	ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);	295	ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
296	if (ret) {	296	if (ret) {
297	debug("SF: fail to set bank%d\n", bank_sel);	297	debug("SF: fail to set bank%d\n", bank_sel);
298	return ret;	298	return ret;
299	}	299	}
300	#endif	300	#endif
301	remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1)) - offset;	301	remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1)) - offset;
302	if (len < remain_len)	302	if (len < remain_len)
303	read_len = len;	303	read_len = len;
304	else	304	else
305	read_len = remain_len;	305	read_len = remain_len;
306		306
307	spi_flash_addr(offset, cmd);	307	spi_flash_addr(offset, cmd);
308		308
309	ret = spi_flash_read_common(flash, cmd, sizeof(cmd),	309	ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
310	data, read_len);	310	data, read_len);
311	if (ret < 0) {	311	if (ret < 0) {
312	debug("SF: read failed\n");	312	debug("SF: read failed\n");
313	break;	313	break;
314	}	314	}
315		315
316	offset += read_len;	316	offset += read_len;
317	len -= read_len;	317	len -= read_len;
318	data += read_len;	318	data += read_len;
319	}	319	}
320		320
321	return ret;	321	return ret;
322	}	322	}
323		323
324	#ifdef CONFIG_SPI_FLASH_SST	324	#ifdef CONFIG_SPI_FLASH_SST
325	static int sst_byte_write(struct spi_flash flash, u32 offset, const void buf)	325	static int sst_byte_write(struct spi_flash flash, u32 offset, const void buf)
326	{	326	{
327	int ret;	327	int ret;
328	u8 cmd[4] = {	328	u8 cmd[4] = {
329	CMD_SST_BP,	329	CMD_SST_BP,
330	offset >> 16,	330	offset >> 16,
331	offset >> 8,	331	offset >> 8,
332	offset,	332	offset,
333	};	333	};
334		334
335	debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",	335	debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
336	spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset);	336	spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset);
337		337
338	ret = spi_flash_cmd_write_enable(flash);	338	ret = spi_flash_cmd_write_enable(flash);
339	if (ret)	339	if (ret)
340	return ret;	340	return ret;
341		341
342	ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf, 1);	342	ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf, 1);
343	if (ret)	343	if (ret)
344	return ret;	344	return ret;
345		345
346	return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);	346	return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
347	}	347	}
348		348
349	int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,	349	int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
350	const void *buf)	350	const void *buf)
351	{	351	{
352	size_t actual, cmd_len;	352	size_t actual, cmd_len;
353	int ret;	353	int ret;
354	u8 cmd[4];	354	u8 cmd[4];
355		355
356	ret = spi_claim_bus(flash->spi);	356	ret = spi_claim_bus(flash->spi);
357	if (ret) {	357	if (ret) {
358	debug("SF: Unable to claim SPI bus\n");	358	debug("SF: Unable to claim SPI bus\n");
359	return ret;	359	return ret;
360	}	360	}
361		361
362	/* If the data is not word aligned, write out leading single byte */	362	/* If the data is not word aligned, write out leading single byte */
363	actual = offset % 2;	363	actual = offset % 2;
364	if (actual) {	364	if (actual) {
365	ret = sst_byte_write(flash, offset, buf);	365	ret = sst_byte_write(flash, offset, buf);
366	if (ret)	366	if (ret)
367	goto done;	367	goto done;
368	}	368	}
369	offset += actual;	369	offset += actual;
370		370
371	ret = spi_flash_cmd_write_enable(flash);	371	ret = spi_flash_cmd_write_enable(flash);
372	if (ret)	372	if (ret)
373	goto done;	373	goto done;
374		374
375	cmd_len = 4;	375	cmd_len = 4;
376	cmd[0] = CMD_SST_AAI_WP;	376	cmd[0] = CMD_SST_AAI_WP;
377	cmd[1] = offset >> 16;	377	cmd[1] = offset >> 16;
378	cmd[2] = offset >> 8;	378	cmd[2] = offset >> 8;
379	cmd[3] = offset;	379	cmd[3] = offset;
380		380
381	for (; actual < len - 1; actual += 2) {	381	for (; actual < len - 1; actual += 2) {
382	debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",	382	debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
383	spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual,	383	spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual,
384	cmd[0], offset);	384	cmd[0], offset);
385		385
386	ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len,	386	ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len,
387	buf + actual, 2);	387	buf + actual, 2);
388	if (ret) {	388	if (ret) {
389	debug("SF: sst word program failed\n");	389	debug("SF: sst word program failed\n");
390	break;	390	break;
391	}	391	}
392		392
393	ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);	393	ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
394	if (ret)	394	if (ret)
395	break;	395	break;
396		396
397	cmd_len = 1;	397	cmd_len = 1;
398	offset += 2;	398	offset += 2;
399	}	399	}
400		400
401	if (!ret)	401	if (!ret)
402	ret = spi_flash_cmd_write_disable(flash);	402	ret = spi_flash_cmd_write_disable(flash);
403		403
404	/* If there is a single trailing byte, write it out */	404	/* If there is a single trailing byte, write it out */
405	if (!ret && actual != len)	405	if (!ret && actual != len)
406	ret = sst_byte_write(flash, offset, buf + actual);	406	ret = sst_byte_write(flash, offset, buf + actual);
407		407
408	done:	408	done:
409	debug("SF: sst: program %s %zu bytes @ 0x%zx\n",	409	debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
410	ret ? "failure" : "success", len, offset - actual);	410	ret ? "failure" : "success", len, offset - actual);
411		411
412	spi_release_bus(flash->spi);	412	spi_release_bus(flash->spi);
413	return ret;	413	return ret;
414	}	414	}
415	#endif	415	#endif
416		416

drivers/mtd/spi/sf_probe.c

Diff comments View file @ 3163aaa

 /*
  * SPI flash probing
  *
  * Copyright (C) 2008 Atmel Corporation
  * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
  * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <fdtdec.h>
 #include <malloc.h>
 #include <spi.h>
 #include <spi_flash.h>
 #include <asm/io.h>
 #include "sf_internal.h"
 DECLARE_GLOBAL_DATA_PTR;
 /**
  * struct spi_flash_params - SPI/QSPI flash device params structure
  *
  * @name:		Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
  * @jedec:		Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
  * @ext_jedec:		Device ext_jedec ID
  * @sector_size:	Sector size of this device
  * @nr_sectors:		No.of sectors on this device
  * @e_rd_cmd:		Enum list for read commands
  * @flags:		Importent param, for flash specific behaviour
  */
 struct spi_flash_params {
 	const char *name;
 	u32 jedec;
 	u16 ext_jedec;
 	u32 sector_size;
 	u32 nr_sectors;
 	u8 e_rd_cmd;
 	u16 flags;
 };
 static const struct spi_flash_params spi_flash_params_table[] = {
 #ifdef CONFIG_SPI_FLASH_ATMEL		/* ATMEL */
-	{"AT45DB011D",	   0x1f2200, 0x0,	64 * 1024,     4,	0,          SECT_4K},
+	{"AT45DB011D",	   0x1f2200, 0x0,	64 * 1024,     4,	0,		    SECT_4K},
-	{"AT45DB021D",	   0x1f2300, 0x0,	64 * 1024,     8,	0,          SECT_4K},
+	{"AT45DB021D",	   0x1f2300, 0x0,	64 * 1024,     8,	0,		    SECT_4K},
-	{"AT45DB041D",	   0x1f2400, 0x0,	64 * 1024,     8,	0,          SECT_4K},
+	{"AT45DB041D",	   0x1f2400, 0x0,	64 * 1024,     8,	0,		    SECT_4K},
-	{"AT45DB081D",	   0x1f2500, 0x0,	64 * 1024,    16,	0,          SECT_4K},
+	{"AT45DB081D",	   0x1f2500, 0x0,	64 * 1024,    16,	0,		    SECT_4K},
-	{"AT45DB161D",	   0x1f2600, 0x0,	64 * 1024,    32,	0,          SECT_4K},
+	{"AT45DB161D",	   0x1f2600, 0x0,	64 * 1024,    32,	0,		    SECT_4K},
-	{"AT45DB321D",	   0x1f2700, 0x0,	64 * 1024,    64,	0,          SECT_4K},
+	{"AT45DB321D",	   0x1f2700, 0x0,	64 * 1024,    64,	0,		    SECT_4K},
-	{"AT45DB641D",	   0x1f2800, 0x0,	64 * 1024,   128,	0,	    SECT_4K},
+	{"AT45DB641D",	   0x1f2800, 0x0,	64 * 1024,   128,	0,		    SECT_4K},
-	{"AT25DF321",      0x1f4701, 0x0,	64 * 1024,    64,	0,          SECT_4K},
+	{"AT25DF321",      0x1f4701, 0x0,	64 * 1024,    64,	0,		    SECT_4K},
 #endif
 #ifdef CONFIG_SPI_FLASH_EON		/* EON */
-	{"EN25Q32B",	   0x1c3016, 0x0,	64 * 1024,    64,	0,                0},
+	{"EN25Q32B",	   0x1c3016, 0x0,	64 * 1024,    64,	0,			  0},
-	{"EN25Q64",	   0x1c3017, 0x0,	64 * 1024,   128,	0,          SECT_4K},
+	{"EN25Q64",	   0x1c3017, 0x0,	64 * 1024,   128,	0,		    SECT_4K},
-	{"EN25Q128B",	   0x1c3018, 0x0,       64 * 1024,   256,	0,                0},
+	{"EN25Q128B",	   0x1c3018, 0x0,       64 * 1024,   256,	0,			  0},
-	{"EN25S64",	   0x1c3817, 0x0,	64 * 1024,   128,	0,	          0},
+	{"EN25S64",	   0x1c3817, 0x0,	64 * 1024,   128,	0,			  0},
 #endif
 #ifdef CONFIG_SPI_FLASH_GIGADEVICE	/* GIGADEVICE */
-	{"GD25Q64B",	   0xc84017, 0x0,	64 * 1024,   128,	0,          SECT_4K},
+	{"GD25Q64B",	   0xc84017, 0x0,	64 * 1024,   128,	0,		    SECT_4K},
-	{"GD25LQ32",	   0xc86016, 0x0,	64 * 1024,    64,	0,          SECT_4K},
+	{"GD25LQ32",	   0xc86016, 0x0,	64 * 1024,    64,	0,		    SECT_4K},
 #endif
 #ifdef CONFIG_SPI_FLASH_MACRONIX	/* MACRONIX */
-	{"MX25L2006E",	   0xc22012, 0x0,	64 * 1024,     4,	0,                0},
+	{"MX25L2006E",	   0xc22012, 0x0,	64 * 1024,     4,	0,			  0},
-	{"MX25L4005",	   0xc22013, 0x0,	64 * 1024,     8,	0,                0},
+	{"MX25L4005",	   0xc22013, 0x0,	64 * 1024,     8,	0,			  0},
-	{"MX25L8005",	   0xc22014, 0x0,	64 * 1024,    16,	0,                0},
+	{"MX25L8005",	   0xc22014, 0x0,	64 * 1024,    16,	0,			  0},
-	{"MX25L1605D",	   0xc22015, 0x0,	64 * 1024,    32,	0,                0},
+	{"MX25L1605D",	   0xc22015, 0x0,	64 * 1024,    32,	0,			  0},
-	{"MX25L3205D",	   0xc22016, 0x0,	64 * 1024,    64,	0,                0},
+	{"MX25L3205D",	   0xc22016, 0x0,	64 * 1024,    64,	0,			  0},
-	{"MX25L6405D",	   0xc22017, 0x0,	64 * 1024,   128,	0,                0},
+	{"MX25L6405D",	   0xc22017, 0x0,	64 * 1024,   128,	0,			  0},
-	{"MX25L12805",	   0xc22018, 0x0,	64 * 1024,   256,	0,                0},
+	{"MX25L12805",	   0xc22018, 0x0,	64 * 1024,   256,	0,			  0},
-	{"MX25L25635F",	   0xc22019, 0x0,	64 * 1024,   512,	0,                0},
+	{"MX25L25635F",	   0xc22019, 0x0,	64 * 1024,   512,	0,			  0},
-	{"MX25L51235F",	   0xc2201a, 0x0,	64 * 1024,  1024,	0,                0},
+	{"MX25L51235F",	   0xc2201a, 0x0,	64 * 1024,  1024,	0,			  0},
-	{"MX25L12855E",	   0xc22618, 0x0,	64 * 1024,   256,	0,                0},
+	{"MX25L12855E",	   0xc22618, 0x0,	64 * 1024,   256,	0,			  0},
 #endif
 #ifdef CONFIG_SPI_FLASH_SPANSION	/* SPANSION */
-	{"S25FL008A",	   0x010213, 0x0,	64 * 1024,    16,	0,                0},
+	{"S25FL008A",	   0x010213, 0x0,	64 * 1024,    16,	0,			  0},
-	{"S25FL016A",	   0x010214, 0x0,	64 * 1024,    32,	0,                0},
+	{"S25FL016A",	   0x010214, 0x0,	64 * 1024,    32,	0,			  0},
-	{"S25FL032A",	   0x010215, 0x0,	64 * 1024,    64,	0,                0},
+	{"S25FL032A",	   0x010215, 0x0,	64 * 1024,    64,	0,			  0},
-	{"S25FL064A",	   0x010216, 0x0,	64 * 1024,   128,	0,                0},
+	{"S25FL064A",	   0x010216, 0x0,	64 * 1024,   128,	0,			  0},
-	{"S25FL128P_256K", 0x012018, 0x0300,   256 * 1024,    64,	0,                0},
+	{"S25FL128P_256K", 0x012018, 0x0300,   256 * 1024,    64,	0,			  0},
-	{"S25FL128P_64K",  0x012018, 0x0301,    64 * 1024,   256,	0,                0},
+	{"S25FL128P_64K",  0x012018, 0x0301,    64 * 1024,   256,	0,			  0},
-	{"S25FL032P",	   0x010215, 0x4d00,    64 * 1024,    64,	0,                0},
+	{"S25FL032P",	   0x010215, 0x4d00,    64 * 1024,    64,	0,			  0},
-	{"S25FL064P",	   0x010216, 0x4d00,    64 * 1024,   128,	0,                0},
+	{"S25FL064P",	   0x010216, 0x4d00,    64 * 1024,   128,	0,			  0},
-	{"S25FL128S_64K",  0x012018, 0x4d01,    64 * 1024,   256,	0,	          0},
+	{"S25FL128S_64K",  0x012018, 0x4d01,    64 * 1024,   256,	0,			  0},
-	{"S25FL256S_256K", 0x010219, 0x4d00,    64 * 1024,   512, RD_EXTN,		  0},
+	{"S25FL256S_256K", 0x010219, 0x4d00,    64 * 1024,   512, RD_FULL,		     WR_QPP},
-	{"S25FL256S_64K",  0x010219, 0x4d01,	64 * 1024,   512, RD_EXTN,		  0},
+	{"S25FL256S_64K",  0x010219, 0x4d01,	64 * 1024,   512, RD_FULL,		     WR_QPP},
-	{"S25FL512S_256K", 0x010220, 0x4d00,    64 * 1024,  1024,	0,                0},
+	{"S25FL512S_256K", 0x010220, 0x4d00,    64 * 1024,  1024,	0,			  0},
-	{"S25FL512S_64K",  0x010220, 0x4d01,    64 * 1024,  1024,	0,                0},
+	{"S25FL512S_64K",  0x010220, 0x4d01,    64 * 1024,  1024,	0,			  0},
 #endif
 #ifdef CONFIG_SPI_FLASH_STMICRO		/* STMICRO */
-	{"M25P10",	   0x202011, 0x0,       32 * 1024,     4,	0,                0},
+	{"M25P10",	   0x202011, 0x0,	32 * 1024,     4,	0,			  0},
-	{"M25P20",	   0x202012, 0x0,       64 * 1024,     4,	0,                0},
+	{"M25P20",	   0x202012, 0x0,       64 * 1024,     4,	0,			  0},
-	{"M25P40",	   0x202013, 0x0,       64 * 1024,     8,	0,                0},
+	{"M25P40",	   0x202013, 0x0,       64 * 1024,     8,	0,			  0},
-	{"M25P80",	   0x202014, 0x0,       64 * 1024,    16,	0,                0},
+	{"M25P80",	   0x202014, 0x0,       64 * 1024,    16,	0,			  0},
-	{"M25P16",	   0x202015, 0x0,       64 * 1024,    32,	0,                0},
+	{"M25P16",	   0x202015, 0x0,       64 * 1024,    32,	0,			  0},
-	{"M25P32",	   0x202016, 0x0,       64 * 1024,    64,	0,                0},
+	{"M25P32",	   0x202016, 0x0,       64 * 1024,    64,	0,			  0},
-	{"M25P64",	   0x202017, 0x0,       64 * 1024,   128,	0,                0},
+	{"M25P64",	   0x202017, 0x0,       64 * 1024,   128,	0,			  0},
-	{"M25P128",	   0x202018, 0x0,      256 * 1024,    64,	0,                0},
+	{"M25P128",	   0x202018, 0x0,      256 * 1024,    64,	0,			  0},
-	{"N25Q32",	   0x20ba16, 0x0,       64 * 1024,    64,	0,          SECT_4K},
+	{"N25Q32",	   0x20ba16, 0x0,       64 * 1024,    64,	0,		    SECT_4K},
-	{"N25Q32A",	   0x20bb16, 0x0,       64 * 1024,    64,	0,          SECT_4K},
+	{"N25Q32A",	   0x20bb16, 0x0,       64 * 1024,    64,	0,		    SECT_4K},
-	{"N25Q64",	   0x20ba17, 0x0,       64 * 1024,   128,	0,          SECT_4K},
+	{"N25Q64",	   0x20ba17, 0x0,       64 * 1024,   128,	0,		    SECT_4K},
-	{"N25Q64A",	   0x20bb17, 0x0,       64 * 1024,   128,	0,          SECT_4K},
+	{"N25Q64A",	   0x20bb17, 0x0,       64 * 1024,   128,	0,		    SECT_4K},
-	{"N25Q128",	   0x20ba18, 0x0,       64 * 1024,   256,	0,          SECT_4K},
+	{"N25Q128",	   0x20ba18, 0x0,       64 * 1024,   256,	0,		    SECT_4K},
-	{"N25Q128A",	   0x20bb18, 0x0,       64 * 1024,   256,	0,          SECT_4K},
+	{"N25Q128A",	   0x20bb18, 0x0,       64 * 1024,   256,	0,		    SECT_4K},
-	{"N25Q256",	   0x20ba19, 0x0,       64 * 1024,   512,	0,          SECT_4K},
+	{"N25Q256",	   0x20ba19, 0x0,       64 * 1024,   512,	0,		    SECT_4K},
-	{"N25Q256A",	   0x20bb19, 0x0,       64 * 1024,   512,	0,          SECT_4K},
+	{"N25Q256A",	   0x20bb19, 0x0,       64 * 1024,   512,	0,		    SECT_4K},
-	{"N25Q512",	   0x20ba20, 0x0,       64 * 1024,  1024,       0,  E_FSR | SECT_4K},
+	{"N25Q512",	   0x20ba20, 0x0,       64 * 1024,  1024,       0,	    E_FSR | SECT_4K},
-	{"N25Q512A",	   0x20bb20, 0x0,       64 * 1024,  1024,       0,  E_FSR | SECT_4K},
+	{"N25Q512A",	   0x20bb20, 0x0,       64 * 1024,  1024,       0,	    E_FSR | SECT_4K},
-	{"N25Q1024",	   0x20ba21, 0x0,       64 * 1024,  2048,       0,  E_FSR | SECT_4K},
+	{"N25Q1024",	   0x20ba21, 0x0,       64 * 1024,  2048,       0,	    E_FSR | SECT_4K},
-	{"N25Q1024A",	   0x20bb21, 0x0,       64 * 1024,  2048,       0,  E_FSR | SECT_4K},
+	{"N25Q1024A",	   0x20bb21, 0x0,       64 * 1024,  2048,	0,	    E_FSR | SECT_4K},
 #endif
 #ifdef CONFIG_SPI_FLASH_SST		/* SST */
-	{"SST25VF040B",	   0xbf258d, 0x0,	64 * 1024,     8,       0, SECT_4K | SST_WP},
+	{"SST25VF040B",	   0xbf258d, 0x0,	64 * 1024,     8,	0,          SECT_4K | SST_WP},
-	{"SST25VF080B",	   0xbf258e, 0x0,	64 * 1024,    16,	0, SECT_4K | SST_WP},
+	{"SST25VF080B",	   0xbf258e, 0x0,	64 * 1024,    16,	0,	    SECT_4K | SST_WP},
-	{"SST25VF016B",	   0xbf2541, 0x0,	64 * 1024,    32,	0, SECT_4K | SST_WP},
+	{"SST25VF016B",	   0xbf2541, 0x0,	64 * 1024,    32,	0,	    SECT_4K | SST_WP},
-	{"SST25VF032B",	   0xbf254a, 0x0,	64 * 1024,    64,	0, SECT_4K | SST_WP},
+	{"SST25VF032B",	   0xbf254a, 0x0,	64 * 1024,    64,	0,	    SECT_4K | SST_WP},
-	{"SST25VF064C",	   0xbf254b, 0x0,	64 * 1024,   128,	0,          SECT_4K},
+	{"SST25VF064C",	   0xbf254b, 0x0,	64 * 1024,   128,	0,		     SECT_4K},
-	{"SST25WF512",	   0xbf2501, 0x0,	64 * 1024,     1,       0, SECT_4K | SST_WP},
+	{"SST25WF512",	   0xbf2501, 0x0,	64 * 1024,     1,	0,	    SECT_4K | SST_WP},
-	{"SST25WF010",	   0xbf2502, 0x0,	64 * 1024,     2,       0, SECT_4K | SST_WP},
+	{"SST25WF010",	   0xbf2502, 0x0,	64 * 1024,     2,       0,          SECT_4K | SST_WP},
-	{"SST25WF020",	   0xbf2503, 0x0,	64 * 1024,     4,       0, SECT_4K | SST_WP},
+	{"SST25WF020",	   0xbf2503, 0x0,	64 * 1024,     4,       0,	    SECT_4K | SST_WP},
-	{"SST25WF040",	   0xbf2504, 0x0,	64 * 1024,     8,       0, SECT_4K | SST_WP},
+	{"SST25WF040",	   0xbf2504, 0x0,	64 * 1024,     8,       0,	    SECT_4K | SST_WP},
-	{"SST25WF080",	   0xbf2505, 0x0,	64 * 1024,    16,       0, SECT_4K | SST_WP},
+	{"SST25WF080",	   0xbf2505, 0x0,	64 * 1024,    16,       0,	    SECT_4K | SST_WP},
 #endif
 #ifdef CONFIG_SPI_FLASH_WINBOND		/* WINBOND */
-	{"W25P80",	   0xef2014, 0x0,	64 * 1024,    16,	0,		  0},
+	{"W25P80",	   0xef2014, 0x0,	64 * 1024,    16,	0,		           0},
-	{"W25P16",	   0xef2015, 0x0,	64 * 1024,    32,	0,		  0},
+	{"W25P16",	   0xef2015, 0x0,	64 * 1024,    32,	0,		           0},
-	{"W25P32",	   0xef2016, 0x0,	64 * 1024,    64,	0,		  0},
+	{"W25P32",	   0xef2016, 0x0,	64 * 1024,    64,	0,		           0},
-	{"W25X40",	   0xef3013, 0x0,	64 * 1024,     8,	0,	    SECT_4K},
+	{"W25X40",	   0xef3013, 0x0,	64 * 1024,     8,	0,		     SECT_4K},
-	{"W25X16",	   0xef3015, 0x0,	64 * 1024,    32,	0,          SECT_4K},
+	{"W25X16",	   0xef3015, 0x0,	64 * 1024,    32,	0,		     SECT_4K},
-	{"W25X32",	   0xef3016, 0x0,	64 * 1024,    64,	0,          SECT_4K},
+	{"W25X32",	   0xef3016, 0x0,	64 * 1024,    64,	0,		     SECT_4K},
-	{"W25X64",	   0xef3017, 0x0,	64 * 1024,   128,	0,          SECT_4K},
+	{"W25X64",	   0xef3017, 0x0,	64 * 1024,   128,	0,		     SECT_4K},
-	{"W25Q80BL",	   0xef4014, 0x0,	64 * 1024,    16,	0,          SECT_4K},
+	{"W25Q80BL",	   0xef4014, 0x0,	64 * 1024,    16,	0,		     SECT_4K},
-	{"W25Q16CL",	   0xef4015, 0x0,	64 * 1024,    32,	0,          SECT_4K},
+	{"W25Q16CL",	   0xef4015, 0x0,	64 * 1024,    32,	0,		     SECT_4K},
-	{"W25Q32BV",	   0xef4016, 0x0,	64 * 1024,    64,	0,          SECT_4K},
+	{"W25Q32BV",	   0xef4016, 0x0,	64 * 1024,    64,	0,		     SECT_4K},
-	{"W25Q64CV",	   0xef4017, 0x0,	64 * 1024,   128,	0,          SECT_4K},
+	{"W25Q64CV",	   0xef4017, 0x0,	64 * 1024,   128,	0,		     SECT_4K},
-	{"W25Q128BV",	   0xef4018, 0x0,	64 * 1024,   256,	0,          SECT_4K},
+	{"W25Q128BV",	   0xef4018, 0x0,	64 * 1024,   256,	0,		     SECT_4K},
-	{"W25Q256",	   0xef4019, 0x0,	64 * 1024,   512,	0,          SECT_4K},
+	{"W25Q256",	   0xef4019, 0x0,	64 * 1024,   512,	0,		     SECT_4K},
-	{"W25Q80BW",	   0xef5014, 0x0,	64 * 1024,    16,	0,          SECT_4K},
+	{"W25Q80BW",	   0xef5014, 0x0,	64 * 1024,    16,	0,		     SECT_4K},
-	{"W25Q16DW",	   0xef6015, 0x0,	64 * 1024,    32,	0,          SECT_4K},
+	{"W25Q16DW",	   0xef6015, 0x0,	64 * 1024,    32,	0,		     SECT_4K},
-	{"W25Q32DW",	   0xef6016, 0x0,	64 * 1024,    64,	0,          SECT_4K},
+	{"W25Q32DW",	   0xef6016, 0x0,	64 * 1024,    64,	0,		     SECT_4K},
-	{"W25Q64DW",	   0xef6017, 0x0,	64 * 1024,   128,	0,          SECT_4K},
+	{"W25Q64DW",	   0xef6017, 0x0,	64 * 1024,   128,	0,		     SECT_4K},
-	{"W25Q128FW",	   0xef6018, 0x0,	64 * 1024,   256,	0,          SECT_4K},
+	{"W25Q128FW",	   0xef6018, 0x0,	64 * 1024,   256,	0,		     SECT_4K},
 #endif
 	/*
 	 * Note:
 	 * Below paired flash devices has similar spi_flash params.
 	 * (S25FL129P_64K, S25FL128S_64K)
 	 * (W25Q80BL, W25Q80BV)
 	 * (W25Q16CL, W25Q16DV)
 	 * (W25Q32BV, W25Q32FV_SPI)
 	 * (W25Q64CV, W25Q64FV_SPI)
 	 * (W25Q128BV, W25Q128FV_SPI)
 	 * (W25Q32DW, W25Q32FV_QPI)
 	 * (W25Q64DW, W25Q64FV_QPI)
 	 * (W25Q128FW, W25Q128FV_QPI)
 	 */
 };
 /* Read commands array */
 static u8 spi_read_cmds_array[] = {
 	CMD_READ_ARRAY_SLOW,
 	CMD_READ_DUAL_OUTPUT_FAST,
 	CMD_READ_DUAL_IO_FAST,
+	CMD_READ_QUAD_OUTPUT_FAST,
 };
 static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
 		u8 *idcode)
 {
 	const struct spi_flash_params *params;
 	struct spi_flash *flash;
 	int i;
 	u8 cmd;
 	u16 jedec = idcode[1] << 8 | idcode[2];
 	u16 ext_jedec = idcode[3] << 8 | idcode[4];
 	/* Get the flash id (jedec = manuf_id + dev_id, ext_jedec) */
 	for (i = 0; i < ARRAY_SIZE(spi_flash_params_table); i++) {
 		params = &spi_flash_params_table[i];
 		if ((params->jedec >> 16) == idcode[0]) {
 			if ((params->jedec & 0xFFFF) == jedec) {
 				if (params->ext_jedec == 0)
 					break;
 				else if (params->ext_jedec == ext_jedec)
 					break;
 			}
 		}
 	}
 	if (i == ARRAY_SIZE(spi_flash_params_table)) {
 		printf("SF: Unsupported flash IDs: ");
 		printf("manuf %02x, jedec %04x, ext_jedec %04x\n",
 		       idcode[0], jedec, ext_jedec);
 		return NULL;
 	}
 	flash = malloc(sizeof(*flash));
 	if (!flash) {
 		debug("SF: Failed to allocate spi_flash\n");
 		return NULL;
 	}
 	memset(flash, '\0', sizeof(*flash));
 	/* Assign spi data */
 	flash->spi = spi;
 	flash->name = params->name;
 	flash->memory_map = spi->memory_map;
 	/* Assign spi_flash ops */
 	flash->write = spi_flash_cmd_write_ops;
 #ifdef CONFIG_SPI_FLASH_SST
 	if (params->flags & SST_WP)
 		flash->write = sst_write_wp;
 #endif
 	flash->erase = spi_flash_cmd_erase_ops;
 	flash->read = spi_flash_cmd_read_ops;
 	/* Compute the flash size */
 	flash->page_size = (ext_jedec == 0x4d00) ? 512 : 256;
 	flash->sector_size = params->sector_size;
 	flash->size = flash->sector_size * params->nr_sectors;
 	/* Compute erase sector and command */
 	if (params->flags & SECT_4K) {
 		flash->erase_cmd = CMD_ERASE_4K;
 		flash->erase_size = 4096;
 	} else if (params->flags & SECT_32K) {
 		flash->erase_cmd = CMD_ERASE_32K;
 		flash->erase_size = 32768;
 	} else {
 		flash->erase_cmd = CMD_ERASE_64K;
 		flash->erase_size = flash->sector_size;
 	}
 	/* Look for the fastest read cmd */
 	cmd = fls(params->e_rd_cmd & flash->spi->op_mode_rx);
 	if (cmd) {
 		cmd = spi_read_cmds_array[cmd - 1];
 		flash->read_cmd = cmd;
 	} else {
 		/* Go for for default supported read cmd */
 		flash->read_cmd = CMD_READ_ARRAY_FAST;
 	}
+	/* Not require to look for fastest only two write cmds yet */
+	if (params->flags & WR_QPP && flash->spi->op_mode_tx & SPI_OPM_TX_QPP)
+		flash->write_cmd = CMD_QUAD_PAGE_PROGRAM;
+	else
+		/* Go for default supported write cmd */
+		flash->write_cmd = CMD_PAGE_PROGRAM;
 	/* Poll cmd seclection */
 	flash->poll_cmd = CMD_READ_STATUS;
 #ifdef CONFIG_SPI_FLASH_STMICRO
 	if (params->flags & E_FSR)
 		flash->poll_cmd = CMD_FLAG_STATUS;
 #endif
 	/* Configure the BAR - discover bank cmds and read current bank */
 #ifdef CONFIG_SPI_FLASH_BAR
 	u8 curr_bank = 0;
 	if (flash->size > SPI_FLASH_16MB_BOUN) {
 		flash->bank_read_cmd = (idcode[0] == 0x01) ?
 					CMD_BANKADDR_BRRD : CMD_EXTNADDR_RDEAR;
 		flash->bank_write_cmd = (idcode[0] == 0x01) ?
 					CMD_BANKADDR_BRWR : CMD_EXTNADDR_WREAR;
 		if (spi_flash_read_common(flash, &flash->bank_read_cmd, 1,
 					  &curr_bank, 1)) {
 			debug("SF: fail to read bank addr register\n");
 			return NULL;
 		}
 		flash->bank_curr = curr_bank;
 	} else {
 		flash->bank_curr = curr_bank;
 	}
 #endif
 	/* Flash powers up read-only, so clear BP# bits */
 #if defined(CONFIG_SPI_FLASH_ATMEL) || \
 	defined(CONFIG_SPI_FLASH_MACRONIX) || \
 	defined(CONFIG_SPI_FLASH_SST)
 		spi_flash_cmd_write_status(flash, 0);
 #endif
 	return flash;
 }
 #ifdef CONFIG_OF_CONTROL
 int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
 {
 	fdt_addr_t addr;
 	fdt_size_t size;
 	int node;
 	/* If there is no node, do nothing */
 	node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH);
 	if (node < 0)
 		return 0;
 	addr = fdtdec_get_addr_size(blob, node, "memory-map", &size);
 	if (addr == FDT_ADDR_T_NONE) {
 		debug("%s: Cannot decode address\n", __func__);
 		return 0;
 	}
 	if (flash->size != size) {
 		debug("%s: Memory map must cover entire device\n", __func__);
 		return -1;
 	}
 	flash->memory_map = map_sysmem(addr, size);
 	return 0;
 }
 #endif /* CONFIG_OF_CONTROL */
 static struct spi_flash *spi_flash_probe_slave(struct spi_slave *spi)
 {
 	struct spi_flash *flash = NULL;
 	u8 idcode[5];
 	int ret;
 	/* Setup spi_slave */
 	if (!spi) {
 		printf("SF: Failed to set up slave\n");
 		return NULL;
 	}
 	/* Claim spi bus */
 	ret = spi_claim_bus(spi);
 	if (ret) {
 		debug("SF: Failed to claim SPI bus: %d\n", ret);
 		goto err_claim_bus;
 	}
 	/* Read the ID codes */
 	ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
 	if (ret) {
 		printf("SF: Failed to get idcodes\n");
 		goto err_read_id;
 	}
 #ifdef DEBUG
 	printf("SF: Got idcodes\n");
 	print_buffer(0, idcode, 1, sizeof(idcode), 0);
 #endif
 	/* Validate params from spi_flash_params table */
 	flash = spi_flash_validate_params(spi, idcode);
 	if (!flash)
 		goto err_read_id;
 #ifdef CONFIG_OF_CONTROL
 	if (spi_flash_decode_fdt(gd->fdt_blob, flash)) {
 		debug("SF: FDT decode error\n");
 		goto err_read_id;
 	}
 #endif
 #ifndef CONFIG_SPL_BUILD
 	printf("SF: Detected %s with page size ", flash->name);
 	print_size(flash->page_size, ", erase size ");
 	print_size(flash->erase_size, ", total ");
 	print_size(flash->size, "");
 	if (flash->memory_map)
 		printf(", mapped at %p", flash->memory_map);
 	puts("\n");
 #endif
 #ifndef CONFIG_SPI_FLASH_BAR
 	if (flash->size > SPI_FLASH_16MB_BOUN) {
 		puts("SF: Warning - Only lower 16MiB accessible,");
 		puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
 	}
 #endif
 	/* Release spi bus */
 	spi_release_bus(spi);
 	return flash;
 err_read_id:
 	spi_release_bus(spi);
 err_claim_bus:
 	spi_free_slave(spi);
 	return NULL;
 }
 struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
 		unsigned int max_hz, unsigned int spi_mode)
 {
 	struct spi_slave *spi;
 	spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
 	return spi_flash_probe_slave(spi);
 }
 #ifdef CONFIG_OF_SPI_FLASH
 struct spi_flash *spi_flash_probe_fdt(const void *blob, int slave_node,
 				      int spi_node)
 {
 	struct spi_slave *spi;
 	spi = spi_setup_slave_fdt(blob, slave_node, spi_node);
 	return spi_flash_probe_slave(spi);
 }
 #endif
 void spi_flash_free(struct spi_flash *flash)
 {
 	spi_free_slave(flash->spi);
 	free(flash);
 }

include/spi.h

Diff comments View file @ 3163aaa

 /*
  * Common SPI Interface: Controller-specific definitions
  *
  * (C) Copyright 2001
  * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef _SPI_H_
 #define _SPI_H_
 /* SPI mode flags */
 #define	SPI_CPHA	0x01			/* clock phase */
 #define	SPI_CPOL	0x02			/* clock polarity */
 #define	SPI_MODE_0	(0|0)			/* (original MicroWire) */
 #define	SPI_MODE_1	(0|SPI_CPHA)
 #define	SPI_MODE_2	(SPI_CPOL|0)
 #define	SPI_MODE_3	(SPI_CPOL|SPI_CPHA)
 #define	SPI_CS_HIGH	0x04			/* CS active high */
 #define	SPI_LSB_FIRST	0x08			/* per-word bits-on-wire */
 #define	SPI_3WIRE	0x10			/* SI/SO signals shared */
 #define	SPI_LOOP	0x20			/* loopback mode */
 #define	SPI_SLAVE	0x40			/* slave mode */
 #define	SPI_PREAMBLE	0x80			/* Skip preamble bytes */
 /* SPI transfer flags */
 #define SPI_XFER_BEGIN		0x01	/* Assert CS before transfer */
 #define SPI_XFER_END		0x02	/* Deassert CS after transfer */
 #define SPI_XFER_MMAP		0x08	/* Memory Mapped start */
 #define SPI_XFER_MMAP_END	0x10	/* Memory Mapped End */
 #define SPI_XFER_ONCE		(SPI_XFER_BEGIN | SPI_XFER_END)
+/* SPI TX operation modes */
+#define SPI_OPM_TX_QPP		1 << 0
 /* SPI RX operation modes */
 #define SPI_OPM_RX_AS		1 << 0
 #define SPI_OPM_RX_DOUT		1 << 1
 #define SPI_OPM_RX_DIO		1 << 2
-#define SPI_OPM_RX_EXTN		SPI_OPM_RX_AS | SPI_OPM_RX_DOUT | SPI_OPM_RX_DIO
+#define SPI_OPM_RX_QOF		1 << 3
+#define SPI_OPM_RX_EXTN		SPI_OPM_RX_AS | SPI_OPM_RX_DOUT | \
+				SPI_OPM_RX_DIO | SPI_OPM_RX_QOF
 /* Header byte that marks the start of the message */
 #define SPI_PREAMBLE_END_BYTE	0xec
 #define SPI_DEFAULT_WORDLEN 8
 /**
  * struct spi_slave - Representation of a SPI slave
  *
  * Drivers are expected to extend this with controller-specific data.
  *
  * @bus:		ID of the bus that the slave is attached to.
  * @cs:			ID of the chip select connected to the slave.
  * @op_mode_rx:		SPI RX operation mode.
+ * @op_mode_tx:		SPI TX operation mode.
  * @wordlen:		Size of SPI word in number of bits
  * @max_write_size:	If non-zero, the maximum number of bytes which can
  *			be written at once, excluding command bytes.
  * @memory_map:		Address of read-only SPI flash access.
  */
 struct spi_slave {
 	unsigned int bus;
 	unsigned int cs;
 	u8 op_mode_rx;
+	u8 op_mode_tx;
 	unsigned int wordlen;
 	unsigned int max_write_size;
 	void *memory_map;
 };
 /**
  * Initialization, must be called once on start up.
  *
  * TODO: I don't think we really need this.
  */
 void spi_init(void);
 /**
  * spi_do_alloc_slave - Allocate a new SPI slave (internal)
  *
  * Allocate and zero all fields in the spi slave, and set the bus/chip
  * select. Use the helper macro spi_alloc_slave() to call this.
  *
  * @offset:	Offset of struct spi_slave within slave structure.
  * @size:	Size of slave structure.
  * @bus:	Bus ID of the slave chip.
  * @cs:		Chip select ID of the slave chip on the specified bus.
  */
 void *spi_do_alloc_slave(int offset, int size, unsigned int bus,
 			 unsigned int cs);
 /**
  * spi_alloc_slave - Allocate a new SPI slave
  *
  * Allocate and zero all fields in the spi slave, and set the bus/chip
  * select.
  *
  * @_struct:	Name of structure to allocate (e.g. struct tegra_spi).
  *		This structure must contain a member 'struct spi_slave *slave'.
  * @bus:	Bus ID of the slave chip.
  * @cs:		Chip select ID of the slave chip on the specified bus.
  */
 #define spi_alloc_slave(_struct, bus, cs) \
 	spi_do_alloc_slave(offsetof(_struct, slave), \
 			    sizeof(_struct), bus, cs)
 /**
  * spi_alloc_slave_base - Allocate a new SPI slave with no private data
  *
  * Allocate and zero all fields in the spi slave, and set the bus/chip
  * select.
  *
  * @bus:	Bus ID of the slave chip.
  * @cs:		Chip select ID of the slave chip on the specified bus.
  */
 #define spi_alloc_slave_base(bus, cs) \
 	spi_do_alloc_slave(0, sizeof(struct spi_slave), bus, cs)
 /**
  * Set up communications parameters for a SPI slave.
  *
  * This must be called once for each slave. Note that this function
  * usually doesn't touch any actual hardware, it only initializes the
  * contents of spi_slave so that the hardware can be easily
  * initialized later.
  *
  * @bus:	Bus ID of the slave chip.
  * @cs:		Chip select ID of the slave chip on the specified bus.
  * @max_hz:	Maximum SCK rate in Hz.
  * @mode:	Clock polarity, clock phase and other parameters.
  *
  * Returns: A spi_slave reference that can be used in subsequent SPI
  * calls, or NULL if one or more of the parameters are not supported.
  */
 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 		unsigned int max_hz, unsigned int mode);
 /**
  * Free any memory associated with a SPI slave.
  *
  * @slave:	The SPI slave
  */
 void spi_free_slave(struct spi_slave *slave);
 /**
  * Claim the bus and prepare it for communication with a given slave.
  *
  * This must be called before doing any transfers with a SPI slave. It
  * will enable and initialize any SPI hardware as necessary, and make
  * sure that the SCK line is in the correct idle state. It is not
  * allowed to claim the same bus for several slaves without releasing
  * the bus in between.
  *
  * @slave:	The SPI slave
  *
  * Returns: 0 if the bus was claimed successfully, or a negative value
  * if it wasn't.
  */
 int spi_claim_bus(struct spi_slave *slave);
 /**
  * Release the SPI bus
  *
  * This must be called once for every call to spi_claim_bus() after
  * all transfers have finished. It may disable any SPI hardware as
  * appropriate.
  *
  * @slave:	The SPI slave
  */
 void spi_release_bus(struct spi_slave *slave);
 /**
  * Set the word length for SPI transactions
  *
  * Set the word length (number of bits per word) for SPI transactions.
  *
  * @slave:	The SPI slave
  * @wordlen:	The number of bits in a word
  *
  * Returns: 0 on success, -1 on failure.
  */
 int spi_set_wordlen(struct spi_slave *slave, unsigned int wordlen);
 /**
  * SPI transfer
  *
  * This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks
  * "bitlen" bits in the SPI MISO port.  That's just the way SPI works.
  *
  * The source of the outgoing bits is the "dout" parameter and the
  * destination of the input bits is the "din" parameter.  Note that "dout"
  * and "din" can point to the same memory location, in which case the
  * input data overwrites the output data (since both are buffered by
  * temporary variables, this is OK).
  *
  * spi_xfer() interface:
  * @slave:	The SPI slave which will be sending/receiving the data.
  * @bitlen:	How many bits to write and read.
  * @dout:	Pointer to a string of bits to send out.  The bits are
  *		held in a byte array and are sent MSB first.
  * @din:	Pointer to a string of bits that will be filled in.
  * @flags:	A bitwise combination of SPI_XFER_* flags.
  *
  * Returns: 0 on success, not 0 on failure
  */
 int  spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 		void *din, unsigned long flags);
 /**
  * Determine if a SPI chipselect is valid.
  * This function is provided by the board if the low-level SPI driver
  * needs it to determine if a given chipselect is actually valid.
  *
  * Returns: 1 if bus:cs identifies a valid chip on this board, 0
  * otherwise.
  */
 int  spi_cs_is_valid(unsigned int bus, unsigned int cs);
 /**
  * Activate a SPI chipselect.
  * This function is provided by the board code when using a driver
  * that can't control its chipselects automatically (e.g.
  * common/soft_spi.c). When called, it should activate the chip select
  * to the device identified by "slave".
  */
 void spi_cs_activate(struct spi_slave *slave);
 /**
  * Deactivate a SPI chipselect.
  * This function is provided by the board code when using a driver
  * that can't control its chipselects automatically (e.g.
  * common/soft_spi.c). When called, it should deactivate the chip
  * select to the device identified by "slave".
  */
 void spi_cs_deactivate(struct spi_slave *slave);
 /**
  * Set transfer speed.
  * This sets a new speed to be applied for next spi_xfer().
  * @slave:	The SPI slave
  * @hz:		The transfer speed
  */
 void spi_set_speed(struct spi_slave *slave, uint hz);
 /**
  * Write 8 bits, then read 8 bits.
  * @slave:	The SPI slave we're communicating with
  * @byte:	Byte to be written
  *
  * Returns: The value that was read, or a negative value on error.
  *
  * TODO: This function probably shouldn't be inlined.
  */
 static inline int spi_w8r8(struct spi_slave *slave, unsigned char byte)
 {
 	unsigned char dout[2];
 	unsigned char din[2];
 	int ret;
 	dout[0] = byte;
 	dout[1] = 0;
 	ret = spi_xfer(slave, 16, dout, din, SPI_XFER_BEGIN | SPI_XFER_END);
 	return ret < 0 ? ret : din[1];
 }
 /**
  * Set up a SPI slave for a particular device tree node
  *
  * This calls spi_setup_slave() with the correct bus number. Call
  * spi_free_slave() to free it later.
  *
  * @param blob:		Device tree blob
  * @param slave_node:	Slave node to use
  * @param spi_node:	SPI peripheral node to use
  * @return pointer to new spi_slave structure
  */
 struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node,
 				      int spi_node);
 /**
  * spi_base_setup_slave_fdt() - helper function to set up a SPI slace
  *
  * This decodes SPI properties from the slave node to determine the
  * chip select and SPI parameters.
  *
  * @blob:	Device tree blob
  * @busnum:	Bus number to use
  * @node:	Device tree node for the SPI bus
  */
 struct spi_slave *spi_base_setup_slave_fdt(const void *blob, int busnum,
 					   int node);
 #endif	/* _SPI_H_ */

include/spi_flash.h

Diff comments View file @ 3163aaa

 /*
  * Common SPI flash Interface
  *
  * Copyright (C) 2008 Atmel Corporation
  * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
  * version 2 as published by the Free Software Foundation.
  */
 #ifndef _SPI_FLASH_H_
 #define _SPI_FLASH_H_
 #include <spi.h>
 #include <linux/types.h>
 #include <linux/compiler.h>
-/* Enum list - Extended read commands */
+/* No enum list for write commands only QPP */
+#define WR_QPP		1 << 4
+/* Enum list - Full read commands */
 enum spi_read_cmds {
 	ARRAY_SLOW = 1 << 0,
 	DUAL_OUTPUT_FAST = 1 << 1,
 	DUAL_IO_FAST = 1 << 2,
+	QUAD_OUTPUT_FAST = 1 << 3,
 };
 #define RD_EXTN		ARRAY_SLOW | DUAL_OUTPUT_FAST | DUAL_IO_FAST
+#define RD_FULL		RD_EXTN | QUAD_OUTPUT_FAST
 /**
  * struct spi_flash - SPI flash structure
  *
  * @spi:		SPI slave
  * @name:		Name of SPI flash
  * @size:		Total flash size
  * @page_size:		Write (page) size
  * @sector_size:	Sector size
  * @erase_size:		Erase size
  * @bank_read_cmd:	Bank read cmd
  * @bank_write_cmd:	Bank write cmd
  * @bank_curr:		Current flash bank
  * @poll_cmd:		Poll cmd - for flash erase/program
  * @erase_cmd:		Erase cmd 4K, 32K, 64K
- * @read_cmd:		Read cmd - Array Fast and Extn read
+ * @read_cmd:		Read cmd - Array Fast, Extn read and quad read.
+ * @write_cmd:		Write cmd - page and quad program.
  * @memory_map:		Address of read-only SPI flash access
  * @read:		Flash read ops: Read len bytes at offset into buf
  *			Supported cmds: Fast Array Read
  * @write:		Flash write ops: Write len bytes from buf into offeset
  *			Supported cmds: Page Program
  * @erase:		Flash erase ops: Erase len bytes from offset
  *			Supported cmds: Sector erase 4K, 32K, 64K
  * return 0 - Sucess, 1 - Failure
  */
 struct spi_flash {
 	struct spi_slave *spi;
 	const char *name;
 	u32 size;
 	u32 page_size;
 	u32 sector_size;
 	u32 erase_size;
 #ifdef CONFIG_SPI_FLASH_BAR
 	u8 bank_read_cmd;
 	u8 bank_write_cmd;
 	u8 bank_curr;
 #endif
 	u8 poll_cmd;
 	u8 erase_cmd;
 	u8 read_cmd;
+	u8 write_cmd;
 	void *memory_map;
 	int (*read)(struct spi_flash *flash, u32 offset, size_t len, void *buf);
 	int (*write)(struct spi_flash *flash, u32 offset, size_t len,
 			const void *buf);
 	int (*erase)(struct spi_flash *flash, u32 offset, size_t len);
 };
 struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
 		unsigned int max_hz, unsigned int spi_mode);
 /**
  * Set up a new SPI flash from an fdt node
  *
  * @param blob		Device tree blob
  * @param slave_node	Pointer to this SPI slave node in the device tree
  * @param spi_node	Cached pointer to the SPI interface this node belongs
  *			to
  * @return 0 if ok, -1 on error
  */
 struct spi_flash *spi_flash_probe_fdt(const void *blob, int slave_node,
 				      int spi_node);
 void spi_flash_free(struct spi_flash *flash);
 static inline int spi_flash_read(struct spi_flash *flash, u32 offset,
 		size_t len, void *buf)
 {
 	return flash->read(flash, offset, len, buf);
 }
 static inline int spi_flash_write(struct spi_flash *flash, u32 offset,
 		size_t len, const void *buf)
 {
 	return flash->write(flash, offset, len, buf);
 }
 static inline int spi_flash_erase(struct spi_flash *flash, u32 offset,
 		size_t len)
 {
 	return flash->erase(flash, offset, len);
 }
 void spi_boot(void) __noreturn;
 #endif /* _SPI_FLASH_H_ */