Eric Lee / smarc-uboot

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Commit 31ad864e47f03288bf1d4232913b38ddb624345c

Authored by Chin Liang See
Committed by Albert ARIBAUD
1 parent fba1ed422e
Exists in master and in 56 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf-6.6.52-2.2.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

socfpga: Adding configuration for development kit 

Separating the configuration file for Virtual
Target and real hardware Cyclone V development kit

Signed-off-by: Chin Liang See <clsee@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>

Showing 1 changed file with 21 additions and 7 deletions Side-by-side Diff

include/configs/socfpga_cyclone5.h
Diff comments   View file @ 31ad864
... ... @@ -11,6 +11,8 @@
11 11 /*
12 12 * High level configuration
13 13 */
  14 +/* Virtual target or real hardware */
  15 +#define CONFIG_SOCFPGA_VIRTUAL_TARGET
14 16  
15 17 #define CONFIG_ARMV7
16 18 #define CONFIG_L2_OFF
17 19  
... ... @@ -21,11 +23,12 @@
21 23 #define CONFIG_SINGLE_BOOTLOADER
22 24 #define CONFIG_SOCFPGA
23 25  
  26 +/* base address for .text section */
  27 +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
24 28 #define CONFIG_SYS_TEXT_BASE 0x08000040
25   -#define V_NS16550_CLK 1000000
26   -#define CONFIG_BAUDRATE 57600
27   -#define CONFIG_SYS_HZ 1000
28   -#define CONFIG_TIMER_CLOCK_KHZ 2400
  29 +#else
  30 +#define CONFIG_SYS_TEXT_BASE 0x01000040
  31 +#endif
29 32 #define CONFIG_SYS_LOAD_ADDR 0x7fc0
30 33  
31 34 /* Console I/O Buffer Size */
... ... @@ -154,7 +157,7 @@
154 157 /* SDRAM Bank #1 */
155 158 #define CONFIG_SYS_SDRAM_BASE 0x00000000
156 159 /* SDRAM memory size */
157   -#define PHYS_SDRAM_1_SIZE 0x80000000
  160 +#define PHYS_SDRAM_1_SIZE 0x40000000
158 161  
159 162 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
160 163 #define CONFIG_SYS_MEMTEST_START 0x00000000
161 164  
... ... @@ -170,8 +173,13 @@
170 173 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
171 174 #define CONFIG_CONS_INDEX 1
172 175 #define CONFIG_SYS_NS16550_COM1 UART0_BASE
173   -
174 176 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
  177 +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
  178 +#define V_NS16550_CLK 1000000
  179 +#else
  180 +#define V_NS16550_CLK 100000000
  181 +#endif
  182 +#define CONFIG_BAUDRATE 115200
175 183  
176 184 /*
177 185 * FLASH
178 186  
... ... @@ -184,9 +192,15 @@
184 192 /* This timer use eosc1 where the clock frequency is fixed
185 193 * throughout any condition */
186 194 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
187   -
188 195 /* reload value when timer count to zero */
189 196 #define TIMER_LOAD_VAL 0xFFFFFFFF
  197 +/* Timer info */
  198 +#define CONFIG_SYS_HZ 1000
  199 +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
  200 +#define CONFIG_TIMER_CLOCK_KHZ 2400
  201 +#else
  202 +#define CONFIG_TIMER_CLOCK_KHZ 25000
  203 +#endif
190 204  
191 205 #define CONFIG_ENV_IS_NOWHERE
192 206