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Commit 31c1ff90e2070759dd8c35a182f96c342543dad6

Authored by Stephen Warren
Committed by Joe Hershberger
1 parent 2b950f3aea

ARM: tegra: add DWC EQoS (ethernet) to Tegra186 DT 

Tegra186 includes a Synopsys DWC EQoS (Ethernet) device. Add this to the
Tegra186 SoC DT so that boards can make use of it.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Showing 1 changed file with 20 additions and 0 deletions Side-by-side Diff

arch/arm/dts/tegra186.dtsi
Diff comments   View file @ 31c1ff9
... ... @@ -31,6 +31,26 @@
31 31 #interrupt-cells = <2>;
32 32 };
33 33  
  34 + ethernet@2490000 {
  35 + compatible = "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10";
  36 + reg = <0x0 0x02490000 0x0 0x10000>;
  37 + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
  38 + clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
  39 + <&bpmp TEGRA186_CLK_EQOS_AXI>,
  40 + <&bpmp TEGRA186_CLK_EQOS_RX>,
  41 + <&bpmp TEGRA186_CLK_EQOS_PTP_REF>,
  42 + <&bpmp TEGRA186_CLK_EQOS_TX>;
  43 + clock-names = "slave_bus",
  44 + "master_bus",
  45 + "rx",
  46 + "ptp_ref",
  47 + "tx";
  48 + resets = <&bpmp TEGRA186_RESET_EQOS>;
  49 + reset-names = "eqos";
  50 + phy-mode = "rgmii";
  51 + status = "disabled";
  52 + };
  53 +
34 54 uarta: serial@3100000 {
35 55 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
36 56 reg = <0x0 0x03100000 0x0 0x10000>;