Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 320cf350801f30875fe5749eee74aed242573031

Authored by Yoshihiro Shimoda
Committed by Nobuhiro Iwamatsu
1 parent fd44194945
Exists in master and in 50 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

sh: add support for sh7753evb board 

The SH7753 EVB board has SH7753, 512MB DDR3-SDRAM, SPI ROM,
Gigabit Ethernet, and eMMC.

This patch support the following functions:
 - 512MB DDR3-SDRAM, SCIF4, SPI ROM, Gigabit Ethernet, eMMC

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Showing 10 changed files with 1368 additions and 0 deletions Side-by-side Diff

arch/sh/include/asm/cpu_sh4.h
Diff comments   View file @ 320cf35
... ... @@ -37,6 +37,8 @@
37 37 # include <asm/cpu_sh7734.h>
38 38 #elif defined (CONFIG_CPU_SH7752)
39 39 # include <asm/cpu_sh7752.h>
  40 +#elif defined (CONFIG_CPU_SH7753)
  41 +# include <asm/cpu_sh7753.h>
40 42 #elif defined (CONFIG_CPU_SH7757)
41 43 # include <asm/cpu_sh7757.h>
42 44 #elif defined (CONFIG_CPU_SH7763)
arch/sh/include/asm/cpu_sh7753.h
Diff comments   View file @ 320cf35
  1 +/*
  2 + * Copyright (C) 2012 Renesas Solutions Corp.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef _ASM_CPU_SH7753_H_
  8 +#define _ASM_CPU_SH7753_H_
  9 +
  10 +#define CCR 0xFF00001C
  11 +#define WTCNT 0xFFCC0000
  12 +#define CCR_CACHE_INIT 0x0000090b
  13 +#define CACHE_OC_NUM_WAYS 1
  14 +
  15 +#ifndef __ASSEMBLY__ /* put C only stuff in this section */
  16 +/* MMU */
  17 +struct mmu_regs {
  18 + unsigned int reserved[4];
  19 + unsigned int mmucr;
  20 +};
  21 +#define MMU_BASE ((struct mmu_regs *)0xff000000)
  22 +
  23 +/* Watchdog */
  24 +#define WTCSR0 0xffcc0002
  25 +#define WRSTCSR_R 0xffcc0003
  26 +#define WRSTCSR_W 0xffcc0002
  27 +#define WTCSR_PREFIX 0xa500
  28 +#define WRSTCSR_PREFIX 0x6900
  29 +#define WRSTCSR_WOVF_PREFIX 0x9600
  30 +
  31 +/* SCIF */
  32 +#define SCIF0_BASE 0xfe4b0000 /* The real name is SCIF2 */
  33 +#define SCIF1_BASE 0xfe4c0000 /* The real name is SCIF3 */
  34 +#define SCIF2_BASE 0xfe4d0000 /* The real name is SCIF4 */
  35 +
  36 +/* TMU0 */
  37 +#define TMU_BASE 0xFE430000
  38 +
  39 +/* ETHER, GETHER MAC address */
  40 +struct ether_mac_regs {
  41 + unsigned int reserved[114];
  42 + unsigned int mahr;
  43 + unsigned int reserved2;
  44 + unsigned int malr;
  45 +};
  46 +#define GETHER0_MAC_BASE ((struct ether_mac_regs *)0xfee0400)
  47 +#define GETHER1_MAC_BASE ((struct ether_mac_regs *)0xfee0c00)
  48 +#define ETHER0_MAC_BASE ((struct ether_mac_regs *)0xfef0000)
  49 +#define ETHER1_MAC_BASE ((struct ether_mac_regs *)0xfef0800)
  50 +
  51 +/* GETHER */
  52 +struct gether_control_regs {
  53 + unsigned int gbecont;
  54 +};
  55 +#define GETHER_CONTROL_BASE ((struct gether_control_regs *)0xffc10100)
  56 +#define GBECONT_RMII1 0x00020000
  57 +#define GBECONT_RMII0 0x00010000
  58 +
  59 +/* SerMux */
  60 +struct sermux_regs {
  61 + unsigned char smr0;
  62 + unsigned char smr1;
  63 + unsigned char smr2;
  64 + unsigned char smr3;
  65 + unsigned char smr4;
  66 + unsigned char smr5;
  67 +};
  68 +#define SERMUX_BASE ((struct sermux_regs *)0xfe470000)
  69 +
  70 +
  71 +/* USB0/1 */
  72 +struct usb_common_regs {
  73 + unsigned short reserved[129];
  74 + unsigned short suspmode;
  75 +};
  76 +#define USB0_COMMON_BASE ((struct usb_common_regs *)0xfe450000)
  77 +#define USB1_COMMON_BASE ((struct usb_common_regs *)0xfe4f0000)
  78 +
  79 +struct usb0_phy_regs {
  80 + unsigned short reset;
  81 + unsigned short reserved[4];
  82 + unsigned short portsel;
  83 +};
  84 +#define USB0_PHY_BASE ((struct usb0_phy_regs *)0xfe5f0000)
  85 +
  86 +struct usb1_port_regs {
  87 + unsigned int port1sel;
  88 + unsigned int reserved;
  89 + unsigned int usb1intsts;
  90 +};
  91 +#define USB1_PORT_BASE ((struct usb1_port_regs *)0xfe4f2000)
  92 +
  93 +struct usb1_alignment_regs {
  94 + unsigned int ehcidatac; /* 0xfe4fe018 */
  95 + unsigned int reserved[63];
  96 + unsigned int ohcidatac;
  97 +};
  98 +#define USB1_ALIGNMENT_BASE ((struct usb1_alignment_regs *)0xfe4fe018)
  99 +
  100 +/* GPIO */
  101 +struct gpio_regs {
  102 + unsigned short pacr;
  103 + unsigned short pbcr;
  104 + unsigned short pccr;
  105 + unsigned short pdcr;
  106 + unsigned short pecr;
  107 + unsigned short pfcr;
  108 + unsigned short pgcr;
  109 + unsigned short phcr;
  110 + unsigned short picr;
  111 + unsigned short pjcr;
  112 + unsigned short pkcr;
  113 + unsigned short plcr;
  114 + unsigned short pmcr;
  115 + unsigned short pncr;
  116 + unsigned short pocr;
  117 + unsigned short reserved;
  118 + unsigned short pqcr;
  119 + unsigned short prcr;
  120 + unsigned short pscr;
  121 + unsigned short ptcr;
  122 + unsigned short pucr;
  123 + unsigned short pvcr;
  124 + unsigned short pwcr;
  125 + unsigned short pxcr;
  126 + unsigned short pycr;
  127 + unsigned short pzcr;
  128 + unsigned char padr;
  129 + unsigned char reserved_a;
  130 + unsigned char pbdr;
  131 + unsigned char reserved_b;
  132 + unsigned char pcdr;
  133 + unsigned char reserved_c;
  134 + unsigned char pddr;
  135 + unsigned char reserved_d;
  136 + unsigned char pedr;
  137 + unsigned char reserved_e;
  138 + unsigned char pfdr;
  139 + unsigned char reserved_f;
  140 + unsigned char pgdr;
  141 + unsigned char reserved_g;
  142 + unsigned char phdr;
  143 + unsigned char reserved_h;
  144 + unsigned char pidr;
  145 + unsigned char reserved_i;
  146 + unsigned char pjdr;
  147 + unsigned char reserved_j;
  148 + unsigned char pkdr;
  149 + unsigned char reserved_k;
  150 + unsigned char pldr;
  151 + unsigned char reserved_l;
  152 + unsigned char pmdr;
  153 + unsigned char reserved_m;
  154 + unsigned char pndr;
  155 + unsigned char reserved_n;
  156 + unsigned char podr;
  157 + unsigned char reserved_o;
  158 + unsigned char ppdr;
  159 + unsigned char reserved_p;
  160 + unsigned char pqdr;
  161 + unsigned char reserved_q;
  162 + unsigned char prdr;
  163 + unsigned char reserved_r;
  164 + unsigned char psdr;
  165 + unsigned char reserved_s;
  166 + unsigned char ptdr;
  167 + unsigned char reserved_t;
  168 + unsigned char pudr;
  169 + unsigned char reserved_u;
  170 + unsigned char pvdr;
  171 + unsigned char reserved_v;
  172 + unsigned char pwdr;
  173 + unsigned char reserved_w;
  174 + unsigned char pxdr;
  175 + unsigned char reserved_x;
  176 + unsigned char pydr;
  177 + unsigned char reserved_y;
  178 + unsigned char pzdr;
  179 + unsigned char reserved_z;
  180 + unsigned short ncer;
  181 + unsigned short ncmcr;
  182 + unsigned short nccsr;
  183 + unsigned char reserved2[2];
  184 + unsigned short psel0; /* +0x70 */
  185 + unsigned short psel1;
  186 + unsigned short psel2;
  187 + unsigned short psel3;
  188 + unsigned short psel4;
  189 + unsigned short psel5;
  190 + unsigned short psel6;
  191 + unsigned short reserved3[2];
  192 + unsigned short psel7;
  193 +};
  194 +#define GPIO_BASE ((struct gpio_regs *)0xffec0000)
  195 +
  196 +#endif /* ifndef __ASSEMBLY__ */
  197 +#endif /* _ASM_CPU_SH7753_H_ */
board/renesas/sh7753evb/Makefile
Diff comments   View file @ 320cf35
  1 +#
  2 +# Copyright (C) 2012 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
  3 +#
  4 +# SPDX-License-Identifier: GPL-2.0+
  5 +
  6 +obj-y := sh7753evb.o spi-boot.o
  7 +obj-y += lowlevel_init.o
board/renesas/sh7753evb/lowlevel_init.S
Diff comments   View file @ 320cf35
  1 +/*
  2 + * Copyright (C) 2013 Renesas Solutions Corp.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <config.h>
  8 +#include <version.h>
  9 +#include <asm/processor.h>
  10 +#include <asm/macro.h>
  11 +
  12 +.macro or32, addr, data
  13 + mov.l \addr, r1
  14 + mov.l \data, r0
  15 + mov.l @r1, r2
  16 + or r2, r0
  17 + mov.l r0, @r1
  18 +.endm
  19 +
  20 +.macro wait_DBCMD
  21 + mov.l DBWAIT_A, r0
  22 + mov.l @r0, r1
  23 +.endm
  24 +
  25 + .global lowlevel_init
  26 + .section .spiboot1.text
  27 + .align 2
  28 +
  29 +lowlevel_init:
  30 + mov #0, r14
  31 + mova 2f, r0
  32 + mov.l PC_MASK, r1
  33 + tst r0, r1
  34 + bf 2f
  35 +
  36 + bra exit_pmb
  37 + nop
  38 +
  39 + .align 2
  40 +
  41 +/* If CPU runs on SDRAM (PC=0x5???????) or not. */
  42 +PC_MASK: .long 0x20000000
  43 +
  44 +2:
  45 + mov #1, r14
  46 +
  47 + mov.l EXPEVT_A, r0
  48 + mov.l @r0, r0
  49 + mov.l EXPEVT_POWER_ON_RESET, r1
  50 + cmp/eq r0, r1
  51 + bt 1f
  52 +
  53 + /*
  54 + * If EXPEVT value is manual reset or tlb multipul-hit,
  55 + * initialization of DBSC3 is not necessary.
  56 + */
  57 + bra exit_ddr
  58 + nop
  59 +
  60 +1:
  61 + /*------- Reset -------*/
  62 + write32 MRSTCR0_A, MRSTCR0_D
  63 + write32 MRSTCR1_A, MRSTCR1_D
  64 +
  65 + /* For Core Reset */
  66 + mov.l DBACEN_A, r0
  67 + mov.l @r0, r0
  68 + cmp/eq #0, r0
  69 + bt 3f
  70 +
  71 + /*
  72 + * If DBACEN == 1(DBSC was already enabled), we have to avoid the
  73 + * initialization of DDR3-SDRAM.
  74 + */
  75 + bra exit_ddr
  76 + nop
  77 +
  78 +3:
  79 + /*------- DBSC3 -------*/
  80 + /* oscillation stabilization time */
  81 + wait_timer WAIT_OSC_TIME
  82 +
  83 + /* step 3 */
  84 + write32 DBKIND_A, DBKIND_D
  85 +
  86 + /* step 4 */
  87 + write32 DBCONF_A, DBCONF_D
  88 + write32 DBTR0_A, DBTR0_D
  89 + write32 DBTR1_A, DBTR1_D
  90 + write32 DBTR2_A, DBTR2_D
  91 + write32 DBTR3_A, DBTR3_D
  92 + write32 DBTR4_A, DBTR4_D
  93 + write32 DBTR5_A, DBTR5_D
  94 + write32 DBTR6_A, DBTR6_D
  95 + write32 DBTR7_A, DBTR7_D
  96 + write32 DBTR8_A, DBTR8_D
  97 + write32 DBTR9_A, DBTR9_D
  98 + write32 DBTR10_A, DBTR10_D
  99 + write32 DBTR11_A, DBTR11_D
  100 + write32 DBTR12_A, DBTR12_D
  101 + write32 DBTR13_A, DBTR13_D
  102 + write32 DBTR14_A, DBTR14_D
  103 + write32 DBTR15_A, DBTR15_D
  104 + write32 DBTR16_A, DBTR16_D
  105 + write32 DBTR17_A, DBTR17_D
  106 + write32 DBTR18_A, DBTR18_D
  107 + write32 DBTR19_A, DBTR19_D
  108 + write32 DBRNK0_A, DBRNK0_D
  109 + write32 DBADJ0_A, DBADJ0_D
  110 + write32 DBADJ2_A, DBADJ2_D
  111 +
  112 + /* step 5 */
  113 + write32 DBCMD_A, DBCMD_RSTL_VAL
  114 + wait_timer WAIT_30US
  115 +
  116 + /* step 6 */
  117 + write32 DBCMD_A, DBCMD_PDEN_VAL
  118 +
  119 + /* step 7 */
  120 + write32 DBPDCNT3_A, DBPDCNT3_D
  121 +
  122 + /* step 8 */
  123 + write32 DBPDCNT1_A, DBPDCNT1_D
  124 + write32 DBPDCNT2_A, DBPDCNT2_D
  125 + write32 DBPDLCK_A, DBPDLCK_D
  126 + write32 DBPDRGA_A, DBPDRGA_D
  127 + write32 DBPDRGD_A, DBPDRGD_D
  128 +
  129 + /* step 9 */
  130 + wait_timer WAIT_30US
  131 +
  132 + /* step 10 */
  133 + write32 DBPDCNT0_A, DBPDCNT0_D
  134 +
  135 + /* step 11 */
  136 + wait_timer WAIT_30US
  137 + wait_timer WAIT_30US
  138 +
  139 + /* step 12 */
  140 + write32 DBCMD_A, DBCMD_WAIT_VAL
  141 + wait_DBCMD
  142 +
  143 + /* step 13 */
  144 + write32 DBCMD_A, DBCMD_RSTH_VAL
  145 + wait_DBCMD
  146 +
  147 + /* step 14 */
  148 + write32 DBCMD_A, DBCMD_WAIT_VAL
  149 + write32 DBCMD_A, DBCMD_WAIT_VAL
  150 + write32 DBCMD_A, DBCMD_WAIT_VAL
  151 + write32 DBCMD_A, DBCMD_WAIT_VAL
  152 +
  153 + /* step 15 */
  154 + write32 DBCMD_A, DBCMD_PDXT_VAL
  155 +
  156 + /* step 16 */
  157 + write32 DBCMD_A, DBCMD_MRS2_VAL
  158 +
  159 + /* step 17 */
  160 + write32 DBCMD_A, DBCMD_MRS3_VAL
  161 +
  162 + /* step 18 */
  163 + write32 DBCMD_A, DBCMD_MRS1_VAL
  164 +
  165 + /* step 19 */
  166 + write32 DBCMD_A, DBCMD_MRS0_VAL
  167 + write32 DBPDNCNF_A, DBPDNCNF_D
  168 +
  169 + /* step 20 */
  170 + write32 DBCMD_A, DBCMD_ZQCL_VAL
  171 +
  172 + write32 DBCMD_A, DBCMD_REF_VAL
  173 + write32 DBCMD_A, DBCMD_REF_VAL
  174 + wait_DBCMD
  175 +
  176 + /* step 21 */
  177 + write32 DBCALTR_A, DBCALTR_D
  178 +
  179 + /* step 22 */
  180 + write32 DBRFCNF0_A, DBRFCNF0_D
  181 + write32 DBRFCNF1_A, DBRFCNF1_D
  182 + write32 DBRFCNF2_A, DBRFCNF2_D
  183 +
  184 + /* step 23 */
  185 + write32 DBCALCNF_A, DBCALCNF_D
  186 +
  187 + /* step 24 */
  188 + write32 DBRFEN_A, DBRFEN_D
  189 + write32 DBCMD_A, DBCMD_SRXT_VAL
  190 +
  191 + /* step 25 */
  192 + write32 DBACEN_A, DBACEN_D
  193 +
  194 + /* step 26 */
  195 + wait_DBCMD
  196 +
  197 + bra exit_ddr
  198 + nop
  199 +
  200 + .align 2
  201 +
  202 +EXPEVT_A: .long 0xff000024
  203 +EXPEVT_POWER_ON_RESET: .long 0x00000000
  204 +
  205 +/*------- Reset -------*/
  206 +MRSTCR0_A: .long 0xffd50030
  207 +MRSTCR0_D: .long 0xfe1ffe7f
  208 +MRSTCR1_A: .long 0xffd50034
  209 +MRSTCR1_D: .long 0xfff3ffff
  210 +
  211 +/*------- DBSC3 -------*/
  212 +DBCMD_A: .long 0xfe800018
  213 +DBKIND_A: .long 0xfe800020
  214 +DBCONF_A: .long 0xfe800024
  215 +DBTR0_A: .long 0xfe800040
  216 +DBTR1_A: .long 0xfe800044
  217 +DBTR2_A: .long 0xfe800048
  218 +DBTR3_A: .long 0xfe800050
  219 +DBTR4_A: .long 0xfe800054
  220 +DBTR5_A: .long 0xfe800058
  221 +DBTR6_A: .long 0xfe80005c
  222 +DBTR7_A: .long 0xfe800060
  223 +DBTR8_A: .long 0xfe800064
  224 +DBTR9_A: .long 0xfe800068
  225 +DBTR10_A: .long 0xfe80006c
  226 +DBTR11_A: .long 0xfe800070
  227 +DBTR12_A: .long 0xfe800074
  228 +DBTR13_A: .long 0xfe800078
  229 +DBTR14_A: .long 0xfe80007c
  230 +DBTR15_A: .long 0xfe800080
  231 +DBTR16_A: .long 0xfe800084
  232 +DBTR17_A: .long 0xfe800088
  233 +DBTR18_A: .long 0xfe80008c
  234 +DBTR19_A: .long 0xfe800090
  235 +DBRNK0_A: .long 0xfe800100
  236 +DBPDCNT0_A: .long 0xfe800200
  237 +DBPDCNT1_A: .long 0xfe800204
  238 +DBPDCNT2_A: .long 0xfe800208
  239 +DBPDCNT3_A: .long 0xfe80020c
  240 +DBPDLCK_A: .long 0xfe800280
  241 +DBPDRGA_A: .long 0xfe800290
  242 +DBPDRGD_A: .long 0xfe8002a0
  243 +DBADJ0_A: .long 0xfe8000c0
  244 +DBADJ2_A: .long 0xfe8000c8
  245 +DBRFCNF0_A: .long 0xfe8000e0
  246 +DBRFCNF1_A: .long 0xfe8000e4
  247 +DBRFCNF2_A: .long 0xfe8000e8
  248 +DBCALCNF_A: .long 0xfe8000f4
  249 +DBRFEN_A: .long 0xfe800014
  250 +DBACEN_A: .long 0xfe800010
  251 +DBWAIT_A: .long 0xfe80001c
  252 +DBCALTR_A: .long 0xfe8000f8
  253 +DBPDNCNF_A: .long 0xfe800180
  254 +
  255 +WAIT_OSC_TIME: .long 6000
  256 +WAIT_30US: .long 13333
  257 +
  258 +DBCMD_RSTL_VAL: .long 0x20000000
  259 +DBCMD_PDEN_VAL: .long 0x1000d73c
  260 +DBCMD_WAIT_VAL: .long 0x0000d73c
  261 +DBCMD_RSTH_VAL: .long 0x2100d73c
  262 +DBCMD_PDXT_VAL: .long 0x110000c8
  263 +DBCMD_MRS0_VAL: .long 0x28000930
  264 +DBCMD_MRS1_VAL: .long 0x29000004
  265 +DBCMD_MRS2_VAL: .long 0x2a000008
  266 +DBCMD_MRS3_VAL: .long 0x2b000000
  267 +DBCMD_ZQCL_VAL: .long 0x03000200
  268 +DBCMD_REF_VAL: .long 0x0c000000
  269 +DBCMD_SRXT_VAL: .long 0x19000000
  270 +DBKIND_D: .long 0x00000007
  271 +DBCONF_D: .long 0x0f030a01
  272 +DBTR0_D: .long 0x00000007
  273 +DBTR1_D: .long 0x00000006
  274 +DBTR2_D: .long 0x00000000
  275 +DBTR3_D: .long 0x00000007
  276 +DBTR4_D: .long 0x00070007
  277 +DBTR5_D: .long 0x0000001b
  278 +DBTR6_D: .long 0x00000014
  279 +DBTR7_D: .long 0x00000004
  280 +DBTR8_D: .long 0x00000014
  281 +DBTR9_D: .long 0x00000004
  282 +DBTR10_D: .long 0x00000008
  283 +DBTR11_D: .long 0x00000007
  284 +DBTR12_D: .long 0x0000000e
  285 +DBTR13_D: .long 0x000000a0
  286 +DBTR14_D: .long 0x00060006
  287 +DBTR15_D: .long 0x00000003
  288 +DBTR16_D: .long 0x00160002
  289 +DBTR17_D: .long 0x000c0000
  290 +DBTR18_D: .long 0x00000200
  291 +DBTR19_D: .long 0x00000040
  292 +DBRNK0_D: .long 0x00000001
  293 +DBPDCNT0_D: .long 0x00000001
  294 +DBPDCNT1_D: .long 0x00000001
  295 +DBPDCNT2_D: .long 0x00000000
  296 +DBPDCNT3_D: .long 0x00004010
  297 +DBPDLCK_D: .long 0x0000a55a
  298 +DBPDRGA_D: .long 0x00000028
  299 +DBPDRGD_D: .long 0x00017100
  300 +
  301 +DBADJ0_D: .long 0x00010000
  302 +DBADJ2_D: .long 0x18061806
  303 +DBRFCNF0_D: .long 0x000001ff
  304 +DBRFCNF1_D: .long 0x00081040
  305 +DBRFCNF2_D: .long 0x00000000
  306 +DBCALCNF_D: .long 0x0000ffff
  307 +DBRFEN_D: .long 0x00000001
  308 +DBACEN_D: .long 0x00000001
  309 +DBCALTR_D: .long 0x08200820
  310 +DBPDNCNF_D: .long 0x00000001
  311 +
  312 + .align 2
  313 +exit_ddr:
  314 +#if defined(CONFIG_SH_32BIT)
  315 + /*------- set PMB -------*/
  316 + write32 PASCR_A, PASCR_29BIT_D
  317 + write32 MMUCR_A, MMUCR_D
  318 +
  319 + /*****************************************************************
  320 + * ent virt phys v sz c wt
  321 + * 0 0xa0000000 0x00000000 1 128M 0 1
  322 + * 1 0xa8000000 0x48000000 1 128M 0 1
  323 + * 5 0x88000000 0x48000000 1 128M 1 1
  324 + */
  325 + write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D
  326 + write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D
  327 + write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
  328 + write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
  329 + write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
  330 + write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
  331 +
  332 + write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D
  333 + write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D
  334 + write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D
  335 + write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D
  336 + write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D
  337 + write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D
  338 + write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D
  339 + write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D
  340 + write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D
  341 + write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D
  342 + write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D
  343 + write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D
  344 + write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D
  345 +
  346 + write32 PASCR_A, PASCR_INIT
  347 + mov.l DUMMY_ADDR, r0
  348 + icbi @r0
  349 +#endif /* if defined(CONFIG_SH_32BIT) */
  350 +
  351 +exit_pmb:
  352 + /* CPU is running on ILRAM? */
  353 + mov r14, r0
  354 + tst #1, r0
  355 + bt 1f
  356 +
  357 + mov.l _stack_ilram, r15
  358 + mov.l _spiboot_main, r0
  359 +100: bsrf r0
  360 + nop
  361 +
  362 + .align 2
  363 +_spiboot_main: .long (spiboot_main - (100b + 4))
  364 +_stack_ilram: .long 0xe5204000
  365 +
  366 +1:
  367 + write32 CCR_A, CCR_D
  368 +
  369 + rts
  370 + nop
  371 +
  372 + .align 2
  373 +
  374 +#if defined(CONFIG_SH_32BIT)
  375 +/*------- set PMB -------*/
  376 +PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0)
  377 +PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1)
  378 +PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5)
  379 +PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2)
  380 +PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3)
  381 +PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4)
  382 +PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6)
  383 +PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7)
  384 +PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8)
  385 +PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9)
  386 +PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10)
  387 +PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11)
  388 +PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12)
  389 +PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13)
  390 +PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14)
  391 +PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15)
  392 +
  393 +PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0)
  394 +PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
  395 +PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
  396 +PMB_ADDR_NOT_USE_D: .long 0x00000000
  397 +
  398 +PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0)
  399 +PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1)
  400 +PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5)
  401 +
  402 +/* ppn ub v s1 s0 c wt */
  403 +PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
  404 +PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
  405 +PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
  406 +
  407 +PASCR_A: .long 0xff000070
  408 +DUMMY_ADDR: .long 0xa0000000
  409 +PASCR_29BIT_D: .long 0x00000000
  410 +PASCR_INIT: .long 0x80000080
  411 +MMUCR_A: .long 0xff000010
  412 +MMUCR_D: .long 0x00000004 /* clear ITLB */
  413 +#endif /* CONFIG_SH_32BIT */
  414 +
  415 +CCR_A: .long CCR
  416 +CCR_D: .long CCR_CACHE_INIT
board/renesas/sh7753evb/sh7753evb.c
Diff comments   View file @ 320cf35
  1 +/*
  2 + * Copyright (C) 2012 Renesas Solutions Corp.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <malloc.h>
  9 +#include <asm/processor.h>
  10 +#include <asm/io.h>
  11 +#include <asm/mmc.h>
  12 +#include <spi_flash.h>
  13 +
  14 +int checkboard(void)
  15 +{
  16 + puts("BOARD: SH7753 EVB\n");
  17 +
  18 + return 0;
  19 +}
  20 +
  21 +static void init_gpio(void)
  22 +{
  23 + struct gpio_regs *gpio = GPIO_BASE;
  24 + struct sermux_regs *sermux = SERMUX_BASE;
  25 +
  26 + /* GPIO */
  27 + writew(0x0000, &gpio->pacr); /* GETHER */
  28 + writew(0x0001, &gpio->pbcr); /* INTC */
  29 + writew(0x0000, &gpio->pccr); /* PWMU, INTC */
  30 + writew(0x0000, &gpio->pdcr); /* SPI0 */
  31 + writew(0xeaff, &gpio->pecr); /* GPIO */
  32 + writew(0x0000, &gpio->pfcr); /* WDT */
  33 + writew(0x0004, &gpio->pgcr); /* SPI0, GETHER MDIO gate(PTG1) */
  34 + writew(0x0000, &gpio->phcr); /* SPI1 */
  35 + writew(0x0000, &gpio->picr); /* SDHI */
  36 + writew(0x0000, &gpio->pjcr); /* SCIF4 */
  37 + writew(0x0003, &gpio->pkcr); /* SerMux */
  38 + writew(0x0000, &gpio->plcr); /* SerMux */
  39 + writew(0x0000, &gpio->pmcr); /* RIIC */
  40 + writew(0x0000, &gpio->pncr); /* USB, SGPIO */
  41 + writew(0x0000, &gpio->pocr); /* SGPIO */
  42 + writew(0xd555, &gpio->pqcr); /* GPIO */
  43 + writew(0x0000, &gpio->prcr); /* RIIC */
  44 + writew(0x0000, &gpio->pscr); /* RIIC */
  45 + writew(0x0000, &gpio->ptcr); /* STATUS */
  46 + writeb(0x00, &gpio->pudr);
  47 + writew(0x5555, &gpio->pucr); /* Debug LED */
  48 + writew(0x0000, &gpio->pvcr); /* RSPI */
  49 + writew(0x0000, &gpio->pwcr); /* EVC */
  50 + writew(0x0000, &gpio->pxcr); /* LBSC */
  51 + writew(0x0000, &gpio->pycr); /* LBSC */
  52 + writew(0x0000, &gpio->pzcr); /* eMMC */
  53 + writew(0xfe00, &gpio->psel0);
  54 + writew(0x0000, &gpio->psel1);
  55 + writew(0x3000, &gpio->psel2);
  56 + writew(0xff00, &gpio->psel3);
  57 + writew(0x771f, &gpio->psel4);
  58 + writew(0x0ffc, &gpio->psel5);
  59 + writew(0x00ff, &gpio->psel6);
  60 + writew(0xfc00, &gpio->psel7);
  61 +
  62 + writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */
  63 +}
  64 +
  65 +static void init_usb_phy(void)
  66 +{
  67 + struct usb_common_regs *common0 = USB0_COMMON_BASE;
  68 + struct usb_common_regs *common1 = USB1_COMMON_BASE;
  69 + struct usb0_phy_regs *phy = USB0_PHY_BASE;
  70 + struct usb1_port_regs *port = USB1_PORT_BASE;
  71 + struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
  72 +
  73 + writew(0x0100, &phy->reset); /* set reset */
  74 + /* port0 = USB0, port1 = USB1 */
  75 + writew(0x0002, &phy->portsel);
  76 + writel(0x0001, &port->port1sel); /* port1 = Host */
  77 + writew(0x0111, &phy->reset); /* clear reset */
  78 +
  79 + writew(0x4000, &common0->suspmode);
  80 + writew(0x4000, &common1->suspmode);
  81 +
  82 +#if defined(__LITTLE_ENDIAN)
  83 + writel(0x00000000, &align->ehcidatac);
  84 + writel(0x00000000, &align->ohcidatac);
  85 +#endif
  86 +}
  87 +
  88 +static void init_gether_mdio(void)
  89 +{
  90 + struct gpio_regs *gpio = GPIO_BASE;
  91 +
  92 + writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr);
  93 + writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */
  94 +}
  95 +
  96 +static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
  97 +{
  98 + struct ether_mac_regs *ether;
  99 + unsigned char mac[6];
  100 + unsigned long val;
  101 +
  102 + eth_parse_enetaddr(mac_string, mac);
  103 +
  104 + if (!channel)
  105 + ether = GETHER0_MAC_BASE;
  106 + else
  107 + ether = GETHER1_MAC_BASE;
  108 +
  109 + val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
  110 + writel(val, &ether->mahr);
  111 + val = (mac[4] << 8) | mac[5];
  112 + writel(val, &ether->malr);
  113 +}
  114 +
  115 +/*****************************************************************
  116 + * This PMB must be set on this timing. The lowlevel_init is run on
  117 + * Area 0(phys 0x00000000), so we have to map it.
  118 + *
  119 + * The new PMB table is following:
  120 + * ent virt phys v sz c wt
  121 + * 0 0xa0000000 0x40000000 1 128M 0 1
  122 + * 1 0xa8000000 0x48000000 1 128M 0 1
  123 + * 2 0xb0000000 0x50000000 1 128M 0 1
  124 + * 3 0xb8000000 0x58000000 1 128M 0 1
  125 + * 4 0x80000000 0x40000000 1 128M 1 1
  126 + * 5 0x88000000 0x48000000 1 128M 1 1
  127 + * 6 0x90000000 0x50000000 1 128M 1 1
  128 + * 7 0x98000000 0x58000000 1 128M 1 1
  129 + */
  130 +static void set_pmb_on_board_init(void)
  131 +{
  132 + struct mmu_regs *mmu = MMU_BASE;
  133 +
  134 + /* clear ITLB */
  135 + writel(0x00000004, &mmu->mmucr);
  136 +
  137 + /* delete PMB for SPIBOOT */
  138 + writel(0, PMB_ADDR_BASE(0));
  139 + writel(0, PMB_DATA_BASE(0));
  140 +
  141 + /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
  142 + /* ppn ub v s1 s0 c wt */
  143 + writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
  144 + writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
  145 + writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
  146 + writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
  147 + writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
  148 + writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
  149 + writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
  150 + writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
  151 + writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
  152 + writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
  153 + writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
  154 + writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
  155 +}
  156 +
  157 +int board_init(void)
  158 +{
  159 + struct gether_control_regs *gether = GETHER_CONTROL_BASE;
  160 +
  161 + init_gpio();
  162 + set_pmb_on_board_init();
  163 +
  164 + /* Sets TXnDLY to B'010 */
  165 + writel(0x00000202, &gether->gbecont);
  166 +
  167 + init_usb_phy();
  168 + init_gether_mdio();
  169 +
  170 + return 0;
  171 +}
  172 +
  173 +int dram_init(void)
  174 +{
  175 + DECLARE_GLOBAL_DATA_PTR;
  176 +
  177 + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
  178 + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
  179 + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
  180 +
  181 + return 0;
  182 +}
  183 +
  184 +int board_mmc_init(bd_t *bis)
  185 +{
  186 + struct gpio_regs *gpio = GPIO_BASE;
  187 +
  188 + writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr);
  189 + writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */
  190 + udelay(1);
  191 + writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */
  192 + udelay(200);
  193 +
  194 + return mmcif_mmc_init();
  195 +}
  196 +
  197 +static int get_sh_eth_mac_raw(unsigned char *buf, int size)
  198 +{
  199 + struct spi_flash *spi;
  200 + int ret;
  201 +
  202 + spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
  203 + if (spi == NULL) {
  204 + printf("%s: spi_flash probe failed.\n", __func__);
  205 + return 1;
  206 + }
  207 +
  208 + ret = spi_flash_read(spi, SH7753EVB_ETHERNET_MAC_BASE, size, buf);
  209 + if (ret) {
  210 + printf("%s: spi_flash read failed.\n", __func__);
  211 + spi_flash_free(spi);
  212 + return 1;
  213 + }
  214 + spi_flash_free(spi);
  215 +
  216 + return 0;
  217 +}
  218 +
  219 +static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
  220 +{
  221 + memcpy(mac_string, &buf[channel * (SH7753EVB_ETHERNET_MAC_SIZE + 1)],
  222 + SH7753EVB_ETHERNET_MAC_SIZE);
  223 + mac_string[SH7753EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
  224 +
  225 + return 0;
  226 +}
  227 +
  228 +static void init_ethernet_mac(void)
  229 +{
  230 + char mac_string[64];
  231 + char env_string[64];
  232 + int i;
  233 + unsigned char *buf;
  234 +
  235 + buf = malloc(256);
  236 + if (!buf) {
  237 + printf("%s: malloc failed.\n", __func__);
  238 + return;
  239 + }
  240 + get_sh_eth_mac_raw(buf, 256);
  241 +
  242 + /* Gigabit Ethernet */
  243 + for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) {
  244 + get_sh_eth_mac(i, mac_string, buf);
  245 + if (i == 0)
  246 + setenv("ethaddr", mac_string);
  247 + else {
  248 + sprintf(env_string, "eth%daddr", i);
  249 + setenv(env_string, mac_string);
  250 + }
  251 + set_mac_to_sh_giga_eth_register(i, mac_string);
  252 + }
  253 +
  254 + free(buf);
  255 +}
  256 +
  257 +int board_late_init(void)
  258 +{
  259 + init_ethernet_mac();
  260 +
  261 + return 0;
  262 +}
  263 +
  264 +int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  265 +{
  266 + int i, ret;
  267 + char mac_string[256];
  268 + struct spi_flash *spi;
  269 + unsigned char *buf;
  270 +
  271 + if (argc != 3) {
  272 + buf = malloc(256);
  273 + if (!buf) {
  274 + printf("%s: malloc failed.\n", __func__);
  275 + return 1;
  276 + }
  277 +
  278 + get_sh_eth_mac_raw(buf, 256);
  279 +
  280 + /* print current MAC address */
  281 + for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) {
  282 + get_sh_eth_mac(i, mac_string, buf);
  283 + printf("GETHERC ch%d = %s\n", i, mac_string);
  284 + }
  285 + free(buf);
  286 + return 0;
  287 + }
  288 +
  289 + /* new setting */
  290 + memset(mac_string, 0xff, sizeof(mac_string));
  291 + sprintf(mac_string, "%s\t%s",
  292 + argv[1], argv[2]);
  293 +
  294 + /* write MAC data to SPI rom */
  295 + spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
  296 + if (!spi) {
  297 + printf("%s: spi_flash probe failed.\n", __func__);
  298 + return 1;
  299 + }
  300 +
  301 + ret = spi_flash_erase(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI,
  302 + SH7753EVB_SPI_SECTOR_SIZE);
  303 + if (ret) {
  304 + printf("%s: spi_flash erase failed.\n", __func__);
  305 + return 1;
  306 + }
  307 +
  308 + ret = spi_flash_write(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI,
  309 + sizeof(mac_string), mac_string);
  310 + if (ret) {
  311 + printf("%s: spi_flash write failed.\n", __func__);
  312 + spi_flash_free(spi);
  313 + return 1;
  314 + }
  315 + spi_flash_free(spi);
  316 +
  317 + puts("The writing of the MAC address to SPI ROM was completed.\n");
  318 +
  319 + return 0;
  320 +}
  321 +
  322 +U_BOOT_CMD(
  323 + write_mac, 3, 1, do_write_mac,
  324 + "write MAC address for GETHERC",
  325 + "[GETHERC ch0] [GETHERC ch1]\n"
  326 +);
board/renesas/sh7753evb/spi-boot.c
Diff comments   View file @ 320cf35
  1 +/*
  2 + * Copyright (C) 2013 Renesas Solutions Corp.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +
  9 +#define CONFIG_SPI_ADDR 0x00000000
  10 +#define PHYADDR(_addr) ((_addr & 0x1fffffff) | 0x40000000)
  11 +#define CONFIG_RAM_BOOT_PHYS PHYADDR(CONFIG_SYS_TEXT_BASE)
  12 +
  13 +#define SPIWDMADR 0xFE001018
  14 +#define SPIWDMCNTR 0xFE001020
  15 +#define SPIDMCOR 0xFE001028
  16 +#define SPIDMINTSR 0xFE001188
  17 +#define SPIDMINTMR 0xFE001190
  18 +
  19 +#define SPIDMINTSR_DMEND 0x00000004
  20 +
  21 +#define TBR 0xFE002000
  22 +#define RBR 0xFE002000
  23 +
  24 +#define CR1 0xFE002008
  25 +#define CR2 0xFE002010
  26 +#define CR3 0xFE002018
  27 +#define CR4 0xFE002020
  28 +#define CR7 0xFE002038
  29 +#define CR8 0xFE002040
  30 +
  31 +/* CR1 */
  32 +#define SPI_TBE 0x80
  33 +#define SPI_TBF 0x40
  34 +#define SPI_RBE 0x20
  35 +#define SPI_RBF 0x10
  36 +#define SPI_PFONRD 0x08
  37 +#define SPI_SSDB 0x04
  38 +#define SPI_SSD 0x02
  39 +#define SPI_SSA 0x01
  40 +
  41 +/* CR2 */
  42 +#define SPI_RSTF 0x80
  43 +#define SPI_LOOPBK 0x40
  44 +#define SPI_CPOL 0x20
  45 +#define SPI_CPHA 0x10
  46 +#define SPI_L1M0 0x08
  47 +
  48 +/* CR4 */
  49 +#define SPI_TBEI 0x80
  50 +#define SPI_TBFI 0x40
  51 +#define SPI_RBEI 0x20
  52 +#define SPI_RBFI 0x10
  53 +#define SPI_SpiS0 0x02
  54 +#define SPI_SSS 0x01
  55 +
  56 +/* CR7 */
  57 +#define CR7_IDX_OR12 0x12
  58 +#define OR12_ADDR32 0x00000001
  59 +
  60 +#define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val
  61 +#define spi_read(addr) (*(volatile unsigned long *)(addr))
  62 +
  63 +/* M25P80 */
  64 +#define M25_READ 0x03
  65 +#define M25_READ_4BYTE 0x13
  66 +
  67 +extern void bss_start(void);
  68 +
  69 +#define __uses_spiboot2 __attribute__((section(".spiboot2.text")))
  70 +static void __uses_spiboot2 spi_reset(void)
  71 +{
  72 + int timeout = 0x00100000;
  73 +
  74 + /* Make sure the last transaction is finalized */
  75 + spi_write(0x00, CR3);
  76 + spi_write(0x02, CR1);
  77 + while (!(spi_read(CR4) & SPI_SpiS0)) {
  78 + if (timeout-- < 0)
  79 + break;
  80 + }
  81 + spi_write(0x00, CR1);
  82 +
  83 + spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */
  84 + spi_write(spi_read(CR2) & ~SPI_RSTF, CR2);
  85 +
  86 + spi_write(0, SPIDMCOR);
  87 +}
  88 +
  89 +static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr,
  90 + unsigned long len)
  91 +{
  92 + spi_write(CR7_IDX_OR12, CR7);
  93 + if (spi_read(CR8) & OR12_ADDR32) {
  94 + /* 4-bytes address mode */
  95 + spi_write(M25_READ_4BYTE, TBR);
  96 + spi_write((addr >> 24) & 0xFF, TBR); /* ADDR31-24 */
  97 + } else {
  98 + /* 3-bytes address mode */
  99 + spi_write(M25_READ, TBR);
  100 + }
  101 + spi_write((addr >> 16) & 0xFF, TBR); /* ADDR23-16 */
  102 + spi_write((addr >> 8) & 0xFF, TBR); /* ADDR15-8 */
  103 + spi_write(addr & 0xFF, TBR); /* ADDR7-0 */
  104 +
  105 + spi_write(SPIDMINTSR_DMEND, SPIDMINTSR);
  106 + spi_write((unsigned long)buf, SPIWDMADR);
  107 + spi_write(len & 0xFFFFFFE0, SPIWDMCNTR);
  108 + spi_write(1, SPIDMCOR);
  109 +
  110 + spi_write(0xff, CR3);
  111 + spi_write(spi_read(CR1) | SPI_SSDB, CR1);
  112 + spi_write(spi_read(CR1) | SPI_SSA, CR1);
  113 +
  114 + while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND))
  115 + ;
  116 +
  117 + /* Nagate SP0-SS0 */
  118 + spi_write(0, CR1);
  119 +}
  120 +
  121 +void __uses_spiboot2 spiboot_main(void)
  122 +{
  123 + /*
  124 + * This code rounds len up for SPIWDMCNTR. We should set it to 0 in
  125 + * lower 5-bits.
  126 + */
  127 + void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE;
  128 + volatile unsigned long len = (bss_start - _start + 31) & 0xffffffe0;
  129 +
  130 + spi_reset();
  131 + spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR, len);
  132 +
  133 + _start();
  134 +}
board/renesas/sh7753evb/u-boot.lds
Diff comments   View file @ 320cf35
  1 +/*
  2 + * Copyright (C) 2007
  3 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
  4 + *
  5 + * Copyright (C) 2012
  6 + * Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
  12 +OUTPUT_ARCH(sh)
  13 +ENTRY(_start)
  14 +
  15 +SECTIONS
  16 +{
  17 + /*
  18 + * entry and reloct_dst will be provided via ldflags
  19 + */
  20 + . = .;
  21 +
  22 + PROVIDE (_ftext = .);
  23 + PROVIDE (_fcode = .);
  24 + PROVIDE (_start = .);
  25 +
  26 + .text :
  27 + {
  28 + KEEP(arch/sh/cpu/sh4/start.o (.text))
  29 + *(.spiboot1.text)
  30 + *(.spiboot2.text)
  31 + . = ALIGN(8192);
  32 + common/env_embedded.o (.ppcenv)
  33 + . = ALIGN(8192);
  34 + common/env_embedded.o (.ppcenvr)
  35 + . = ALIGN(8192);
  36 + *(.text)
  37 + . = ALIGN(4);
  38 + } =0xFF
  39 + PROVIDE (_ecode = .);
  40 + .rodata :
  41 + {
  42 + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
  43 + . = ALIGN(4);
  44 + }
  45 + PROVIDE (_etext = .);
  46 +
  47 +
  48 + PROVIDE (_fdata = .);
  49 + .data :
  50 + {
  51 + *(.data)
  52 + . = ALIGN(4);
  53 + }
  54 + PROVIDE (_edata = .);
  55 +
  56 + PROVIDE (_fgot = .);
  57 + .got :
  58 + {
  59 + *(.got)
  60 + . = ALIGN(4);
  61 + }
  62 + PROVIDE (_egot = .);
  63 +
  64 + .u_boot_list : {
  65 + KEEP(*(SORT(.u_boot_list*)));
  66 + }
  67 +
  68 + PROVIDE (reloc_dst_end = .);
  69 + /* _reloc_dst_end = .; */
  70 +
  71 + PROVIDE (bss_start = .);
  72 + PROVIDE (__bss_start = .);
  73 + .bss (NOLOAD) :
  74 + {
  75 + *(.bss)
  76 + . = ALIGN(4);
  77 + }
  78 + PROVIDE (bss_end = .);
  79 +
  80 + PROVIDE (__bss_end = .);
  81 +}
... ... @@ -1209,6 +1209,7 @@
1209 1209 Active sh sh4 - renesas r2dplus r2dplus - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
1210 1210 Active sh sh4 - renesas r7780mp r7780mp - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
1211 1211 Active sh sh4 - renesas sh7752evb sh7752evb - -
  1212 +Active sh sh4 - renesas sh7753evb sh7753evb - -
1212 1213 Active sh sh4 - renesas sh7757lcr sh7757lcr - -
1213 1214 Active sh sh4 - renesas sh7763rdp sh7763rdp - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
1214 1215 Active sh sh4 - renesas sh7785lcr sh7785lcr - -
doc/README.sh7753evb
Diff comments   View file @ 320cf35
  1 +========================================
  2 +Renesas SH7753 EVB board
  3 +========================================
  4 +
  5 +This board specification:
  6 +=========================
  7 +
  8 +The SH7753 EVB (board config name:sh7753evb) has the following device:
  9 +
  10 + - SH7753 (SH-4A)
  11 + - DDR3-SDRAM 512MB
  12 + - SPI ROM 8MB
  13 + - Gigabit Ethernet controllers
  14 + - eMMC 4GB
  15 +
  16 +
  17 +Configuration for This board:
  18 +=============================
  19 +
  20 +You can select the configuration as follows:
  21 +
  22 + - make sh7753evb_config
  23 +
  24 +
  25 +This board specific command:
  26 +============================
  27 +
  28 +This board has the following its specific command:
  29 +
  30 + - write_mac
  31 +
  32 +
  33 +1. write_mac
  34 +
  35 +You can write MAC address to SPI ROM.
  36 +
  37 + Usage 1) Write MAC address
  38 +
  39 + write_mac [GETHERC ch0] [GETHERC ch1]
  40 +
  41 + For example)
  42 + => write_mac 74:90:50:00:33:9e 74:90:50:00:33:9f
  43 + *) We have to input the command as a single line
  44 + (without carriage return)
  45 + *) We have to reset after input the command.
  46 +
  47 + Usage 2) Show current data
  48 +
  49 + write_mac
  50 +
  51 + For example)
  52 + => write_mac
  53 + GETHERC ch0 = 74:90:50:00:33:9e
  54 + GETHERC ch1 = 74:90:50:00:33:9f
  55 +
  56 +
  57 +Update SPI ROM:
  58 +============================
  59 +
  60 +1. Copy u-boot image to RAM area.
  61 +2. Probe SPI device.
  62 + => sf probe 0
  63 + SF: Detected MX25L6405D with page size 64KiB, total 8 MiB
  64 +3. Erase SPI ROM.
  65 + => sf erase 0 80000
  66 +4. Write u-boot image to SPI ROM.
  67 + => sf write 0x48000000 0 80000
include/configs/sh7753evb.h
Diff comments   View file @ 320cf35
  1 +/*
  2 + * Configuation settings for the sh7753evb board
  3 + *
  4 + * Copyright (C) 2012 Renesas Solutions Corp.
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef __SH7753EVB_H
  10 +#define __SH7753EVB_H
  11 +
  12 +#undef DEBUG
  13 +#define CONFIG_SH 1
  14 +#define CONFIG_SH4A 1
  15 +#define CONFIG_SH_32BIT 1
  16 +#define CONFIG_CPU_SH7753 1
  17 +#define CONFIG_SH7753EVB 1
  18 +
  19 +#define CONFIG_SYS_TEXT_BASE 0x5ff80000
  20 +#define CONFIG_SYS_LDSCRIPT "board/renesas/sh7753evb/u-boot.lds"
  21 +
  22 +#define CONFIG_CMD_MEMORY
  23 +#define CONFIG_CMD_NET
  24 +#define CONFIG_CMD_MII
  25 +#define CONFIG_CMD_PING
  26 +#define CONFIG_CMD_NFS
  27 +#define CONFIG_CMD_DFL
  28 +#define CONFIG_CMD_SDRAM
  29 +#define CONFIG_CMD_SF
  30 +#define CONFIG_CMD_RUN
  31 +#define CONFIG_CMD_SAVEENV
  32 +#define CONFIG_CMD_MD5SUM
  33 +#define CONFIG_MD5
  34 +#define CONFIG_CMD_LOADS
  35 +#define CONFIG_CMD_MMC
  36 +#define CONFIG_CMD_EXT2
  37 +#define CONFIG_DOS_PARTITION
  38 +#define CONFIG_MAC_PARTITION
  39 +
  40 +#define CONFIG_BAUDRATE 115200
  41 +#define CONFIG_BOOTDELAY 3
  42 +#define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp"
  43 +
  44 +#define CONFIG_VERSION_VARIABLE
  45 +#undef CONFIG_SHOW_BOOT_PROGRESS
  46 +#define CONFIG_CMDLINE_EDITING
  47 +#define CONFIG_AUTO_COMPLETE
  48 +
  49 +/* MEMORY */
  50 +#define SH7753EVB_SDRAM_BASE (0x40000000)
  51 +#define SH7753EVB_SDRAM_SIZE (512 * 1024 * 1024)
  52 +
  53 +#define CONFIG_SYS_LONGHELP
  54 +#define CONFIG_SYS_CBSIZE 256
  55 +#define CONFIG_SYS_PBSIZE 256
  56 +#define CONFIG_SYS_MAXARGS 16
  57 +#define CONFIG_SYS_BARGSIZE 512
  58 +#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
  59 +
  60 +/* SCIF */
  61 +#define CONFIG_SCIF_CONSOLE 1
  62 +#define CONFIG_CONS_SCIF2 1
  63 +#undef CONFIG_SYS_CONSOLE_INFO_QUIET
  64 +#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
  65 +#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
  66 +
  67 +#define CONFIG_SYS_MEMTEST_START (SH7753EVB_SDRAM_BASE)
  68 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
  69 + 480 * 1024 * 1024)
  70 +#undef CONFIG_SYS_ALT_MEMTEST
  71 +#undef CONFIG_SYS_MEMTEST_SCRATCH
  72 +#undef CONFIG_SYS_LOADS_BAUD_CHANGE
  73 +
  74 +#define CONFIG_SYS_SDRAM_BASE (SH7753EVB_SDRAM_BASE)
  75 +#define CONFIG_SYS_SDRAM_SIZE (SH7753EVB_SDRAM_SIZE)
  76 +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
  77 + 128 * 1024 * 1024)
  78 +
  79 +#define CONFIG_SYS_MONITOR_BASE 0x00000000
  80 +#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
  81 +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  82 +#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
  83 +
  84 +/* FLASH */
  85 +#define CONFIG_SYS_NO_FLASH
  86 +
  87 +/* Ether */
  88 +#define CONFIG_SH_ETHER 1
  89 +#define CONFIG_SH_ETHER_USE_PORT 0
  90 +#define CONFIG_SH_ETHER_PHY_ADDR 18
  91 +#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
  92 +#define CONFIG_SH_ETHER_USE_GETHER 1
  93 +#define CONFIG_PHYLIB
  94 +#define CONFIG_BITBANGMII
  95 +#define CONFIG_BITBANGMII_MULTI
  96 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
  97 +#define CONFIG_PHY_VITESSE
  98 +
  99 +#define SH7753EVB_ETHERNET_MAC_BASE_SPI 0x00090000
  100 +#define SH7753EVB_SPI_SECTOR_SIZE (64 * 1024)
  101 +#define SH7753EVB_ETHERNET_MAC_BASE SH7753EVB_ETHERNET_MAC_BASE_SPI
  102 +#define SH7753EVB_ETHERNET_MAC_SIZE 17
  103 +#define SH7753EVB_ETHERNET_NUM_CH 2
  104 +#define CONFIG_BOARD_LATE_INIT
  105 +
  106 +/* SPI */
  107 +#define CONFIG_SH_SPI 1
  108 +#define CONFIG_SH_SPI_BASE 0xfe002000
  109 +#define CONFIG_SPI_FLASH
  110 +#define CONFIG_SPI_FLASH_STMICRO 1
  111 +#define CONFIG_SPI_FLASH_MACRONIX 1
  112 +
  113 +/* MMCIF */
  114 +#define CONFIG_MMC 1
  115 +#define CONFIG_GENERIC_MMC 1
  116 +#define CONFIG_SH_MMCIF 1
  117 +#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
  118 +#define CONFIG_SH_MMCIF_CLK 48000000
  119 +
  120 +/* ENV setting */
  121 +#define CONFIG_ENV_IS_EMBEDDED
  122 +#define CONFIG_ENV_IS_IN_SPI_FLASH
  123 +#define CONFIG_ENV_SECT_SIZE (64 * 1024)
  124 +#define CONFIG_ENV_ADDR (0x00080000)
  125 +#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
  126 +#define CONFIG_ENV_OVERWRITE 1
  127 +#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
  128 +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
  129 +#define CONFIG_EXTRA_ENV_SETTINGS \
  130 + "netboot=bootp; bootm\0"
  131 +
  132 +/* Board Clock */
  133 +#define CONFIG_SYS_CLK_FREQ 48000000
  134 +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
  135 +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
  136 +#define CONFIG_SYS_TMU_CLK_DIV 4
  137 +#endif /* __SH7753EVB_H */