MIPS: initial infrastructure for Microchip PIC32 architecture

Create initial directory, Kconfigs needed for PIC32 architecture support. Also add PIC32 specific register definition required for drivers. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>

MIPS: initial infrastructure for Microchip PIC32 architecture
Create initial directory, Kconfigs needed for PIC32 architecture support. Also add PIC32 specific register definition required for drivers. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Purna Chandra Mandal · Daniel Schwierzeck
1 parent 91ec615e54
Showing 6 changed files with 110 additions and 0 deletions Side-by-side Diff
arch/mips/Kconfig
arch/mips/Makefile
arch/mips/mach-pic32/Kconfig
arch/mips/mach-pic32/Makefile
arch/mips/mach-pic32/cpu.c
arch/mips/mach-pic32/include/mach/pic32.h
@@ -55,6 +55,11 @@
 	select SYS_MIPS_CACHE_INIT_RAM_LOAD
 	select MIPS_TUNE_4KC
  
+config MACH_PIC32
+	bool "Support Microchip PIC32"
+	select OF_CONTROL
+	select DM
+
 endchoice
  
 source "board/dbau1x00/Kconfig"
@@ -62,6 +67,7 @@
 source "board/micronas/vct/Kconfig"
 source "board/pb1x00/Kconfig"
 source "board/qemu-mips/Kconfig"
+source "arch/mips/mach-pic32/Kconfig"
  
 if MIPS
  
@@ -8,6 +8,7 @@
 libs-y += arch/mips/lib/
  
 machine-$(CONFIG_SOC_AU1X00) += au1x00
+machine-$(CONFIG_MACH_PIC32) += pic32
  
 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
 libs-y += $(machdirs)
+menu "Microchip PIC32 platforms"
+	depends on MACH_PIC32
+
+config SYS_SOC
+	default "none"
+
+endmenu
+# (C) Copyright 2015
+# Purna Chandra Mandal, purna.mandal@microchip.com.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y = cpu.o
+/*
+ * Copyright (C) 2015
+ * Purna Chandra Mandal <purna.mandal@microchip.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+#include <common.h>
+
+phys_size_t initdram(int board_type)
+{
+	return 0;
+}
+/*
+ * (c) 2015 Paul Thacker <paul.thacker@microchip.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+#ifndef __PIC32_REGS_H__
+#define __PIC32_REGS_H__
+
+#include <asm/io.h>
+
+/* System Configuration */
+#define PIC32_CFG_BASE		0x1f800000
+
+/* System config register offsets */
+#define CFGCON		0x0000
+#define DEVID		0x0020
+#define SYSKEY		0x0030
+#define PMD1		0x0040
+#define PMD7		0x00a0
+#define CFGEBIA		0x00c0
+#define CFGEBIC		0x00d0
+#define CFGPG		0x00e0
+#define CFGMPLL		0x0100
+
+/* Non Volatile Memory (NOR flash) */
+#define PIC32_NVM_BASE		(PIC32_CFG_BASE + 0x0600)
+/* Oscillator Configuration */
+#define PIC32_OSC_BASE		(PIC32_CFG_BASE + 0x1200)
+/* Peripheral Pin Select Input */
+#define PPS_IN_BASE		0x1f801400
+/* Peripheral Pin Select Output */
+#define PPS_OUT_BASE		0x1f801500
+/* Pin Config */
+#define PINCTRL_BASE		0x1f860000
+
+/* USB Core */
+#define PIC32_USB_CORE_BASE	0x1f8e3000
+#define PIC32_USB_CTRL_BASE	0x1f884000
+
+/* SPI1-SPI6 */
+#define PIC32_SPI1_BASE		0x1f821000
+
+/* Prefetch Module */
+#define PREFETCH_BASE		0x1f8e0000
+
+/* DDR2 Controller */
+#define PIC32_DDR2C_BASE	0x1f8e8000
+
+/* DDR2 PHY */
+#define PIC32_DDR2P_BASE	0x1f8e9100
+
+/* EBI */
+#define PIC32_EBI_BASE		0x1f8e1000
+
+/* SQI */
+#define PIC32_SQI_BASE		0x1f8e2000
+
+struct pic32_reg_atomic {
+	u32 raw;
+	u32 clr;
+	u32 set;
+	u32 inv;
+};
+
+#define _CLR_OFFSET	0x04
+#define _SET_OFFSET	0x08
+#define _INV_OFFSET	0x0c
+
+static inline void __iomem *pic32_get_syscfg_base(void)
+{
+	return (void __iomem *)CKSEG1ADDR(PIC32_CFG_BASE);
+}
+
+#endif	/* __PIC32_REGS_H__ */
...	...	@@ -55,6 +55,11 @@
55	55	select SYS_MIPS_CACHE_INIT_RAM_LOAD
56	56	select MIPS_TUNE_4KC
57	57
	58	+config MACH_PIC32
	59	+ bool "Support Microchip PIC32"
	60	+ select OF_CONTROL
	61	+ select DM
	62	+
58	63	endchoice
59	64
60	65	source "board/dbau1x00/Kconfig"
...	...	@@ -62,6 +67,7 @@
62	67	source "board/micronas/vct/Kconfig"
63	68	source "board/pb1x00/Kconfig"
64	69	source "board/qemu-mips/Kconfig"
	70	+source "arch/mips/mach-pic32/Kconfig"
65	71
66	72	if MIPS
67	73
...	...	@@ -8,6 +8,7 @@
8	8	libs-y += arch/mips/lib/
9	9
10	10	machine-$(CONFIG_SOC_AU1X00) += au1x00
	11	+machine-$(CONFIG_MACH_PIC32) += pic32
11	12
12	13	machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
13	14	libs-y += $(machdirs)
	1	+menu "Microchip PIC32 platforms"
	2	+ depends on MACH_PIC32
	3	+
	4	+config SYS_SOC
	5	+ default "none"
	6	+
	7	+endmenu
	1	+# (C) Copyright 2015
	2	+# Purna Chandra Mandal, purna.mandal@microchip.com.
	3	+#
	4	+# SPDX-License-Identifier: GPL-2.0+
	5	+#
	6	+
	7	+obj-y = cpu.o
	1	+/*
	2	+ * Copyright (C) 2015
	3	+ * Purna Chandra Mandal <purna.mandal@microchip.com>
	4	+ *
	5	+ * SPDX-License-Identifier: GPL-2.0+
	6	+ *
	7	+ */
	8	+#include <common.h>
	9	+
	10	+phys_size_t initdram(int board_type)
	11	+{
	12	+ return 0;
	13	+}
	1	+/*
	2	+ * (c) 2015 Paul Thacker <paul.thacker@microchip.com>
	3	+ *
	4	+ * SPDX-License-Identifier: GPL-2.0+
	5	+ *
	6	+ */
	7	+
	8	+#ifndef __PIC32_REGS_H__
	9	+#define __PIC32_REGS_H__
	10	+
	11	+#include <asm/io.h>
	12	+
	13	+/* System Configuration */
	14	+#define PIC32_CFG_BASE 0x1f800000
	15	+
	16	+/* System config register offsets */
	17	+#define CFGCON 0x0000
	18	+#define DEVID 0x0020
	19	+#define SYSKEY 0x0030
	20	+#define PMD1 0x0040
	21	+#define PMD7 0x00a0
	22	+#define CFGEBIA 0x00c0
	23	+#define CFGEBIC 0x00d0
	24	+#define CFGPG 0x00e0
	25	+#define CFGMPLL 0x0100
	26	+
	27	+/* Non Volatile Memory (NOR flash) */
	28	+#define PIC32_NVM_BASE (PIC32_CFG_BASE + 0x0600)
	29	+/* Oscillator Configuration */
	30	+#define PIC32_OSC_BASE (PIC32_CFG_BASE + 0x1200)
	31	+/* Peripheral Pin Select Input */
	32	+#define PPS_IN_BASE 0x1f801400
	33	+/* Peripheral Pin Select Output */
	34	+#define PPS_OUT_BASE 0x1f801500
	35	+/* Pin Config */
	36	+#define PINCTRL_BASE 0x1f860000
	37	+
	38	+/* USB Core */
	39	+#define PIC32_USB_CORE_BASE 0x1f8e3000
	40	+#define PIC32_USB_CTRL_BASE 0x1f884000
	41	+
	42	+/* SPI1-SPI6 */
	43	+#define PIC32_SPI1_BASE 0x1f821000
	44	+
	45	+/* Prefetch Module */
	46	+#define PREFETCH_BASE 0x1f8e0000
	47	+
	48	+/* DDR2 Controller */
	49	+#define PIC32_DDR2C_BASE 0x1f8e8000
	50	+
	51	+/* DDR2 PHY */
	52	+#define PIC32_DDR2P_BASE 0x1f8e9100
	53	+
	54	+/* EBI */
	55	+#define PIC32_EBI_BASE 0x1f8e1000
	56	+
	57	+/* SQI */
	58	+#define PIC32_SQI_BASE 0x1f8e2000
	59	+
	60	+struct pic32_reg_atomic {
	61	+ u32 raw;
	62	+ u32 clr;
	63	+ u32 set;
	64	+ u32 inv;
	65	+};
	66	+
	67	+#define _CLR_OFFSET 0x04
	68	+#define _SET_OFFSET 0x08
	69	+#define _INV_OFFSET 0x0c
	70	+
	71	+static inline void __iomem *pic32_get_syscfg_base(void)
	72	+{
	73	+ return (void __iomem *)CKSEG1ADDR(PIC32_CFG_BASE);
	74	+}
	75	+
	76	+#endif /* __PIC32_REGS_H__ */