imx: consolidate set_chipselect_size function

Move MX5 specific set_chipselect_size function into generic i.MX part, such that MX6 based boards are able to use this function as well. While doing this the iomuxc gpr member needed to be consolidated between MX5 and MX6. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

imx: consolidate set_chipselect_size function
Move MX5 specific set_chipselect_size function into generic i.MX part, such that MX6 based boards are able to use this function as well. While doing this the iomuxc gpr member needed to be consolidated between MX5 and MX6. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Fabio Estevam · Stefano Babic
1 parent 53b7f18044
Showing 5 changed files with 39 additions and 41 deletions Side-by-side Diff
arch/arm/cpu/armv7/mx5/soc.c
arch/arm/imx-common/cpu.c
arch/arm/include/asm/arch-imx/cpu.h
arch/arm/include/asm/arch-mx5/imx-regs.h
arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -85,37 +85,6 @@
 }
 #endif
  
-void set_chipselect_size(int const cs_size)
-{
-	unsigned int reg;
-	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
-	reg = readl(&iomuxc_regs->gpr1);
-
-	switch (cs_size) {
-	case CS0_128:
-		reg &= ~0x7;	/* CS0=128MB, CS1=0, CS2=0, CS3=0 */
-		reg |= 0x5;
-		break;
-	case CS0_64M_CS1_64M:
-		reg &= ~0x3F;	/* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
-		reg |= 0x1B;
-		break;
-	case CS0_64M_CS1_32M_CS2_32M:
-		reg &= ~0x1FF;	/* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
-		reg |= 0x4B;
-		break;
-	case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
-		reg &= ~0xFFF;  /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
-		reg |= 0x249;
-		break;
-	default:
-		printf("Unknown chip select size: %d\n", cs_size);
-		break;
-	}
-
-	writel(reg, &iomuxc_regs->gpr1);
-}
-
 #ifdef CONFIG_MX53
 void boot_mode_apply(unsigned cfg_val)
 {
@@ -187,4 +187,35 @@
 	ipuv3_fb_shutdown();
 }
 #endif
+
+void set_chipselect_size(int const cs_size)
+{
+	unsigned int reg;
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	reg = readl(&iomuxc_regs->gpr[1]);
+
+	switch (cs_size) {
+	case CS0_128:
+		reg &= ~0x7;	/* CS0=128MB, CS1=0, CS2=0, CS3=0 */
+		reg |= 0x5;
+		break;
+	case CS0_64M_CS1_64M:
+		reg &= ~0x3F;	/* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
+		reg |= 0x1B;
+		break;
+	case CS0_64M_CS1_32M_CS2_32M:
+		reg &= ~0x1FF;	/* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
+		reg |= 0x4B;
+		break;
+	case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
+		reg &= ~0xFFF;  /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
+		reg |= 0x249;
+		break;
+	default:
+		printf("Unknown chip select size: %d\n", cs_size);
+		break;
+	}
+
+	writel(reg, &iomuxc_regs->gpr[1]);
+}
@@ -12,4 +12,9 @@
 #define MXC_CPU_MX6Q		0x63
 #define MXC_CPU_MX6D		0x64
 #define MXC_CPU_MX6SOLO		0x65 /* dummy ID */
+
+#define CS0_128					0
+#define CS0_64M_CS1_64M				1
+#define CS0_64M_CS1_32M_CS2_32M			2
+#define CS0_32M_CS1_32M_CS2_32M_CS3_32M		3
@@ -202,11 +202,6 @@
  */
 #define WBED		1
  
-#define CS0_128					0
-#define CS0_64M_CS1_64M				1
-#define CS0_64M_CS1_32M_CS2_32M			2
-#define CS0_32M_CS1_32M_CS2_32M_CS3_32M		3
-
 /*
  * CSPI register definitions
  */
@@ -414,8 +409,7 @@
  
 #if defined(CONFIG_MX51)
 struct iomuxc {
-	u32	gpr0;
-	u32	gpr1;
+	u32	gpr[2];
 	u32	omux0;
 	u32	omux1;
 	u32	omux2;
@@ -424,9 +418,7 @@
 };
 #elif defined(CONFIG_MX53)
 struct iomuxc {
-	u32	gpr0;
-	u32	gpr1;
-	u32	gpr2;
+	u32	gpr[3];
 	u32	omux0;
 	u32	omux1;
 	u32	omux2;
@@ -26,6 +26,7 @@
  
 const char *get_imx_type(u32 imxtype);
 unsigned imx_ddr_size(void);
+void set_chipselect_size(int const);
  
 /*
  * Initializes on-chip ethernet controllers.
...	...	@@ -85,37 +85,6 @@
85	85	}
86	86	#endif
87	87
88		-void set_chipselect_size(int const cs_size)
89		-{
90		- unsigned int reg;
91		- struct iomuxc iomuxc_regs = (struct iomuxc )IOMUXC_BASE_ADDR;
92		- reg = readl(&iomuxc_regs->gpr1);
93		-
94		- switch (cs_size) {
95		- case CS0_128:
96		- reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
97		- reg \|= 0x5;
98		- break;
99		- case CS0_64M_CS1_64M:
100		- reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
101		- reg \|= 0x1B;
102		- break;
103		- case CS0_64M_CS1_32M_CS2_32M:
104		- reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
105		- reg \|= 0x4B;
106		- break;
107		- case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
108		- reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
109		- reg \|= 0x249;
110		- break;
111		- default:
112		- printf("Unknown chip select size: %d\n", cs_size);
113		- break;
114		- }
115		-
116		- writel(reg, &iomuxc_regs->gpr1);
117		-}
118		-
119	88	#ifdef CONFIG_MX53
120	89	void boot_mode_apply(unsigned cfg_val)
121	90	{
...	...	@@ -187,4 +187,35 @@
187	187	ipuv3_fb_shutdown();
188	188	}
189	189	#endif
	190	+
	191	+void set_chipselect_size(int const cs_size)
	192	+{
	193	+ unsigned int reg;
	194	+ struct iomuxc iomuxc_regs = (struct iomuxc )IOMUXC_BASE_ADDR;
	195	+ reg = readl(&iomuxc_regs->gpr[1]);
	196	+
	197	+ switch (cs_size) {
	198	+ case CS0_128:
	199	+ reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
	200	+ reg \|= 0x5;
	201	+ break;
	202	+ case CS0_64M_CS1_64M:
	203	+ reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
	204	+ reg \|= 0x1B;
	205	+ break;
	206	+ case CS0_64M_CS1_32M_CS2_32M:
	207	+ reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
	208	+ reg \|= 0x4B;
	209	+ break;
	210	+ case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
	211	+ reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
	212	+ reg \|= 0x249;
	213	+ break;
	214	+ default:
	215	+ printf("Unknown chip select size: %d\n", cs_size);
	216	+ break;
	217	+ }
	218	+
	219	+ writel(reg, &iomuxc_regs->gpr[1]);
	220	+}
...	...	@@ -12,4 +12,9 @@
12	12	#define MXC_CPU_MX6Q 0x63
13	13	#define MXC_CPU_MX6D 0x64
14	14	#define MXC_CPU_MX6SOLO 0x65 /* dummy ID */
	15	+
	16	+#define CS0_128 0
	17	+#define CS0_64M_CS1_64M 1
	18	+#define CS0_64M_CS1_32M_CS2_32M 2
	19	+#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3
...	...	@@ -202,11 +202,6 @@
202	202	*/
203	203	#define WBED 1
204	204
205		-#define CS0_128 0
206		-#define CS0_64M_CS1_64M 1
207		-#define CS0_64M_CS1_32M_CS2_32M 2
208		-#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3
209		-
210	205	/*
211	206	* CSPI register definitions
212	207	*/
...	...	@@ -414,8 +409,7 @@
414	409
415	410	#if defined(CONFIG_MX51)
416	411	struct iomuxc {
417		- u32 gpr0;
418		- u32 gpr1;
	412	+ u32 gpr[2];
419	413	u32 omux0;
420	414	u32 omux1;
421	415	u32 omux2;
...	...	@@ -424,9 +418,7 @@
424	418	};
425	419	#elif defined(CONFIG_MX53)
426	420	struct iomuxc {
427		- u32 gpr0;
428		- u32 gpr1;
429		- u32 gpr2;
	421	+ u32 gpr[3];
430	422	u32 omux0;
431	423	u32 omux1;
432	424	u32 omux2;
...	...	@@ -26,6 +26,7 @@
26	26
27	27	const char *get_imx_type(u32 imxtype);
28	28	unsigned imx_ddr_size(void);
	29	+void set_chipselect_size(int const);
29	30
30	31	/*
31	32	* Initializes on-chip ethernet controllers.